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-rw-r--r--drivers/gpu/drm/i915/intel_psr.c4
1 files changed, 0 insertions, 4 deletions
diff --git a/drivers/gpu/drm/i915/intel_psr.c b/drivers/gpu/drm/i915/intel_psr.c
index c4a63712c68e..bc5ea2a6cf4c 100644
--- a/drivers/gpu/drm/i915/intel_psr.c
+++ b/drivers/gpu/drm/i915/intel_psr.c
@@ -283,10 +283,6 @@ static void hsw_psr_enable_source(struct intel_dp *intel_dp)
const uint32_t link_entry_time = EDP_PSR_MIN_LINK_ENTRY_TIME_8_LINES;
if (intel_dp->psr_dpcd[1] & DP_PSR_NO_TRAIN_ON_EXIT) {
- /* It doesn't mean we shouldn't send TPS patters, so let's
- send the minimal TP1 possible and skip TP2. */
- val |= EDP_PSR_TP1_TIME_100us;
- val |= EDP_PSR_TP2_TP3_TIME_0us;
/* Sink should be able to train with the 5 or 6 idle patterns */
idle_frames += 4;
}