diff options
Diffstat (limited to 'drivers/gpu/drm/amd/amdgpu/umc_v6_1.c')
| -rw-r--r-- | drivers/gpu/drm/amd/amdgpu/umc_v6_1.c | 10 |
1 files changed, 5 insertions, 5 deletions
diff --git a/drivers/gpu/drm/amd/amdgpu/umc_v6_1.c b/drivers/gpu/drm/amd/amdgpu/umc_v6_1.c index 64df37b860dd..8502e736f721 100644 --- a/drivers/gpu/drm/amd/amdgpu/umc_v6_1.c +++ b/drivers/gpu/drm/amd/amdgpu/umc_v6_1.c @@ -116,7 +116,7 @@ static void umc_v6_1_query_correctable_error_count(struct amdgpu_device *adev, /* check for SRAM correctable error MCUMC_STATUS is a 64 bit register */ - mc_umc_status = RREG64(mc_umc_status_addr + umc_reg_offset); + mc_umc_status = RREG64_UMC(mc_umc_status_addr + umc_reg_offset); if (REG_GET_FIELD(mc_umc_status, MCA_UMC_UMC0_MCUMC_STATUST0, ErrorCodeExt) == 6 && REG_GET_FIELD(mc_umc_status, MCA_UMC_UMC0_MCUMC_STATUST0, Val) == 1 && REG_GET_FIELD(mc_umc_status, MCA_UMC_UMC0_MCUMC_STATUST0, CECC) == 1) @@ -134,7 +134,7 @@ static void umc_v6_1_querry_uncorrectable_error_count(struct amdgpu_device *adev SOC15_REG_OFFSET(UMC, 0, mmMCA_UMC_UMC0_MCUMC_STATUST0); /* check the MCUMC_STATUS */ - mc_umc_status = RREG64(mc_umc_status_addr + umc_reg_offset); + mc_umc_status = RREG64_UMC(mc_umc_status_addr + umc_reg_offset); if ((REG_GET_FIELD(mc_umc_status, MCA_UMC_UMC0_MCUMC_STATUST0, Val) == 1) && (REG_GET_FIELD(mc_umc_status, MCA_UMC_UMC0_MCUMC_STATUST0, Deferred) == 1 || REG_GET_FIELD(mc_umc_status, MCA_UMC_UMC0_MCUMC_STATUST0, UECC) == 1 || @@ -173,11 +173,11 @@ static void umc_v6_1_query_error_address(struct amdgpu_device *adev, /* skip error address process if -ENOMEM */ if (!err_data->err_addr) { /* clear umc status */ - WREG64(mc_umc_status_addr + umc_reg_offset, 0x0ULL); + WREG64_UMC(mc_umc_status_addr + umc_reg_offset, 0x0ULL); return; } - mc_umc_status = RREG64(mc_umc_status_addr + umc_reg_offset); + mc_umc_status = RREG64_UMC(mc_umc_status_addr + umc_reg_offset); /* calculate error address if ue/ce error is detected */ if (REG_GET_FIELD(mc_umc_status, MCA_UMC_UMC0_MCUMC_STATUST0, Val) == 1 && @@ -200,7 +200,7 @@ static void umc_v6_1_query_error_address(struct amdgpu_device *adev, } /* clear umc status */ - WREG64(mc_umc_status_addr + umc_reg_offset, 0x0ULL); + WREG64_UMC(mc_umc_status_addr + umc_reg_offset, 0x0ULL); } static void umc_v6_1_query_ras_error_address(struct amdgpu_device *adev, |