diff options
Diffstat (limited to 'arch')
469 files changed, 14870 insertions, 8558 deletions
diff --git a/arch/alpha/kernel/ptrace.c b/arch/alpha/kernel/ptrace.c index d9ee81769899..940dfb406591 100644 --- a/arch/alpha/kernel/ptrace.c +++ b/arch/alpha/kernel/ptrace.c @@ -157,14 +157,16 @@ put_reg(struct task_struct *task, unsigned long regno, unsigned long data) static inline int read_int(struct task_struct *task, unsigned long addr, int * data) { - int copied = access_process_vm(task, addr, data, sizeof(int), 0); + int copied = access_process_vm(task, addr, data, sizeof(int), + FOLL_FORCE); return (copied == sizeof(int)) ? 0 : -EIO; } static inline int write_int(struct task_struct *task, unsigned long addr, int data) { - int copied = access_process_vm(task, addr, &data, sizeof(int), 1); + int copied = access_process_vm(task, addr, &data, sizeof(int), + FOLL_FORCE | FOLL_WRITE); return (copied == sizeof(int)) ? 0 : -EIO; } @@ -281,7 +283,8 @@ long arch_ptrace(struct task_struct *child, long request, /* When I and D space are separate, these will need to be fixed. */ case PTRACE_PEEKTEXT: /* read word at location addr. */ case PTRACE_PEEKDATA: - copied = access_process_vm(child, addr, &tmp, sizeof(tmp), 0); + copied = access_process_vm(child, addr, &tmp, sizeof(tmp), + FOLL_FORCE); ret = -EIO; if (copied != sizeof(tmp)) break; diff --git a/arch/arc/Kconfig b/arch/arc/Kconfig index ecd12379e2cd..bd204bfa29ed 100644 --- a/arch/arc/Kconfig +++ b/arch/arc/Kconfig @@ -41,6 +41,8 @@ config ARC select PERF_USE_VMALLOC select HAVE_DEBUG_STACKOVERFLOW select HAVE_GENERIC_DMA_COHERENT + select HAVE_KERNEL_GZIP + select HAVE_KERNEL_LZMA config MIGHT_HAVE_PCI bool @@ -186,14 +188,6 @@ if SMP config ARC_HAS_COH_CACHES def_bool n -config ARC_MCIP - bool "ARConnect Multicore IP (MCIP) Support " - depends on ISA_ARCV2 - help - This IP block enables SMP in ARC-HS38 cores. - It provides for cross-core interrupts, multi-core debug - hardware semaphores, shared memory,.... - config NR_CPUS int "Maximum number of CPUs (2-4096)" range 2 4096 @@ -211,6 +205,15 @@ config ARC_SMP_HALT_ON_RESET endif #SMP +config ARC_MCIP + bool "ARConnect Multicore IP (MCIP) Support " + depends on ISA_ARCV2 + default y if SMP + help + This IP block enables SMP in ARC-HS38 cores. + It provides for cross-core interrupts, multi-core debug + hardware semaphores, shared memory,.... + menuconfig ARC_CACHE bool "Enable Cache Support" default y @@ -537,14 +540,6 @@ config ARC_DBG_TLB_PARANOIA bool "Paranoia Checks in Low Level TLB Handlers" default n -config ARC_DBG_TLB_MISS_COUNT - bool "Profile TLB Misses" - default n - select DEBUG_FS - help - Counts number of I and D TLB Misses and exports them via Debugfs - The counters can be cleared via Debugfs as well - endif config ARC_UBOOT_SUPPORT diff --git a/arch/arc/Makefile b/arch/arc/Makefile index aa82d13d4213..864adad52280 100644 --- a/arch/arc/Makefile +++ b/arch/arc/Makefile @@ -50,9 +50,6 @@ atleast_gcc44 := $(call cc-ifversion, -ge, 0404, y) cflags-$(atleast_gcc44) += -fsection-anchors -cflags-$(CONFIG_ARC_HAS_LLSC) += -mlock -cflags-$(CONFIG_ARC_HAS_SWAPE) += -mswape - ifdef CONFIG_ISA_ARCV2 ifndef CONFIG_ARC_HAS_LL64 diff --git a/arch/arc/boot/Makefile b/arch/arc/boot/Makefile index e597cb34c16a..f94cf151e06a 100644 --- a/arch/arc/boot/Makefile +++ b/arch/arc/boot/Makefile @@ -14,9 +14,15 @@ UIMAGE_ENTRYADDR = $(LINUX_START_TEXT) suffix-y := bin suffix-$(CONFIG_KERNEL_GZIP) := gz +suffix-$(CONFIG_KERNEL_LZMA) := lzma -targets += uImage uImage.bin uImage.gz -extra-y += vmlinux.bin vmlinux.bin.gz +targets += uImage +targets += uImage.bin +targets += uImage.gz +targets += uImage.lzma +extra-y += vmlinux.bin +extra-y += vmlinux.bin.gz +extra-y += vmlinux.bin.lzma $(obj)/vmlinux.bin: vmlinux FORCE $(call if_changed,objcopy) @@ -24,12 +30,18 @@ $(obj)/vmlinux.bin: vmlinux FORCE $(obj)/vmlinux.bin.gz: $(obj)/vmlinux.bin FORCE $(call if_changed,gzip) +$(obj)/vmlinux.bin.lzma: $(obj)/vmlinux.bin FORCE + $(call if_changed,lzma) + $(obj)/uImage.bin: $(obj)/vmlinux.bin FORCE $(call if_changed,uimage,none) $(obj)/uImage.gz: $(obj)/vmlinux.bin.gz FORCE $(call if_changed,uimage,gzip) +$(obj)/uImage.lzma: $(obj)/vmlinux.bin.lzma FORCE + $(call if_changed,uimage,lzma) + $(obj)/uImage: $(obj)/uImage.$(suffix-y) @ln -sf $(notdir $<) $@ @echo ' Image $@ is ready' diff --git a/arch/arc/include/asm/arcregs.h b/arch/arc/include/asm/arcregs.h index db25c65155cb..7f3f9f63708c 100644 --- a/arch/arc/include/asm/arcregs.h +++ b/arch/arc/include/asm/arcregs.h @@ -349,10 +349,11 @@ struct cpuinfo_arc { struct cpuinfo_arc_bpu bpu; struct bcr_identity core; struct bcr_isa isa; + const char *details, *name; unsigned int vec_base; struct cpuinfo_arc_ccm iccm, dccm; struct { - unsigned int swap:1, norm:1, minmax:1, barrel:1, crc:1, pad1:3, + unsigned int swap:1, norm:1, minmax:1, barrel:1, crc:1, swape:1, pad1:2, fpu_sp:1, fpu_dp:1, pad2:6, debug:1, ap:1, smart:1, rtt:1, pad3:4, timer0:1, timer1:1, rtc:1, gfrc:1, pad4:4; diff --git a/arch/arc/include/asm/cache.h b/arch/arc/include/asm/cache.h index fb781e34f322..b3410ff6a62d 100644 --- a/arch/arc/include/asm/cache.h +++ b/arch/arc/include/asm/cache.h @@ -53,7 +53,7 @@ extern void arc_cache_init(void); extern char *arc_cache_mumbojumbo(int cpu_id, char *buf, int len); extern void read_decode_cache_bcr(void); -extern int ioc_exists; +extern int ioc_enable; extern unsigned long perip_base, perip_end; #endif /* !__ASSEMBLY__ */ diff --git a/arch/arc/include/asm/elf.h b/arch/arc/include/asm/elf.h index 7096f97a1434..aa2d6da9d187 100644 --- a/arch/arc/include/asm/elf.h +++ b/arch/arc/include/asm/elf.h @@ -54,7 +54,7 @@ extern int elf_check_arch(const struct elf32_hdr *); * the loader. We need to make sure that it is out of the way of the program * that it will "exec", and that there is sufficient room for the brk. */ -#define ELF_ET_DYN_BASE (2 * TASK_SIZE / 3) +#define ELF_ET_DYN_BASE (2UL * TASK_SIZE / 3) /* * When the program starts, a1 contains a pointer to a function to be diff --git a/arch/arc/include/asm/mcip.h b/arch/arc/include/asm/mcip.h index 847e3bbe387f..c8fbe4114bad 100644 --- a/arch/arc/include/asm/mcip.h +++ b/arch/arc/include/asm/mcip.h @@ -55,6 +55,22 @@ struct mcip_cmd { #define IDU_M_DISTRI_DEST 0x2 }; +struct mcip_bcr { +#ifdef CONFIG_CPU_BIG_ENDIAN + unsigned int pad3:8, + idu:1, llm:1, num_cores:6, + iocoh:1, gfrc:1, dbg:1, pad2:1, + msg:1, sem:1, ipi:1, pad:1, + ver:8; +#else + unsigned int ver:8, + pad:1, ipi:1, sem:1, msg:1, + pad2:1, dbg:1, gfrc:1, iocoh:1, + num_cores:6, llm:1, idu:1, + pad3:8; +#endif +}; + /* * MCIP programming model * diff --git a/arch/arc/include/asm/module.h b/arch/arc/include/asm/module.h index 518222bb3f8e..6e91d8b339c3 100644 --- a/arch/arc/include/asm/module.h +++ b/arch/arc/include/asm/module.h @@ -18,6 +18,7 @@ struct mod_arch_specific { void *unw_info; int unw_sec_idx; + const char *secstr; }; #endif diff --git a/arch/arc/include/asm/setup.h b/arch/arc/include/asm/setup.h index 48b37c693db3..cb954cdab070 100644 --- a/arch/arc/include/asm/setup.h +++ b/arch/arc/include/asm/setup.h @@ -27,11 +27,6 @@ struct id_to_str { const char *str; }; -struct cpuinfo_data { - struct id_to_str info; - int up_range; -}; - extern int root_mountflags, end_mem; void setup_processor(void); @@ -43,5 +38,6 @@ void __init setup_arch_memory(void); #define IS_USED_RUN(v) ((v) ? "" : "(not used) ") #define IS_USED_CFG(cfg) IS_USED_RUN(IS_ENABLED(cfg)) #define IS_AVAIL2(v, s, cfg) IS_AVAIL1(v, s), IS_AVAIL1(v, IS_USED_CFG(cfg)) +#define IS_AVAIL3(v, v2, s) IS_AVAIL1(v, s), IS_AVAIL1(v, IS_DISABLED_RUN(v2)) #endif /* __ASMARC_SETUP_H */ diff --git a/arch/arc/include/asm/syscalls.h b/arch/arc/include/asm/syscalls.h index e56f9fcc5581..772b67ca56e7 100644 --- a/arch/arc/include/asm/syscalls.h +++ b/arch/arc/include/asm/syscalls.h @@ -17,6 +17,7 @@ int sys_clone_wrapper(int, int, int, int, int); int sys_cacheflush(uint32_t, uint32_t uint32_t); int sys_arc_settls(void *); int sys_arc_gettls(void); +int sys_arc_usr_cmpxchg(int *, int, int); #include <asm-generic/syscalls.h> diff --git a/arch/arc/include/uapi/asm/unistd.h b/arch/arc/include/uapi/asm/unistd.h index 41fa2ec9e02c..9a34136d84b2 100644 --- a/arch/arc/include/uapi/asm/unistd.h +++ b/arch/arc/include/uapi/asm/unistd.h @@ -27,18 +27,19 @@ #define NR_syscalls __NR_syscalls +/* Generic syscall (fs/filesystems.c - lost in asm-generic/unistd.h */ +#define __NR_sysfs (__NR_arch_specific_syscall + 3) + /* ARC specific syscall */ #define __NR_cacheflush (__NR_arch_specific_syscall + 0) #define __NR_arc_settls (__NR_arch_specific_syscall + 1) #define __NR_arc_gettls (__NR_arch_specific_syscall + 2) +#define __NR_arc_usr_cmpxchg (__NR_arch_specific_syscall + 4) __SYSCALL(__NR_cacheflush, sys_cacheflush) __SYSCALL(__NR_arc_settls, sys_arc_settls) __SYSCALL(__NR_arc_gettls, sys_arc_gettls) - - -/* Generic syscall (fs/filesystems.c - lost in asm-generic/unistd.h */ -#define __NR_sysfs (__NR_arch_specific_syscall + 3) +__SYSCALL(__NR_arc_usr_cmpxchg, sys_arc_usr_cmpxchg) __SYSCALL(__NR_sysfs, sys_sysfs) #undef __SYSCALL diff --git a/arch/arc/kernel/mcip.c b/arch/arc/kernel/mcip.c index 72f9179b1a24..c424d5abc318 100644 --- a/arch/arc/kernel/mcip.c +++ b/arch/arc/kernel/mcip.c @@ -15,11 +15,12 @@ #include <asm/mcip.h> #include <asm/setup.h> -static char smp_cpuinfo_buf[128]; -static int idu_detected; - static DEFINE_RAW_SPINLOCK(mcip_lock); +#ifdef CONFIG_SMP + +static char smp_cpuinfo_buf[128]; + static void mcip_setup_per_cpu(int cpu) { smp_ipi_irq_setup(cpu, IPI_IRQ); @@ -86,21 +87,7 @@ static void mcip_ipi_clear(int irq) static void mcip_probe_n_setup(void) { - struct mcip_bcr { -#ifdef CONFIG_CPU_BIG_ENDIAN - unsigned int pad3:8, - idu:1, llm:1, num_cores:6, - iocoh:1, gfrc:1, dbg:1, pad2:1, - msg:1, sem:1, ipi:1, pad:1, - ver:8; -#else - unsigned int ver:8, - pad:1, ipi:1, sem:1, msg:1, - pad2:1, dbg:1, gfrc:1, iocoh:1, - num_cores:6, llm:1, idu:1, - pad3:8; -#endif - } mp; + struct mcip_bcr mp; READ_BCR(ARC_REG_MCIP_BCR, mp); @@ -114,7 +101,6 @@ static void mcip_probe_n_setup(void) IS_AVAIL1(mp.gfrc, "GFRC")); cpuinfo_arc700[0].extn.gfrc = mp.gfrc; - idu_detected = mp.idu; if (mp.dbg) { __mcip_cmd_data(CMD_DEBUG_SET_SELECT, 0, 0xf); @@ -130,6 +116,8 @@ struct plat_smp_ops plat_smp_ops = { .ipi_clear = mcip_ipi_clear, }; +#endif + /*************************************************************************** * ARCv2 Interrupt Distribution Unit (IDU) * @@ -295,8 +283,11 @@ idu_of_init(struct device_node *intc, struct device_node *parent) /* Read IDU BCR to confirm nr_irqs */ int nr_irqs = of_irq_count(intc); int i, irq; + struct mcip_bcr mp; + + READ_BCR(ARC_REG_MCIP_BCR, mp); - if (!idu_detected) + if (!mp.idu) panic("IDU not detected, but DeviceTree using it"); pr_info("MCIP: IDU referenced from Devicetree %d irqs\n", nr_irqs); diff --git a/arch/arc/kernel/module.c b/arch/arc/kernel/module.c index 9a2849756022..42e964db2967 100644 --- a/arch/arc/kernel/module.c +++ b/arch/arc/kernel/module.c @@ -30,17 +30,9 @@ int module_frob_arch_sections(Elf_Ehdr *hdr, Elf_Shdr *sechdrs, char *secstr, struct module *mod) { #ifdef CONFIG_ARC_DW2_UNWIND - int i; - mod->arch.unw_sec_idx = 0; mod->arch.unw_info = NULL; - - for (i = 1; i < hdr->e_shnum; i++) { - if (strcmp(secstr+sechdrs[i].sh_name, ".eh_frame") == 0) { - mod->arch.unw_sec_idx = i; - break; - } - } + mod->arch.secstr = secstr; #endif return 0; } @@ -59,29 +51,33 @@ int apply_relocate_add(Elf32_Shdr *sechdrs, unsigned int relsec, /* sec index for relo sec */ struct module *module) { - int i, n; + int i, n, relo_type; Elf32_Rela *rel_entry = (void *)sechdrs[relsec].sh_addr; Elf32_Sym *sym_entry, *sym_sec; - Elf32_Addr relocation; - Elf32_Addr location; - Elf32_Addr sec_to_patch; - int relo_type; - - sec_to_patch = sechdrs[sechdrs[relsec].sh_info].sh_addr; + Elf32_Addr relocation, location, tgt_addr; + unsigned int tgtsec; + + /* + * @relsec has relocations e.g. .rela.init.text + * @tgtsec is section to patch e.g. .init.text + */ + tgtsec = sechdrs[relsec].sh_info; + tgt_addr = sechdrs[tgtsec].sh_addr; sym_sec = (Elf32_Sym *) sechdrs[symindex].sh_addr; n = sechdrs[relsec].sh_size / sizeof(*rel_entry); - pr_debug("\n========== Module Sym reloc ===========================\n"); - pr_debug("Section to fixup %x\n", sec_to_patch); + pr_debug("\nSection to fixup %s @%x\n", + module->arch.secstr + sechdrs[tgtsec].sh_name, tgt_addr); pr_debug("=========================================================\n"); - pr_debug("rela->r_off | rela->addend | sym->st_value | ADDR | VALUE\n"); + pr_debug("r_off\tr_add\tst_value ADDRESS VALUE\n"); pr_debug("=========================================================\n"); /* Loop thru entries in relocation section */ for (i = 0; i < n; i++) { + const char *s; /* This is where to make the change */ - location = sec_to_patch + rel_entry[i].r_offset; + location = tgt_addr + rel_entry[i].r_offset; /* This is the symbol it is referring to. Note that all undefined symbols have been resolved. */ @@ -89,10 +85,15 @@ int apply_relocate_add(Elf32_Shdr *sechdrs, relocation = sym_entry->st_value + rel_entry[i].r_addend; - pr_debug("\t%x\t\t%x\t\t%x %x %x [%s]\n", - rel_entry[i].r_offset, rel_entry[i].r_addend, - sym_entry->st_value, location, relocation, - strtab + sym_entry->st_name); + if (sym_entry->st_name == 0 && ELF_ST_TYPE (sym_entry->st_info) == STT_SECTION) { + s = module->arch.secstr + sechdrs[sym_entry->st_shndx].sh_name; + } else { + s = strtab + sym_entry->st_name; + } + + pr_debug(" %x\t%x\t%x %x %x [%s]\n", + rel_entry[i].r_offset, rel_entry[i].r_addend, + sym_entry->st_value, location, relocation, s); /* This assumes modules are built with -mlong-calls * so any branches/jumps are absolute 32 bit jmps @@ -111,6 +112,10 @@ int apply_relocate_add(Elf32_Shdr *sechdrs, goto relo_err; } + + if (strcmp(module->arch.secstr+sechdrs[tgtsec].sh_name, ".eh_frame") == 0) + module->arch.unw_sec_idx = tgtsec; + return 0; relo_err: diff --git a/arch/arc/kernel/process.c b/arch/arc/kernel/process.c index be1972bd2729..59aa43cb146e 100644 --- a/arch/arc/kernel/process.c +++ b/arch/arc/kernel/process.c @@ -41,6 +41,39 @@ SYSCALL_DEFINE0(arc_gettls) return task_thread_info(current)->thr_ptr; } +SYSCALL_DEFINE3(arc_usr_cmpxchg, int *, uaddr, int, expected, int, new) +{ + int uval; + int ret; + + /* + * This is only for old cores lacking LLOCK/SCOND, which by defintion + * can't possibly be SMP. Thus doesn't need to be SMP safe. + * And this also helps reduce the overhead for serializing in + * the UP case + */ + WARN_ON_ONCE(IS_ENABLED(CONFIG_SMP)); + + if (!access_ok(VERIFY_WRITE, uaddr, sizeof(int))) + return -EFAULT; + + preempt_disable(); + + ret = __get_user(uval, uaddr); + if (ret) + goto done; + + if (uval != expected) + ret = -EAGAIN; + else + ret = __put_user(new, uaddr); + +done: + preempt_enable(); + + return ret; +} + void arch_cpu_idle(void) { /* sleep, but enable all interrupts before committing */ diff --git a/arch/arc/kernel/setup.c b/arch/arc/kernel/setup.c index 3df7f9c72f42..0385df77a697 100644 --- a/arch/arc/kernel/setup.c +++ b/arch/arc/kernel/setup.c @@ -40,6 +40,29 @@ struct task_struct *_current_task[NR_CPUS]; /* For stack switching */ struct cpuinfo_arc cpuinfo_arc700[NR_CPUS]; +static const struct id_to_str arc_cpu_rel[] = { +#ifdef CONFIG_ISA_ARCOMPACT + { 0x34, "R4.10"}, + { 0x35, "R4.11"}, +#else + { 0x51, "R2.0" }, + { 0x52, "R2.1" }, + { 0x53, "R3.0" }, +#endif + { 0x00, NULL } +}; + +static const struct id_to_str arc_cpu_nm[] = { +#ifdef CONFIG_ISA_ARCOMPACT + { 0x20, "ARC 600" }, + { 0x30, "ARC 770" }, /* 750 identified seperately */ +#else + { 0x40, "ARC EM" }, + { 0x50, "ARC HS38" }, +#endif + { 0x00, "Unknown" } +}; + static void read_decode_ccm_bcr(struct cpuinfo_arc *cpu) { if (is_isa_arcompact()) { @@ -92,11 +115,26 @@ static void read_arc_build_cfg_regs(void) struct bcr_timer timer; struct bcr_generic bcr; struct cpuinfo_arc *cpu = &cpuinfo_arc700[smp_processor_id()]; + const struct id_to_str *tbl; + FIX_PTR(cpu); READ_BCR(AUX_IDENTITY, cpu->core); READ_BCR(ARC_REG_ISA_CFG_BCR, cpu->isa); + for (tbl = &arc_cpu_rel[0]; tbl->id != 0; tbl++) { + if (cpu->core.family == tbl->id) { + cpu->details = tbl->str; + break; + } + } + + for (tbl = &arc_cpu_nm[0]; tbl->id != 0; tbl++) { + if ((cpu->core.family & 0xF0) == tbl->id) + break; + } + cpu->name = tbl->str; + READ_BCR(ARC_REG_TIMERS_BCR, timer); cpu->extn.timer0 = timer.t0; cpu->extn.timer1 = timer.t1; @@ -111,6 +149,9 @@ static void read_arc_build_cfg_regs(void) cpu->extn.swap = read_aux_reg(ARC_REG_SWAP_BCR) ? 1 : 0; /* 1,3 */ cpu->extn.crc = read_aux_reg(ARC_REG_CRC_BCR) ? 1 : 0; cpu->extn.minmax = read_aux_reg(ARC_REG_MIXMAX_BCR) > 1 ? 1 : 0; /* 2 */ + cpu->extn.swape = (cpu->core.family >= 0x34) ? 1 : + IS_ENABLED(CONFIG_ARC_HAS_SWAPE); + READ_BCR(ARC_REG_XY_MEM_BCR, cpu->extn_xymem); /* Read CCM BCRs for boot reporting even if not enabled in Kconfig */ @@ -160,64 +201,38 @@ static void read_arc_build_cfg_regs(void) cpu->extn.rtt = bcr.ver ? 1 : 0; cpu->extn.debug = cpu->extn.ap | cpu->extn.smart | cpu->extn.rtt; -} -static const struct cpuinfo_data arc_cpu_tbl[] = { -#ifdef CONFIG_ISA_ARCOMPACT - { {0x20, "ARC 600" }, 0x2F}, - { {0x30, "ARC 700" }, 0x33}, - { {0x34, "ARC 700 R4.10"}, 0x34}, - { {0x35, "ARC 700 R4.11"}, 0x35}, -#else - { {0x50, "ARC HS38 R2.0"}, 0x51}, - { {0x52, "ARC HS38 R2.1"}, 0x52}, - { {0x53, "ARC HS38 R3.0"}, 0x53}, -#endif - { {0x00, NULL } } -}; + /* some hacks for lack of feature BCR info in old ARC700 cores */ + if (is_isa_arcompact()) { + if (!cpu->isa.ver) /* ISA BCR absent, use Kconfig info */ + cpu->isa.atomic = IS_ENABLED(CONFIG_ARC_HAS_LLSC); + else + cpu->isa.atomic = cpu->isa.atomic1; + cpu->isa.be = IS_ENABLED(CONFIG_CPU_BIG_ENDIAN); + + /* there's no direct way to distinguish 750 vs. 770 */ + if (unlikely(cpu->core.family < 0x34 || cpu->mmu.ver < 3)) + cpu->name = "ARC750"; + } +} static char *arc_cpu_mumbojumbo(int cpu_id, char *buf, int len) { struct cpuinfo_arc *cpu = &cpuinfo_arc700[cpu_id]; struct bcr_identity *core = &cpu->core; - const struct cpuinfo_data *tbl; - char *isa_nm; - int i, be, atomic; - int n = 0; + int i, n = 0; FIX_PTR(cpu); - if (is_isa_arcompact()) { - isa_nm = "ARCompact"; - be = IS_ENABLED(CONFIG_CPU_BIG_ENDIAN); - - atomic = cpu->isa.atomic1; - if (!cpu->isa.ver) /* ISA BCR absent, use Kconfig info */ - atomic = IS_ENABLED(CONFIG_ARC_HAS_LLSC); - } else { - isa_nm = "ARCv2"; - be = cpu->isa.be; - atomic = cpu->isa.atomic; - } - n += scnprintf(buf + n, len - n, "\nIDENTITY\t: ARCVER [%#02x] ARCNUM [%#02x] CHIPID [%#4x]\n", core->family, core->cpu_id, core->chip_id); - for (tbl = &arc_cpu_tbl[0]; tbl->info.id != 0; tbl++) { - if ((core->family >= tbl->info.id) && - (core->family <= tbl->up_range)) { - n += scnprintf(buf + n, len - n, - "processor [%d]\t: %s (%s ISA) %s\n", - cpu_id, tbl->info.str, isa_nm, - IS_AVAIL1(be, "[Big-Endian]")); - break; - } - } - - if (tbl->info.id == 0) - n += scnprintf(buf + n, len - n, "UNKNOWN ARC Processor\n"); + n += scnprintf(buf + n, len - n, "processor [%d]\t: %s %s (%s ISA) %s\n", + cpu_id, cpu->name, cpu->details, + is_isa_arcompact() ? "ARCompact" : "ARCv2", + IS_AVAIL1(cpu->isa.be, "[Big-Endian]")); n += scnprintf(buf + n, len - n, "Timers\t\t: %s%s%s%s\nISA Extn\t: ", IS_AVAIL1(cpu->extn.timer0, "Timer0 "), @@ -226,7 +241,7 @@ static char *arc_cpu_mumbojumbo(int cpu_id, char *buf, int len) CONFIG_ARC_HAS_RTC)); n += i = scnprintf(buf + n, len - n, "%s%s%s%s%s", - IS_AVAIL2(atomic, "atomic ", CONFIG_ARC_HAS_LLSC), + IS_AVAIL2(cpu->isa.atomic, "atomic ", CONFIG_ARC_HAS_LLSC), IS_AVAIL2(cpu->isa.ldd, "ll64 ", CONFIG_ARC_HAS_LL64), IS_AVAIL1(cpu->isa.unalign, "unalign (not used)")); @@ -253,7 +268,7 @@ static char *arc_cpu_mumbojumbo(int cpu_id, char *buf, int len) IS_AVAIL1(cpu->extn.swap, "swap "), IS_AVAIL1(cpu->extn.minmax, "minmax "), IS_AVAIL1(cpu->extn.crc, "crc "), - IS_AVAIL2(1, "swape", CONFIG_ARC_HAS_SWAPE)); + IS_AVAIL2(cpu->extn.swape, "swape", CONFIG_ARC_HAS_SWAPE)); if (cpu->bpu.ver) n += scnprintf(buf + n, len - n, @@ -272,9 +287,7 @@ static char *arc_extn_mumbojumbo(int cpu_id, char *buf, int len) FIX_PTR(cpu); - n += scnprintf(buf + n, len - n, - "Vector Table\t: %#x\nPeripherals\t: %#lx:%#lx\n", - cpu->vec_base, perip_base, perip_end); + n += scnprintf(buf + n, len - n, "Vector Table\t: %#x\n", cpu->vec_base); if (cpu->extn.fpu_sp || cpu->extn.fpu_dp) n += scnprintf(buf + n, len - n, "FPU\t\t: %s%s\n", @@ -507,7 +520,7 @@ static void *c_start(struct seq_file *m, loff_t *pos) * way to pass it w/o having to kmalloc/free a 2 byte string. * Encode cpu-id as 0xFFcccc, which is decoded by show routine. */ - return *pos < num_possible_cpus() ? cpu_to_ptr(*pos) : NULL; + return *pos < nr_cpu_ids ? cpu_to_ptr(*pos) : NULL; } static void *c_next(struct seq_file *m, void *v, loff_t *pos) diff --git a/arch/arc/kernel/troubleshoot.c b/arch/arc/kernel/troubleshoot.c index 934150e7ac48..82f9bc819f4a 100644 --- a/arch/arc/kernel/troubleshoot.c +++ b/arch/arc/kernel/troubleshoot.c @@ -237,113 +237,3 @@ void show_kernel_fault_diag(const char *str, struct pt_regs *regs, if (!user_mode(regs)) show_stacktrace(current, regs); } - -#ifdef CONFIG_DEBUG_FS - -#include <linux/module.h> -#include <linux/fs.h> -#include <linux/mount.h> -#include <linux/pagemap.h> -#include <linux/init.h> -#include <linux/namei.h> -#include <linux/debugfs.h> - -static struct dentry *test_dentry; -static struct dentry *test_dir; -static struct dentry *test_u32_dentry; - -static u32 clr_on_read = 1; - -#ifdef CONFIG_ARC_DBG_TLB_MISS_COUNT -u32 numitlb, numdtlb, num_pte_not_present; - -static int fill_display_data(char *kbuf) -{ - size_t num = 0; - num += sprintf(kbuf + num, "I-TLB Miss %x\n", numitlb); - num += sprintf(kbuf + num, "D-TLB Miss %x\n", numdtlb); - num += sprintf(kbuf + num, "PTE not present %x\n", num_pte_not_present); - - if (clr_on_read) - numitlb = numdtlb = num_pte_not_present = 0; - - return num; -} - -static int tlb_stats_open(struct inode *inode, struct file *file) -{ - file->private_data = (void *)__get_free_page(GFP_KERNEL); - return 0; -} - -/* called on user read(): display the counters */ -static ssize_t tlb_stats_output(struct file *file, /* file descriptor */ - char __user *user_buf, /* user buffer */ - size_t len, /* length of buffer */ - loff_t *offset) /* offset in the file */ -{ - size_t num; - char *kbuf = (char *)file->private_data; - - /* All of the data can he shoved in one iteration */ - if (*offset != 0) - return 0; - - num = fill_display_data(kbuf); - - /* simple_read_from_buffer() is helper for copy to user space - It copies up to @2 (num) bytes from kernel buffer @4 (kbuf) at offset - @3 (offset) into the user space address starting at @1 (user_buf). - @5 (len) is max size of user buffer - */ - return simple_read_from_buffer(user_buf, num, offset, kbuf, len); -} - -/* called on user write : clears the counters */ -static ssize_t tlb_stats_clear(struct file *file, const char __user *user_buf, - size_t length, loff_t *offset) -{ - numitlb = numdtlb = num_pte_not_present = 0; - return length; -} - -static int tlb_stats_close(struct inode *inode, struct file *file) -{ - free_page((unsigned long)(file->private_data)); - return 0; -} - -static const struct file_operations tlb_stats_file_ops = { - .read = tlb_stats_output, - .write = tlb_stats_clear, - .open = tlb_stats_open, - .release = tlb_stats_close -}; -#endif - -static int __init arc_debugfs_init(void) -{ - test_dir = debugfs_create_dir("arc", NULL); - -#ifdef CONFIG_ARC_DBG_TLB_MISS_COUNT - test_dentry = debugfs_create_file("tlb_stats", 0444, test_dir, NULL, - &tlb_stats_file_ops); -#endif - - test_u32_dentry = - debugfs_create_u32("clr_on_read", 0444, test_dir, &clr_on_read); - - return 0; -} - -module_init(arc_debugfs_init); - -static void __exit arc_debugfs_exit(void) -{ - debugfs_remove(test_u32_dentry); - debugfs_remove(test_dentry); - debugfs_remove(test_dir); -} -module_exit(arc_debugfs_exit); - -#endif diff --git a/arch/arc/mm/cache.c b/arch/arc/mm/cache.c index 97dddbefb86a..2b96cfc3be75 100644 --- a/arch/arc/mm/cache.c +++ b/arch/arc/mm/cache.c @@ -22,8 +22,8 @@ #include <asm/setup.h> static int l2_line_sz; -int ioc_exists; -volatile int slc_enable = 1, ioc_enable = 1; +static int ioc_exists; +int slc_enable = 1, ioc_enable = 1; unsigned long perip_base = ARC_UNCACHED_ADDR_SPACE; /* legacy value for boot */ unsigned long perip_end = 0xFFFFFFFF; /* legacy value */ @@ -53,18 +53,15 @@ char *arc_cache_mumbojumbo(int c, char *buf, int len) PR_CACHE(&cpuinfo_arc700[c].icache, CONFIG_ARC_HAS_ICACHE, "I-Cache"); PR_CACHE(&cpuinfo_arc700[c].dcache, CONFIG_ARC_HAS_DCACHE, "D-Cache"); - if (!is_isa_arcv2()) - return buf; - p = &cpuinfo_arc700[c].slc; if (p->ver) n += scnprintf(buf + n, len - n, "SLC\t\t: %uK, %uB Line%s\n", p->sz_k, p->line_len, IS_USED_RUN(slc_enable)); - if (ioc_exists) - n += scnprintf(buf + n, len - n, "IOC\t\t:%s\n", - IS_DISABLED_RUN(ioc_enable)); + n += scnprintf(buf + n, len - n, "Peripherals\t: %#lx%s%s\n", + perip_base, + IS_AVAIL3(ioc_exists, ioc_enable, ", IO-Coherency ")); return buf; } @@ -113,8 +110,10 @@ static void read_decode_cache_bcr_arcv2(int cpu) } READ_BCR(ARC_REG_CLUSTER_BCR, cbcr); - if (cbcr.c && ioc_enable) + if (cbcr.c) ioc_exists = 1; + else + ioc_enable = 0; /* HS 2.0 didn't have AUX_VOL */ if (cpuinfo_arc700[cpu].core.family > 0x51) { @@ -1002,7 +1001,7 @@ void arc_cache_init(void) read_aux_reg(ARC_REG_SLC_CTRL) | SLC_CTRL_DISABLE); } - if (is_isa_arcv2() && ioc_exists) { + if (is_isa_arcv2() && ioc_enable) { /* IO coherency base - 0x8z */ write_aux_reg(ARC_REG_IO_COH_AP0_BASE, 0x80000); /* IO coherency aperture size - 512Mb: 0x8z-0xAz */ diff --git a/arch/arc/mm/dma.c b/arch/arc/mm/dma.c index 20afc65e22dc..60aab5a7522b 100644 --- a/arch/arc/mm/dma.c +++ b/arch/arc/mm/dma.c @@ -45,7 +45,7 @@ static void *arc_dma_alloc(struct device *dev, size_t size, * -For coherent data, Read/Write to buffers terminate early in cache * (vs. always going to memory - thus are faster) */ - if ((is_isa_arcv2() && ioc_exists) || + if ((is_isa_arcv2() && ioc_enable) || (attrs & DMA_ATTR_NON_CONSISTENT)) need_coh = 0; @@ -97,7 +97,7 @@ static void arc_dma_free(struct device *dev, size_t size, void *vaddr, int is_non_coh = 1; is_non_coh = (attrs & DMA_ATTR_NON_CONSISTENT) || - (is_isa_arcv2() && ioc_exists); + (is_isa_arcv2() && ioc_enable); if (PageHighMem(page) || !is_non_coh) iounmap((void __force __iomem *)vaddr); diff --git a/arch/arc/mm/tlb.c b/arch/arc/mm/tlb.c index ec868a9081a1..bdb295e09160 100644 --- a/arch/arc/mm/tlb.c +++ b/arch/arc/mm/tlb.c @@ -793,16 +793,16 @@ char *arc_mmu_mumbojumbo(int cpu_id, char *buf, int len) char super_pg[64] = ""; if (p_mmu->s_pg_sz_m) - scnprintf(super_pg, 64, "%dM Super Page%s, ", + scnprintf(super_pg, 64, "%dM Super Page %s", p_mmu->s_pg_sz_m, IS_USED_CFG(CONFIG_TRANSPARENT_HUGEPAGE)); n += scnprintf(buf + n, len - n, - "MMU [v%x]\t: %dk PAGE, %sJTLB %d (%dx%d), uDTLB %d, uITLB %d %s%s\n", + "MMU [v%x]\t: %dk PAGE, %sJTLB %d (%dx%d), uDTLB %d, uITLB %d%s%s\n", p_mmu->ver, p_mmu->pg_sz_k, super_pg, p_mmu->sets * p_mmu->ways, p_mmu->sets, p_mmu->ways, p_mmu->u_dtlb, p_mmu->u_itlb, - IS_AVAIL2(p_mmu->pae, "PAE40 ", CONFIG_ARC_HAS_PAE40)); + IS_AVAIL2(p_mmu->pae, ", PAE40 ", CONFIG_ARC_HAS_PAE40)); return buf; } diff --git a/arch/arc/mm/tlbex.S b/arch/arc/mm/tlbex.S index f1967eeb32e7..b30e4e36bb00 100644 --- a/arch/arc/mm/tlbex.S +++ b/arch/arc/mm/tlbex.S @@ -237,15 +237,6 @@ ex_saved_reg1: 2: -#ifdef CONFIG_ARC_DBG_TLB_MISS_COUNT - and.f 0, r0, _PAGE_PRESENT - bz 1f - ld r3, [num_pte_not_present] - add r3, r3, 1 - st r3, [num_pte_not_present] -1: -#endif - .endm ;----------------------------------------------------------------- @@ -309,12 +300,6 @@ ENTRY(EV_TLBMissI) TLBMISS_FREEUP_REGS -#ifdef CONFIG_ARC_DBG_TLB_MISS_COUNT - ld r0, [@numitlb] - add r0, r0, 1 - st r0, [@numitlb] -#endif - ;---------------------------------------------------------------- ; Get the PTE corresponding to V-addr accessed, r2 is setup with EFA LOAD_FAULT_PTE @@ -349,12 +334,6 @@ ENTRY(EV_TLBMissD) TLBMISS_FREEUP_REGS -#ifdef CONFIG_ARC_DBG_TLB_MISS_COUNT - ld r0, [@numdtlb] - add r0, r0, 1 - st r0, [@numdtlb] -#endif - ;---------------------------------------------------------------- ; Get the PTE corresponding to V-addr accessed ; If PTE exists, it will setup, r0 = PTE, r1 = Ptr to PTE, r2 = EFA diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile index befcd2619902..3ba77c4f2943 100644 --- a/arch/arm/boot/dts/Makefile +++ b/arch/arm/boot/dts/Makefile @@ -136,6 +136,7 @@ dtb-$(CONFIG_ARCH_EXYNOS4) += \ exynos4210-smdkv310.dtb \ exynos4210-trats.dtb \ exynos4210-universal_c210.dtb \ + exynos4412-itop-elite.dtb \ exynos4412-odroidu3.dtb \ exynos4412-odroidx.dtb \ exynos4412-odroidx2.dtb \ @@ -330,6 +331,7 @@ dtb-$(CONFIG_SOC_IMX6Q) += \ imx6dl-aristainetos_7.dtb \ imx6dl-aristainetos2_4.dtb \ imx6dl-aristainetos2_7.dtb \ + imx6dl-colibri-eval-v3.dtb \ imx6dl-cubox-i.dtb \ imx6dl-dfi-fs700-m60.dtb \ imx6dl-gw51xx.dtb \ @@ -340,6 +342,7 @@ dtb-$(CONFIG_SOC_IMX6Q) += \ imx6dl-gw552x.dtb \ imx6dl-gw553x.dtb \ imx6dl-hummingboard.dtb \ + imx6dl-icore.dtb \ imx6dl-nit6xlite.dtb \ imx6dl-nitrogen6x.dtb \ imx6dl-phytec-pbab01.dtb \ @@ -381,10 +384,12 @@ dtb-$(CONFIG_SOC_IMX6Q) += \ imx6q-gw553x.dtb \ imx6q-h100.dtb \ imx6q-hummingboard.dtb \ + imx6q-icore.dtb \ imx6q-icore-rqs.dtb \ imx6q-marsboard.dtb \ imx6q-nitrogen6x.dtb \ imx6q-nitrogen6_max.dtb \ + imx6q-nitrogen6_som2.dtb \ imx6q-novena.dtb \ imx6q-phytec-pbab01.dtb \ imx6q-rex-pro.dtb \ @@ -416,14 +421,19 @@ dtb-$(CONFIG_SOC_IMX6SX) += \ imx6sx-sabreauto.dtb \ imx6sx-sdb-reva.dtb \ imx6sx-sdb-sai.dtb \ - imx6sx-sdb.dtb + imx6sx-sdb.dtb \ + imx6sx-udoo-neo-basic.dtb \ + imx6sx-udoo-neo-extended.dtb \ + imx6sx-udoo-neo-full.dtb dtb-$(CONFIG_SOC_IMX6UL) += \ imx6ul-14x14-evk.dtb \ imx6ul-geam-kit.dtb \ + imx6ul-liteboard.dtb \ imx6ul-pico-hobbit.dtb \ imx6ul-tx6ul-0010.dtb \ imx6ul-tx6ul-0011.dtb \ - imx6ul-tx6ul-mainboard.dtb + imx6ul-tx6ul-mainboard.dtb \ + imx6ull-14x14-evk.dtb dtb-$(CONFIG_SOC_IMX7D) += \ imx7d-cl-som-imx7.dtb \ imx7d-colibri-eval-v3.dtb \ @@ -561,6 +571,7 @@ dtb-$(CONFIG_SOC_AM33XX) += \ am335x-sl50.dtb \ am335x-wega-rdk.dtb dtb-$(CONFIG_ARCH_OMAP4) += \ + omap4-droid4-xt894.dtb \ omap4-duovero-parlor.dtb \ omap4-kc1.dtb \ omap4-panda.dtb \ @@ -590,13 +601,15 @@ dtb-$(CONFIG_SOC_DRA7XX) += \ am572x-idk.dtb \ dra7-evm.dtb \ dra72-evm.dtb \ - dra72-evm-revc.dtb + dra72-evm-revc.dtb \ + dra71-evm.dtb dtb-$(CONFIG_ARCH_ORION5X) += \ orion5x-kuroboxpro.dtb \ orion5x-lacie-d2-network.dtb \ orion5x-lacie-ethernet-disk-mini-v2.dtb \ orion5x-linkstation-lsgl.dtb \ orion5x-linkstation-lswtgl.dtb \ + orion5x-lschl.dtb \ orion5x-lswsgl.dtb \ orion5x-maxtor-shared-storage-2.dtb \ orion5x-netgear-wnr854t.dtb \ @@ -604,7 +617,8 @@ dtb-$(CONFIG_ARCH_ORION5X) += \ dtb-$(CONFIG_ARCH_PRIMA2) += \ prima2-evb.dtb dtb-$(CONFIG_ARCH_OXNAS) += \ - wd-mbwe.dtb + wd-mbwe.dtb \ + cloudengines-pogoplug-series-3.dtb dtb-$(CONFIG_ARCH_QCOM) += \ qcom-apq8060-dragonboard.dtb \ qcom-apq8064-arrow-sd-600eval.dtb \ @@ -620,7 +634,8 @@ dtb-$(CONFIG_ARCH_QCOM) += \ qcom-msm8660-surf.dtb \ qcom-msm8960-cdp.dtb \ qcom-msm8974-lge-nexus5-hammerhead.dtb \ - qcom-msm8974-sony-xperia-honami.dtb + qcom-msm8974-sony-xperia-honami.dtb \ + qcom-mdm9615-wp8548-mangoh-green.dtb dtb-$(CONFIG_ARCH_REALVIEW) += \ arm-realview-pb1176.dtb \ arm-realview-pb11mp.dtb \ @@ -639,7 +654,9 @@ dtb-$(CONFIG_ARCH_ROCKCHIP) += \ rk3036-kylin.dtb \ rk3066a-bqcurie2.dtb \ rk3066a-marsboard.dtb \ + rk3066a-mk808.dtb \ rk3066a-rayeager.dtb \ + rk3188-px3-evb.dtb \ rk3188-radxarock.dtb \ rk3228-evb.dtb \ rk3229-evb.dtb \ @@ -690,12 +707,14 @@ dtb-$(CONFIG_ARCH_SHMOBILE_MULTI) += \ sh73a0-kzm9g.dtb dtb-$(CONFIG_ARCH_SOCFPGA) += \ socfpga_arria5_socdk.dtb \ + socfpga_arria10_socdk_qspi.dtb \ socfpga_arria10_socdk_sdmmc.dtb \ socfpga_cyclone5_mcvevk.dtb \ socfpga_cyclone5_socdk.dtb \ socfpga_cyclone5_de0_sockit.dtb \ socfpga_cyclone5_sockit.dtb \ socfpga_cyclone5_socrates.dtb \ + socfpga_cyclone5_sodia.dtb \ socfpga_cyclone5_vining_fpga.dtb \ socfpga_vt.dtb dtb-$(CONFIG_ARCH_SPEAR13XX) += \ @@ -712,16 +731,12 @@ dtb-$(CONFIG_ARCH_STI) += \ stih407-b2120.dtb \ stih410-b2120.dtb \ stih410-b2260.dtb \ - stih415-b2000.dtb \ - stih415-b2020.dtb \ - stih416-b2000.dtb \ - stih416-b2020.dtb \ - stih416-b2020e.dtb \ stih418-b2199.dtb dtb-$(CONFIG_ARCH_STM32)+= \ stm32f429-disco.dtb \ stm32f469-disco.dtb \ - stm32429i-eval.dtb + stm32429i-eval.dtb \ + stm32746g-eval.dtb dtb-$(CONFIG_MACH_SUN4I) += \ sun4i-a10-a1000.dtb \ sun4i-a10-ba10-tvbox.dtb \ @@ -745,7 +760,6 @@ dtb-$(CONFIG_MACH_SUN4I) += \ sun4i-a10-pcduino2.dtb \ sun4i-a10-pov-protab2-ips9.dtb dtb-$(CONFIG_MACH_SUN5I) += \ - ntc-gr8-evb.dtb \ sun5i-a10s-auxtek-t003.dtb \ sun5i-a10s-auxtek-t004.dtb \ sun5i-a10s-mk802.dtb \ @@ -761,6 +775,8 @@ dtb-$(CONFIG_MACH_SUN5I) += \ sun5i-a13-olinuxino-micro.dtb \ sun5i-a13-q8-tablet.dtb \ sun5i-a13-utoo-p66.dtb \ + sun5i-gr8-chip-pro.dtb \ + sun5i-gr8-evb.dtb \ sun5i-r8-chip.dtb dtb-$(CONFIG_MACH_SUN6I) += \ sun6i-a31-app4-evb1.dtb \ diff --git a/arch/arm/boot/dts/am335x-baltos-ir5221.dts b/arch/arm/boot/dts/am335x-baltos-ir5221.dts index d0faa7b8c5da..f599350dd305 100644 --- a/arch/arm/boot/dts/am335x-baltos-ir5221.dts +++ b/arch/arm/boot/dts/am335x-baltos-ir5221.dts @@ -114,7 +114,7 @@ &usb1 { status = "okay"; - dr_mode = "otg"; + dr_mode = "host"; }; &cpsw_emac0 { diff --git a/arch/arm/boot/dts/am335x-baltos.dtsi b/arch/arm/boot/dts/am335x-baltos.dtsi index dd45d172a892..09b954154e6b 100644 --- a/arch/arm/boot/dts/am335x-baltos.dtsi +++ b/arch/arm/boot/dts/am335x-baltos.dtsi @@ -406,3 +406,7 @@ &gpio0 { ti,no-reset-on-init; }; + +&gpio3 { + ti,no-reset-on-init; +}; diff --git a/arch/arm/boot/dts/am335x-bone-common.dtsi b/arch/arm/boot/dts/am335x-bone-common.dtsi index 007b5e5a51a9..dc561d505bbe 100644 --- a/arch/arm/boot/dts/am335x-bone-common.dtsi +++ b/arch/arm/boot/dts/am335x-bone-common.dtsi @@ -6,6 +6,8 @@ * published by the Free Software Foundation. */ +#include <dt-bindings/mfd/tps65217.h> + / { cpus { cpu@0 { @@ -310,8 +312,23 @@ * by the hardware problems. (Tip: double-check by performing a current * measurement after shutdown: it should be less than 1 mA.) */ + + interrupts = <7>; /* NMI */ + interrupt-parent = <&intc>; + ti,pmic-shutdown-controller; + charger { + interrupts = <TPS65217_IRQ_AC>, <TPS65217_IRQ_USB>; + interrupts-names = "AC", "USB"; + status = "okay"; + }; + + pwrbutton { + interrupts = <TPS65217_IRQ_PB>; + status = "okay"; + }; + regulators { dcdc1_reg: regulator@0 { regulator-name = "vdds_dpr"; @@ -393,3 +410,8 @@ &sham { status = "okay"; }; + +&rtc { + clocks = <&clk_32768_ck>, <&clkdiv32k_ick>; + clock-names = "ext-clk", "int-clk"; +}; diff --git a/arch/arm/boot/dts/am335x-evm.dts b/arch/arm/boot/dts/am335x-evm.dts index e82432c79f85..c2186ec2834b 100644 --- a/arch/arm/boot/dts/am335x-evm.dts +++ b/arch/arm/boot/dts/am335x-evm.dts @@ -783,3 +783,8 @@ pinctrl-names = "default"; pinctrl-0 = <&dcan1_pins_default>; }; + +&rtc { + clocks = <&clk_32768_ck>, <&clkdiv32k_ick>; + clock-names = "ext-clk", "int-clk"; +}; diff --git a/arch/arm/boot/dts/am335x-evmsk.dts b/arch/arm/boot/dts/am335x-evmsk.dts index 975c36e332a2..e2548d1ce753 100644 --- a/arch/arm/boot/dts/am335x-evmsk.dts +++ b/arch/arm/boot/dts/am335x-evmsk.dts @@ -715,3 +715,8 @@ blue-and-red-wiring = "crossed"; }; + +&rtc { + clocks = <&clk_32768_ck>, <&clkdiv32k_ick>; + clock-names = "ext-clk", "int-clk"; +}; diff --git a/arch/arm/boot/dts/am33xx.dtsi b/arch/arm/boot/dts/am33xx.dtsi index 194d884c9de1..64c8aa9057a3 100644 --- a/arch/arm/boot/dts/am33xx.dtsi +++ b/arch/arm/boot/dts/am33xx.dtsi @@ -130,6 +130,7 @@ reg = <0x210000 0x2000>; #address-cells = <1>; #size-cells = <1>; + #pinctrl-cells = <1>; ranges = <0 0x210000 0x2000>; am33xx_pinmux: pinmux@800 { @@ -137,6 +138,7 @@ reg = <0x800 0x238>; #address-cells = <1>; #size-cells = <0>; + #pinctrl-cells = <1>; pinctrl-single,register-width = <32>; pinctrl-single,function-mask = <0x7f>; }; @@ -505,6 +507,8 @@ interrupts = <75 76>; ti,hwmods = "rtc"; + clocks = <&clkdiv32k_ick>; + clock-names = "int-clk"; }; spi0: spi@48030000 { @@ -855,6 +859,8 @@ interrupts = <16>; ti,hwmods = "adc_tsc"; status = "disabled"; + dmas = <&edma 53 0>, <&edma 57 0>; + dma-names = "fifo0", "fifo1"; tsc { compatible = "ti,am3359-tsc"; diff --git a/arch/arm/boot/dts/am3517.dtsi b/arch/arm/boot/dts/am3517.dtsi index 0db19d39d24c..9fe545dbfa89 100644 --- a/arch/arm/boot/dts/am3517.dtsi +++ b/arch/arm/boot/dts/am3517.dtsi @@ -66,6 +66,7 @@ reg = <0x480025d8 0x24>; #address-cells = <1>; #size-cells = <0>; + #pinctrl-cells = <1>; #interrupt-cells = <1>; interrupt-controller; pinctrl-single,register-width = <16>; diff --git a/arch/arm/boot/dts/am4372.dtsi b/arch/arm/boot/dts/am4372.dtsi index a275fa956813..ac55f93fc91e 100644 --- a/arch/arm/boot/dts/am4372.dtsi +++ b/arch/arm/boot/dts/am4372.dtsi @@ -189,6 +189,7 @@ reg = <0x800 0x31c>; #address-cells = <1>; #size-cells = <0>; + #pinctrl-cells = <1>; #interrupt-cells = <1>; interrupt-controller; pinctrl-single,register-width = <32>; @@ -871,6 +872,8 @@ clocks = <&adc_tsc_fck>; clock-names = "fck"; status = "disabled"; + dmas = <&edma 53 0>, <&edma 57 0>; + dma-names = "fifo0", "fifo1"; tsc { compatible = "ti,am3359-tsc"; diff --git a/arch/arm/boot/dts/armada-370-db.dts b/arch/arm/boot/dts/armada-370-db.dts index 033fa63544f7..a9419f8e17e8 100644 --- a/arch/arm/boot/dts/armada-370-db.dts +++ b/arch/arm/boot/dts/armada-370-db.dts @@ -67,7 +67,7 @@ stdout-path = "serial0:115200n8"; }; - memory { + memory@0 { device_type = "memory"; reg = <0x00000000 0x40000000>; /* 1 GB */ }; @@ -86,18 +86,6 @@ status = "okay"; }; - mdio { - pinctrl-0 = <&mdio_pins>; - pinctrl-names = "default"; - phy0: ethernet-phy@0 { - reg = <0>; - }; - - phy1: ethernet-phy@1 { - reg = <1>; - }; - }; - ethernet@70000 { pinctrl-0 = <&ge0_rgmii_pins>; pinctrl-names = "default"; @@ -182,24 +170,6 @@ }; }; }; - - pcie-controller { - status = "okay"; - /* - * The two PCIe units are accessible through - * both standard PCIe slots and mini-PCIe - * slots on the board. - */ - pcie@1,0 { - /* Port 0, Lane 0 */ - status = "okay"; - }; - - pcie@2,0 { - /* Port 1, Lane 0 */ - status = "okay"; - }; - }; }; sound { @@ -261,6 +231,37 @@ }; }; +&pciec { + status = "okay"; + /* + * The two PCIe units are accessible through + * both standard PCIe slots and mini-PCIe + * slots on the board. + */ + pcie@1,0 { + /* Port 0, Lane 0 */ + status = "okay"; + }; + + pcie@2,0 { + /* Port 1, Lane 0 */ + status = "okay"; + }; +}; + +&mdio { + pinctrl-0 = <&mdio_pins>; + pinctrl-names = "default"; + phy0: ethernet-phy@0 { + reg = <0>; + }; + + phy1: ethernet-phy@1 { + reg = <1>; + }; +}; + + &spi0 { pinctrl-0 = <&spi0_pins2>; pinctrl-names = "default"; diff --git a/arch/arm/boot/dts/armada-370-dlink-dns327l.dts b/arch/arm/boot/dts/armada-370-dlink-dns327l.dts index e2a363b1dd8a..aeedc463daa6 100644 --- a/arch/arm/boot/dts/armada-370-dlink-dns327l.dts +++ b/arch/arm/boot/dts/armada-370-dlink-dns327l.dts @@ -62,7 +62,7 @@ stdout-path = &uart0; }; - memory { + memory@0 { device_type = "memory"; reg = <0x00000000 0x20000000>; /* 512 MiB */ }; @@ -72,20 +72,6 @@ MBUS_ID(0x01, 0xe0) 0 0xfff00000 0x100000 MBUS_ID(0x09, 0x01) 0 0xf1100000 0x10000>; - pcie-controller { - status = "okay"; - - pcie@1,0 { - /* Port 0, Lane 0 */ - status = "okay"; - }; - - pcie@2,0 { - /* Port 1, Lane 0 */ - status = "okay"; - }; - }; - internal-regs { sata@a0000 { nr-ports = <2>; @@ -262,6 +248,20 @@ }; }; +&pciec { + status = "okay"; + + pcie@1,0 { + /* Port 0, Lane 0 */ + status = "okay"; + }; + + pcie@2,0 { + /* Port 1, Lane 0 */ + status = "okay"; + }; +}; + &pinctrl { sata_l_white_pin: sata-l-white-pin { marvell,pins = "mpp57"; diff --git a/arch/arm/boot/dts/armada-370-mirabox.dts b/arch/arm/boot/dts/armada-370-mirabox.dts index d5e19cd4d256..a1425409e570 100644 --- a/arch/arm/boot/dts/armada-370-mirabox.dts +++ b/arch/arm/boot/dts/armada-370-mirabox.dts @@ -54,7 +54,7 @@ stdout-path = "serial0:115200n8"; }; - memory { + memory@0 { device_type = "memory"; reg = <0x00000000 0x20000000>; /* 512 MB */ }; @@ -64,22 +64,6 @@ MBUS_ID(0x01, 0xe0) 0 0xfff00000 0x100000 MBUS_ID(0x09, 0x01) 0 0xf1100000 0x10000>; - pcie-controller { - status = "okay"; - - /* Internal mini-PCIe connector */ - pcie@1,0 { - /* Port 0, Lane 0 */ - status = "okay"; - }; - - /* Connected on the PCB to a USB 3.0 XHCI controller */ - pcie@2,0 { - /* Port 1, Lane 0 */ - status = "okay"; - }; - }; - internal-regs { serial@12000 { status = "okay"; @@ -113,17 +97,6 @@ }; }; - mdio { - pinctrl-0 = <&mdio_pins>; - pinctrl-names = "default"; - phy0: ethernet-phy@0 { - reg = <0>; - }; - - phy1: ethernet-phy@1 { - reg = <1>; - }; - }; ethernet@70000 { pinctrl-0 = <&ge0_rgmii_pins>; pinctrl-names = "default"; @@ -197,6 +170,34 @@ }; }; +&pciec { + status = "okay"; + + /* Internal mini-PCIe connector */ + pcie@1,0 { + /* Port 0, Lane 0 */ + status = "okay"; + }; + + /* Connected on the PCB to a USB 3.0 XHCI controller */ + pcie@2,0 { + /* Port 1, Lane 0 */ + status = "okay"; + }; +}; + +&mdio { + pinctrl-0 = <&mdio_pins>; + pinctrl-names = "default"; + phy0: ethernet-phy@0 { + reg = <0>; + }; + + phy1: ethernet-phy@1 { + reg = <1>; + }; +}; + &pinctrl { pwr_led_pin: pwr-led-pin { marvell,pins = "mpp63"; diff --git a/arch/arm/boot/dts/armada-370-netgear-rn102.dts b/arch/arm/boot/dts/armada-370-netgear-rn102.dts index 39181b3fa90d..6bd9265f1062 100644 --- a/arch/arm/boot/dts/armada-370-netgear-rn102.dts +++ b/arch/arm/boot/dts/armada-370-netgear-rn102.dts @@ -56,7 +56,7 @@ stdout-path = "serial0:115200n8"; }; - memory { + memory@0 { device_type = "memory"; reg = <0x00000000 0x20000000>; /* 512 MB */ }; @@ -66,22 +66,6 @@ MBUS_ID(0x01, 0xe0) 0 0xfff00000 0x100000 MBUS_ID(0x09, 0x01) 0 0xf1100000 0x10000>; - pcie-controller { - status = "okay"; - - /* Connected to Marvell 88SE9170 SATA controller */ - pcie@1,0 { - /* Port 0, Lane 0 */ - status = "okay"; - }; - - /* Connected to FL1009 USB 3.0 controller */ - pcie@2,0 { - /* Port 1, Lane 0 */ - status = "okay"; - }; - }; - internal-regs { /* RTC is provided by Intersil ISL12057 I2C RTC chip */ @@ -99,14 +83,6 @@ status = "okay"; }; - mdio { - pinctrl-0 = <&mdio_pins>; - pinctrl-names = "default"; - phy0: ethernet-phy@0 { /* Marvell 88E1318 */ - reg = <0>; - }; - }; - ethernet@74000 { pinctrl-0 = <&ge1_rgmii_pins>; pinctrl-names = "default"; @@ -120,8 +96,11 @@ }; i2c@11000 { - compatible = "marvell,mv64xxx-i2c"; clock-frequency = <100000>; + + pinctrl-0 = <&i2c0_pins>; + pinctrl-names = "default"; + status = "okay"; isl12057: isl12057@68 { @@ -257,6 +236,30 @@ }; }; +&pciec { + status = "okay"; + + /* Connected to Marvell 88SE9170 SATA controller */ + pcie@1,0 { + /* Port 0, Lane 0 */ + status = "okay"; + }; + + /* Connected to FL1009 USB 3.0 controller */ + pcie@2,0 { + /* Port 1, Lane 0 */ + status = "okay"; + }; +}; + +&mdio { + pinctrl-0 = <&mdio_pins>; + pinctrl-names = "default"; + phy0: ethernet-phy@0 { /* Marvell 88E1318 */ + reg = <0>; + }; +}; + &pinctrl { power_led_pin: power-led-pin { marvell,pins = "mpp57"; diff --git a/arch/arm/boot/dts/armada-370-netgear-rn104.dts b/arch/arm/boot/dts/armada-370-netgear-rn104.dts index 11565752b9f6..c84ab5bf1e18 100644 --- a/arch/arm/boot/dts/armada-370-netgear-rn104.dts +++ b/arch/arm/boot/dts/armada-370-netgear-rn104.dts @@ -56,7 +56,7 @@ stdout-path = "serial0:115200n8"; }; - memory { + memory@0 { device_type = "memory"; reg = <0x00000000 0x20000000>; /* 512 MB */ }; @@ -66,22 +66,6 @@ MBUS_ID(0x01, 0xe0) 0 0xfff00000 0x100000 MBUS_ID(0x09, 0x01) 0 0xf1100000 0x10000>; - pcie-controller { - status = "okay"; - - /* Connected to FL1009 USB 3.0 controller */ - pcie@1,0 { - /* Port 0, Lane 0 */ - status = "okay"; - }; - - /* Connected to Marvell 88SE9215 SATA controller */ - pcie@2,0 { - /* Port 1, Lane 0 */ - status = "okay"; - }; - }; - internal-regs { /* RTC is provided by Intersil ISL12057 I2C RTC chip */ @@ -93,18 +77,6 @@ status = "okay"; }; - mdio { - pinctrl-0 = <&mdio_pins>; - pinctrl-names = "default"; - phy0: ethernet-phy@0 { /* Marvell 88E1318 */ - reg = <0>; - }; - - phy1: ethernet-phy@1 { /* Marvell 88E1318 */ - reg = <1>; - }; - }; - ethernet@70000 { pinctrl-0 = <&ge0_rgmii_pins>; pinctrl-names = "default"; @@ -126,8 +98,11 @@ }; i2c@11000 { - compatible = "marvell,mv64xxx-i2c"; clock-frequency = <100000>; + + pinctrl-0 = <&i2c0_pins>; + pinctrl-names = "default"; + status = "okay"; isl12057: isl12057@68 { @@ -279,6 +254,34 @@ }; }; +&pciec { + status = "okay"; + + /* Connected to FL1009 USB 3.0 controller */ + pcie@1,0 { + /* Port 0, Lane 0 */ + status = "okay"; + }; + + /* Connected to Marvell 88SE9215 SATA controller */ + pcie@2,0 { + /* Port 1, Lane 0 */ + status = "okay"; + }; +}; + +&mdio { + pinctrl-0 = <&mdio_pins>; + pinctrl-names = "default"; + phy0: ethernet-phy@0 { /* Marvell 88E1318 */ + reg = <0>; + }; + + phy1: ethernet-phy@1 { /* Marvell 88E1318 */ + reg = <1>; + }; +}; + &pinctrl { poweroff: poweroff { marvell,pins = "mpp60"; diff --git a/arch/arm/boot/dts/armada-370-rd.dts b/arch/arm/boot/dts/armada-370-rd.dts index fbef730e8d37..c3fd6e49212f 100644 --- a/arch/arm/boot/dts/armada-370-rd.dts +++ b/arch/arm/boot/dts/armada-370-rd.dts @@ -67,7 +67,7 @@ stdout-path = "serial0:115200n8"; }; - memory { + memory@0 { device_type = "memory"; reg = <0x00000000 0x20000000>; /* 512 MB */ }; @@ -77,22 +77,6 @@ MBUS_ID(0x01, 0xe0) 0 0xfff00000 0x100000 MBUS_ID(0x09, 0x01) 0 0xf1100000 0x10000>; - pcie-controller { - status = "okay"; - - /* Internal mini-PCIe connector */ - pcie@1,0 { - /* Port 0, Lane 0 */ - status = "okay"; - }; - - /* Internal mini-PCIe connector */ - pcie@2,0 { - /* Port 1, Lane 0 */ - status = "okay"; - }; - }; - internal-regs { serial@12000 { status = "okay"; @@ -102,14 +86,6 @@ status = "okay"; }; - mdio { - pinctrl-0 = <&mdio_pins>; - pinctrl-names = "default"; - phy0: ethernet-phy@0 { - reg = <0>; - }; - }; - ethernet@70000 { status = "okay"; phy = <&phy0>; @@ -146,7 +122,7 @@ compatible = "gpio-keys"; #address-cells = <1>; #size-cells = <0>; - button@1 { + button { label = "Software Button"; linux,code = <KEY_POWER>; gpios = <&gpio0 6 GPIO_ACTIVE_LOW>; @@ -196,7 +172,7 @@ }; }; - dsa@0 { + dsa { compatible = "marvell,dsa"; #address-cells = <2>; #size-cells = <0>; @@ -235,7 +211,32 @@ }; }; }; - }; +}; + +&pciec { + status = "okay"; + + /* Internal mini-PCIe connector */ + pcie@1,0 { + /* Port 0, Lane 0 */ + status = "okay"; + }; + + /* Internal mini-PCIe connector */ + pcie@2,0 { + /* Port 1, Lane 0 */ + status = "okay"; + }; +}; + +&mdio { + pinctrl-0 = <&mdio_pins>; + pinctrl-names = "default"; + phy0: ethernet-phy@0 { + reg = <0>; + }; +}; + &pinctrl { fan_pins: fan-pins { diff --git a/arch/arm/boot/dts/armada-370-seagate-nas-4bay.dts b/arch/arm/boot/dts/armada-370-seagate-nas-4bay.dts index ae2e1fe50ef6..eb6af53b4954 100644 --- a/arch/arm/boot/dts/armada-370-seagate-nas-4bay.dts +++ b/arch/arm/boot/dts/armada-370-seagate-nas-4bay.dts @@ -28,20 +28,7 @@ compatible = "seagate,dart-4", "marvell,armada370", "marvell,armada-370-xp"; soc { - pcie-controller { - /* SATA AHCI controller 88SE9170 */ - pcie@1,0 { - status = "okay"; - }; - }; - internal-regs { - mdio { - phy1: ethernet-phy@1 { - reg = <1>; - }; - }; - ethernet@74000 { status = "okay"; pinctrl-0 = <&ge1_rgmii_pins>; @@ -131,3 +118,17 @@ 1300 0>; }; }; + +&pciec { + /* SATA AHCI controller 88SE9170 */ + pcie@1,0 { + status = "okay"; + }; +}; + +&mdio { + phy1: ethernet-phy@1 { + reg = <1>; + }; +}; + diff --git a/arch/arm/boot/dts/armada-370-seagate-nas-xbay.dtsi b/arch/arm/boot/dts/armada-370-seagate-nas-xbay.dtsi index 3036e25c5992..e9a5b952afc0 100644 --- a/arch/arm/boot/dts/armada-370-seagate-nas-xbay.dtsi +++ b/arch/arm/boot/dts/armada-370-seagate-nas-xbay.dtsi @@ -23,7 +23,7 @@ stdout-path = "serial0:115200n8"; }; - memory { + memory@0 { device_type = "memory"; reg = <0x00000000 0x20000000>; /* 512 MB */ }; @@ -32,15 +32,6 @@ ranges = <MBUS_ID(0xf0, 0x01) 0 0xf1000000 0x100000 MBUS_ID(0x01, 0xe0) 0 0xfff00000 0x100000>; - pcie-controller { - status = "okay"; - - /* USB 3.0 bridge ASM1042A */ - pcie@2,0 { - status = "okay"; - }; - }; - internal-regs { serial@12000 { status = "okay"; @@ -51,15 +42,6 @@ status = "okay"; }; - mdio { - pinctrl-0 = <&mdio_pins>; - pinctrl-names = "default"; - - phy0: ethernet-phy@0 { - reg = <0>; - }; - }; - ethernet@70000 { status = "okay"; pinctrl-0 = <&ge0_rgmii_pins>; @@ -159,19 +141,19 @@ #address-cells = <1>; #size-cells = <0>; - button@1 { + power { label = "Power button"; linux,code = <KEY_POWER>; gpios = <&gpio1 19 GPIO_ACTIVE_LOW>; debounce-interval = <100>; }; - button@2 { + backup { label = "Backup button"; linux,code = <KEY_OPTION>; gpios = <&gpio0 31 GPIO_ACTIVE_LOW>; debounce-interval = <100>; }; - button@3 { + reset { label = "Reset Button"; linux,code = <KEY_RESTART>; gpios = <&gpio1 23 GPIO_ACTIVE_LOW>; @@ -208,6 +190,25 @@ }; }; +&pciec { + status = "okay"; + + /* USB 3.0 bridge ASM1042A */ + pcie@2,0 { + status = "okay"; + }; +}; + + +&mdio { + pinctrl-0 = <&mdio_pins>; + pinctrl-names = "default"; + + phy0: ethernet-phy@0 { + reg = <0>; + }; +}; + &pinctrl { pinctrl-0 = <&hdd0_led_sata_pin>, <&hdd1_led_sata_pin>; pinctrl-names = "default"; diff --git a/arch/arm/boot/dts/armada-370-seagate-personal-cloud.dtsi b/arch/arm/boot/dts/armada-370-seagate-personal-cloud.dtsi index 01cded310cbc..d079a89ee5a2 100644 --- a/arch/arm/boot/dts/armada-370-seagate-personal-cloud.dtsi +++ b/arch/arm/boot/dts/armada-370-seagate-personal-cloud.dtsi @@ -24,7 +24,7 @@ stdout-path = "serial0:115200n8"; }; - memory { + memory@0 { device_type = "memory"; reg = <0x00000000 0x20000000>; /* 512 MB */ }; @@ -33,15 +33,6 @@ ranges = <MBUS_ID(0xf0, 0x01) 0 0xf1000000 0x100000 MBUS_ID(0x01, 0xe0) 0 0xfff00000 0x100000>; - pcie-controller { - status = "okay"; - - /* USB 3.0 Bridge ASM1042A */ - pcie@1,0 { - status = "okay"; - }; - }; - internal-regs { coherency-fabric@20200 { broken-idle; @@ -51,15 +42,6 @@ status = "okay"; }; - mdio { - pinctrl-0 = <&mdio_pins>; - pinctrl-names = "default"; - - phy0: ethernet-phy@0 { - reg = <0>; - }; - }; - ethernet@74000 { status = "okay"; pinctrl-0 = <&ge1_rgmii_pins>; @@ -107,19 +89,19 @@ #address-cells = <1>; #size-cells = <0>; - button@1 { + power { label = "Power button"; linux,code = <KEY_POWER>; gpios = <&gpio1 19 GPIO_ACTIVE_HIGH>; debounce-interval = <100>; }; - button@2 { + reset { label = "Reset Button"; linux,code = <KEY_RESTART>; gpios = <&gpio1 23 GPIO_ACTIVE_LOW>; debounce-interval = <100>; }; - button@3 { + button { label = "USB VBUS error"; linux,code = <KEY_UNKNOWN>; gpios = <&gpio1 21 GPIO_ACTIVE_LOW>; @@ -143,6 +125,24 @@ }; }; +&pciec { + status = "okay"; + + /* USB 3.0 Bridge ASM1042A */ + pcie@1,0 { + status = "okay"; + }; +}; + +&mdio { + pinctrl-0 = <&mdio_pins>; + pinctrl-names = "default"; + + phy0: ethernet-phy@0 { + reg = <0>; + }; +}; + &pinctrl { pinctrl-0 = <&sata_led_pin>; pinctrl-names = "default"; diff --git a/arch/arm/boot/dts/armada-370-synology-ds213j.dts b/arch/arm/boot/dts/armada-370-synology-ds213j.dts index a9cc42776874..99f9de229ea8 100644 --- a/arch/arm/boot/dts/armada-370-synology-ds213j.dts +++ b/arch/arm/boot/dts/armada-370-synology-ds213j.dts @@ -70,7 +70,7 @@ stdout-path = "serial0:115200n8"; }; - memory { + memory@0 { device_type = "memory"; reg = <0x00000000 0x20000000>; /* 512 MB */ }; @@ -127,12 +127,6 @@ status = "okay"; }; - mdio { - phy1: ethernet-phy@1 { /* Marvell 88E1512 */ - reg = <1>; - }; - }; - ethernet@70000 { status = "okay"; phy = <&phy1>; @@ -192,7 +186,7 @@ pinctrl-0 = <&sata1_pwr_pin &sata2_pwr_pin>; pinctrl-names = "default"; - sata1_regulator: sata1-regulator { + sata1_regulator: sata1-regulator@1 { compatible = "regulator-fixed"; reg = <1>; regulator-name = "SATA1 Power"; @@ -205,7 +199,7 @@ gpio = <&gpio1 5 GPIO_ACTIVE_HIGH>; }; - sata2_regulator: sata2-regulator { + sata2_regulator: sata2-regulator@2 { compatible = "regulator-fixed"; reg = <2>; regulator-name = "SATA2 Power"; @@ -220,6 +214,12 @@ }; }; +&mdio { + phy1: ethernet-phy@1 { /* Marvell 88E1512 */ + reg = <1>; + }; +}; + &pinctrl { disk1_led_pin: disk1-led-pin { marvell,pins = "mpp31"; diff --git a/arch/arm/boot/dts/armada-370-xp.dtsi b/arch/arm/boot/dts/armada-370-xp.dtsi index 3ccedc9dffb2..b0520bdeea27 100644 --- a/arch/arm/boot/dts/armada-370-xp.dtsi +++ b/arch/arm/boot/dts/armada-370-xp.dtsi @@ -50,8 +50,6 @@ * 370 and Armada XP SoC. */ -/include/ "skeleton64.dtsi" - #define MBUS_ID(target,attributes) (((target) << 24) | ((attributes) << 16)) / { @@ -86,7 +84,7 @@ pcie-mem-aperture = <0xf8000000 0x7e00000>; pcie-io-aperture = <0xffe00000 0x100000>; - devbus-bootcs { + devbus_bootcs: devbus-bootcs { compatible = "marvell,mvebu-devbus"; reg = <MBUS_ID(0xf0, 0x01) 0x10400 0x8>; ranges = <0 MBUS_ID(0x01, 0x2f) 0 0xffffffff>; @@ -96,7 +94,7 @@ status = "disabled"; }; - devbus-cs0 { + devbus_cs0: devbus-cs0 { compatible = "marvell,mvebu-devbus"; reg = <MBUS_ID(0xf0, 0x01) 0x10408 0x8>; ranges = <0 MBUS_ID(0x01, 0x3e) 0 0xffffffff>; @@ -106,7 +104,7 @@ status = "disabled"; }; - devbus-cs1 { + devbus_cs1: devbus-cs1 { compatible = "marvell,mvebu-devbus"; reg = <MBUS_ID(0xf0, 0x01) 0x10410 0x8>; ranges = <0 MBUS_ID(0x01, 0x3d) 0 0xffffffff>; @@ -116,7 +114,7 @@ status = "disabled"; }; - devbus-cs2 { + devbus_cs2: devbus-cs2 { compatible = "marvell,mvebu-devbus"; reg = <MBUS_ID(0xf0, 0x01) 0x10418 0x8>; ranges = <0 MBUS_ID(0x01, 0x3b) 0 0xffffffff>; @@ -126,7 +124,7 @@ status = "disabled"; }; - devbus-cs3 { + devbus_cs3: devbus-cs3 { compatible = "marvell,mvebu-devbus"; reg = <MBUS_ID(0xf0, 0x01) 0x10420 0x8>; ranges = <0 MBUS_ID(0x01, 0x37) 0 0xffffffff>; @@ -142,7 +140,7 @@ #size-cells = <1>; ranges = <0 MBUS_ID(0xf0, 0x01) 0 0x100000>; - rtc@10300 { + rtc: rtc@10300 { compatible = "marvell,orion-rtc"; reg = <0x10300 0x20>; interrupts = <50>; @@ -214,33 +212,38 @@ msi-controller; }; - coherency-fabric@20200 { + coherencyfab: coherency-fabric@20200 { compatible = "marvell,coherency-fabric"; reg = <0x20200 0xb0>, <0x21010 0x1c>; }; - timer@20300 { + timer: timer@20300 { reg = <0x20300 0x30>, <0x21040 0x30>; interrupts = <37>, <38>, <39>, <40>, <5>, <6>; }; - watchdog@20300 { + watchdog: watchdog@20300 { reg = <0x20300 0x34>, <0x20704 0x4>; }; - pmsu@22000 { + cpurst: cpurst@20800 { + compatible = "marvell,armada-370-cpu-reset"; + reg = <0x20800 0x8>; + }; + + pmsu: pmsu@22000 { compatible = "marvell,armada-370-pmsu"; reg = <0x22000 0x1000>; }; - usb@50000 { + usb0: usb@50000 { compatible = "marvell,orion-ehci"; reg = <0x50000 0x500>; interrupts = <45>; status = "disabled"; }; - usb@51000 { + usb1: usb@51000 { compatible = "marvell,orion-ehci"; reg = <0x51000 0x500>; interrupts = <46>; @@ -254,7 +257,7 @@ status = "disabled"; }; - mdio: mdio { + mdio: mdio@72004 { #address-cells = <1>; #size-cells = <0>; compatible = "marvell,orion-mdio"; @@ -269,7 +272,7 @@ status = "disabled"; }; - sata@a0000 { + sata: sata@a0000 { compatible = "marvell,armada-370-sata"; reg = <0xa0000 0x5000>; interrupts = <55>; @@ -278,7 +281,7 @@ status = "disabled"; }; - nand@d0000 { + nand: nand@d0000 { compatible = "marvell,armada370-nand"; reg = <0xd0000 0x54>; #address-cells = <1>; @@ -288,7 +291,7 @@ status = "disabled"; }; - mvsdio@d4000 { + sdio: mvsdio@d4000 { compatible = "marvell,orion-sdio"; reg = <0xd4000 0x200>; interrupts = <54>; diff --git a/arch/arm/boot/dts/armada-370.dtsi b/arch/arm/boot/dts/armada-370.dtsi index b4258105e91f..b704bcc597f7 100644 --- a/arch/arm/boot/dts/armada-370.dtsi +++ b/arch/arm/boot/dts/armada-370.dtsi @@ -50,9 +50,11 @@ */ #include "armada-370-xp.dtsi" -/include/ "skeleton.dtsi" / { + #address-cells = <1>; + #size-cells = <1>; + model = "Marvell Armada 370 family SoC"; compatible = "marvell,armada370", "marvell,armada-370-xp"; @@ -70,7 +72,7 @@ reg = <MBUS_ID(0x01, 0xe0) 0 0x100000>; }; - pcie-controller { + pciec: pcie-controller@82000000 { compatible = "marvell,armada-370-pcie"; status = "disabled"; device_type = "pci"; @@ -89,7 +91,7 @@ 0x82000000 0x2 0 MBUS_ID(0x08, 0xe8) 0 1 0 /* Port 1.0 MEM */ 0x81000000 0x2 0 MBUS_ID(0x08, 0xe0) 0 1 0 /* Port 1.0 IO */>; - pcie@1,0 { + pcie0: pcie@1,0 { device_type = "pci"; assigned-addresses = <0x82000800 0 0x40000 0 0x2000>; reg = <0x0800 0 0 0 0>; @@ -106,7 +108,7 @@ status = "disabled"; }; - pcie@2,0 { + pcie2: pcie@2,0 { device_type = "pci"; assigned-addresses = <0x82002800 0 0x80000 0 0x2000>; reg = <0x1000 0 0 0 0>; @@ -125,7 +127,7 @@ }; internal-regs { - L2: l2-cache { + L2: l2-cache@8000 { compatible = "marvell,aurora-outer-cache"; reg = <0x08000 0x1000>; cache-id-part = <0x100>; @@ -134,14 +136,6 @@ wt-override; }; - i2c0: i2c@11000 { - reg = <0x11000 0x20>; - }; - - i2c1: i2c@11100 { - reg = <0x11100 0x20>; - }; - gpio0: gpio@18100 { compatible = "marvell,orion-gpio"; reg = <0x18100 0x40>; @@ -175,22 +169,8 @@ interrupts = <91>; }; - /* - * Default UART pinctrl setting without RTS/CTS, can - * be overwritten on board level if a different - * configuration is used. - */ - uart0: serial@12000 { - pinctrl-0 = <&uart0_pins>; - pinctrl-names = "default"; - }; - - uart1: serial@12100 { - pinctrl-0 = <&uart1_pins>; - pinctrl-names = "default"; - }; - system-controller@18200 { + systemc: system-controller@18200 { compatible = "marvell,armada-370-xp-system-controller"; reg = <0x18200 0x100>; }; @@ -208,37 +188,18 @@ #clock-cells = <1>; }; - thermal@18300 { + thermal: thermal@18300 { compatible = "marvell,armada370-thermal"; reg = <0x18300 0x4 0x18304 0x4>; status = "okay"; }; - sscg@18330 { + sscg: sscg@18330 { reg = <0x18330 0x4>; }; - interrupt-controller@20a00 { - reg = <0x20a00 0x1d0>, <0x21870 0x58>; - }; - - timer@20300 { - compatible = "marvell,armada-370-timer"; - clocks = <&coreclk 2>; - }; - - watchdog@20300 { - compatible = "marvell,armada-370-wdt"; - clocks = <&coreclk 2>; - }; - - cpurst@20800 { - compatible = "marvell,armada-370-cpu-reset"; - reg = <0x20800 0x8>; - }; - - cpu-config@21000 { + cpuconf: cpu-config@21000 { compatible = "marvell,armada-370-cpu-config"; reg = <0x21000 0x8>; }; @@ -253,15 +214,7 @@ status = "disabled"; }; - usb@50000 { - clocks = <&coreclk 0>; - }; - - usb@51000 { - clocks = <&coreclk 0>; - }; - - xor@60800 { + xor0: xor@60800 { compatible = "marvell,orion-xor"; reg = <0x60800 0x100 0x60A00 0x100>; @@ -280,7 +233,7 @@ }; }; - xor@60900 { + xor1: xor@60900 { compatible = "marvell,orion-xor"; reg = <0x60900 0x100 0x60b00 0x100>; @@ -299,15 +252,7 @@ }; }; - ethernet@70000 { - compatible = "marvell,armada-370-neta"; - }; - - ethernet@74000 { - compatible = "marvell,armada-370-neta"; - }; - - crypto@90000 { + cesa: crypto@90000 { compatible = "marvell,armada-370-crypto"; reg = <0x90000 0x10000>; reg-names = "regs"; @@ -342,6 +287,59 @@ }; }; +/* + * Default UART pinctrl setting without RTS/CTS, can be overwritten on + * board level if a different configuration is used. + */ + +&uart0 { + pinctrl-0 = <&uart0_pins>; + pinctrl-names = "default"; +}; + +&uart1 { + pinctrl-0 = <&uart1_pins>; + pinctrl-names = "default"; +}; + +&i2c0 { + reg = <0x11000 0x20>; +}; + +&i2c1 { + reg = <0x11100 0x20>; +}; + +&mpic { + reg = <0x20a00 0x1d0>, <0x21870 0x58>; +}; + +&timer { + compatible = "marvell,armada-370-timer"; + clocks = <&coreclk 2>; +}; + +&watchdog { + compatible = "marvell,armada-370-wdt"; + clocks = <&coreclk 2>; +}; + +&usb0 { + clocks = <&coreclk 0>; +}; + +&usb1 { + clocks = <&coreclk 0>; +}; + +ð0 { + compatible = "marvell,armada-370-neta"; +}; + +ð1 { + compatible = "marvell,armada-370-neta"; +}; + &pinctrl { compatible = "marvell,mv88f6710-pinctrl"; diff --git a/arch/arm/boot/dts/armada-375-db.dts b/arch/arm/boot/dts/armada-375-db.dts index cded5f0a262d..ef45cbeb3e7d 100644 --- a/arch/arm/boot/dts/armada-375-db.dts +++ b/arch/arm/boot/dts/armada-375-db.dts @@ -58,7 +58,7 @@ stdout-path = "serial0:115200n8"; }; - memory { + memory@0 { device_type = "memory"; reg = <0x00000000 0x40000000>; /* 1 GB */ }; @@ -69,138 +69,141 @@ MBUS_ID(0x09, 0x09) 0 0xf1100000 0x10000 MBUS_ID(0x09, 0x05) 0 0xf1110000 0x10000>; - internal-regs { - spi@10600 { - pinctrl-0 = <&spi0_pins>; - pinctrl-names = "default"; - /* - * SPI conflicts with NAND, so we disable it - * here, and select NAND as the enabled device - * by default. - */ - status = "disabled"; - - spi-flash@0 { - #address-cells = <1>; - #size-cells = <1>; - compatible = "n25q128a13", "jedec,spi-nor"; - reg = <0>; /* Chip select 0 */ - spi-max-frequency = <108000000>; - }; - }; - - i2c@11000 { - status = "okay"; - clock-frequency = <100000>; - pinctrl-0 = <&i2c0_pins>; - pinctrl-names = "default"; - }; - - i2c@11100 { - status = "okay"; - clock-frequency = <100000>; - pinctrl-0 = <&i2c1_pins>; - pinctrl-names = "default"; - }; - - serial@12000 { - status = "okay"; - }; - - pinctrl { - sdio_st_pins: sdio-st-pins { - marvell,pins = "mpp44", "mpp45"; - marvell,function = "gpio"; - }; - }; - - sata@a0000 { - status = "okay"; - nr-ports = <2>; - }; - - nand: nand@d0000 { - pinctrl-0 = <&nand_pins>; - pinctrl-names = "default"; - status = "okay"; - num-cs = <1>; - marvell,nand-keep-config; - marvell,nand-enable-arbiter; - nand-on-flash-bbt; - nand-ecc-strength = <4>; - nand-ecc-step-size = <512>; - - partition@0 { - label = "U-Boot"; - reg = <0 0x800000>; - }; - partition@800000 { - label = "Linux"; - reg = <0x800000 0x800000>; - }; - partition@1000000 { - label = "Filesystem"; - reg = <0x1000000 0x3f000000>; - }; - }; - - usb@54000 { - status = "okay"; - }; - - usb3@58000 { - status = "okay"; - }; - - mvsdio@d4000 { - pinctrl-0 = <&sdio_pins &sdio_st_pins>; - pinctrl-names = "default"; - status = "okay"; - cd-gpios = <&gpio1 12 GPIO_ACTIVE_HIGH>; - wp-gpios = <&gpio1 13 GPIO_ACTIVE_HIGH>; - }; - - mdio { - phy0: ethernet-phy@0 { - reg = <0>; - }; - - phy3: ethernet-phy@3 { - reg = <3>; - }; - }; - - ethernet@f0000 { - status = "okay"; - - eth0@c4000 { - status = "okay"; - phy = <&phy0>; - phy-mode = "rgmii-id"; - }; - - eth1@c5000 { - status = "okay"; - phy = <&phy3>; - phy-mode = "gmii"; - }; - }; - }; - - pcie-controller { - status = "okay"; - /* - * The two PCIe units are accessible through - * standard PCIe slots on the board. - */ - pcie@1,0 { - /* Port 0, Lane 0 */ - status = "okay"; - }; - pcie@2,0 { - /* Port 1, Lane 0 */ - status = "okay"; - }; - }; }; }; +&pciec { + status = "okay"; +}; + +/* + * The two PCIe units are accessible through + * standard PCIe slots on the board. + */ +&pcie0 { + /* Port 0, Lane 0 */ + status = "okay"; +}; + +&pcie1 { + /* Port 1, Lane 0 */ + status = "okay"; +}; + + +&spi0 { + pinctrl-0 = <&spi0_pins>; + pinctrl-names = "default"; + + /* + * SPI conflicts with NAND, so we disable it here, and + * select NAND as the enabled device by default. + */ + + status = "disabled"; + + spi-flash@0 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "n25q128a13", "jedec,spi-nor"; + reg = <0>; /* Chip select 0 */ + spi-max-frequency = <108000000>; + }; +}; + +&i2c0 { + status = "okay"; + clock-frequency = <100000>; + pinctrl-0 = <&i2c0_pins>; + pinctrl-names = "default"; +}; + +&i2c1 { + status = "okay"; + clock-frequency = <100000>; + pinctrl-0 = <&i2c1_pins>; + pinctrl-names = "default"; +}; + +&uart0 { + status = "okay"; +}; + +&pinctrl { + sdio_st_pins: sdio-st-pins { + marvell,pins = "mpp44", "mpp45"; + marvell,function = "gpio"; + }; +}; + +&sata { + status = "okay"; + nr-ports = <2>; +}; + +&nand { + pinctrl-0 = <&nand_pins>; + pinctrl-names = "default"; + status = "okay"; + num-cs = <1>; + marvell,nand-keep-config; + marvell,nand-enable-arbiter; + nand-on-flash-bbt; + nand-ecc-strength = <4>; + nand-ecc-step-size = <512>; + + partition@0 { + label = "U-Boot"; + reg = <0 0x800000>; + }; + partition@800000 { + label = "Linux"; + reg = <0x800000 0x800000>; + }; + partition@1000000 { + label = "Filesystem"; + reg = <0x1000000 0x3f000000>; + }; +}; + +&usb1 { + status = "okay"; +}; + +&usb2 { + status = "okay"; +}; + +&sdio { + pinctrl-0 = <&sdio_pins &sdio_st_pins>; + pinctrl-names = "default"; + status = "okay"; + cd-gpios = <&gpio1 12 GPIO_ACTIVE_HIGH>; + wp-gpios = <&gpio1 13 GPIO_ACTIVE_HIGH>; +}; + +&mdio { + phy0: ethernet-phy@0 { + reg = <0>; + }; + + phy3: ethernet-phy@3 { + reg = <3>; + }; +}; + +ðernet { + status = "okay"; +}; + + +ð0 { + status = "okay"; + phy = <&phy0>; + phy-mode = "rgmii-id"; +}; + +ð1 { + status = "okay"; + phy = <&phy3>; + phy-mode = "gmii"; +}; diff --git a/arch/arm/boot/dts/armada-375.dtsi b/arch/arm/boot/dts/armada-375.dtsi index cc952cf8ec30..f515591e8733 100644 --- a/arch/arm/boot/dts/armada-375.dtsi +++ b/arch/arm/boot/dts/armada-375.dtsi @@ -45,7 +45,6 @@ * OTHER DEALINGS IN THE SOFTWARE. */ -#include "skeleton.dtsi" #include <dt-bindings/interrupt-controller/arm-gic.h> #include <dt-bindings/interrupt-controller/irq.h> #include <dt-bindings/phy/phy.h> @@ -53,6 +52,9 @@ #define MBUS_ID(target,attributes) (((target) << 24) | ((attributes) << 16)) / { + #address-cells = <1>; + #size-cells = <1>; + model = "Marvell Armada 375 family SoC"; compatible = "marvell,armada375"; @@ -65,7 +67,7 @@ }; clocks { - /* 2 GHz fixed main PLL */ + /* 1 GHz fixed main PLL */ mainpll: mainpll { compatible = "fixed-clock"; #clock-cells = <0>; @@ -84,12 +86,12 @@ #size-cells = <0>; enable-method = "marvell,armada-375-smp"; - cpu@0 { + cpu0: cpu@0 { device_type = "cpu"; compatible = "arm,cortex-a9"; reg = <0>; }; - cpu@1 { + cpu1: cpu@1 { device_type = "cpu"; compatible = "arm,cortex-a9"; reg = <1>; @@ -115,7 +117,7 @@ reg = <MBUS_ID(0x01, 0x1d) 0 0x100000>; }; - devbus-bootcs { + devbus_bootcs: devbus-bootcs { compatible = "marvell,mvebu-devbus"; reg = <MBUS_ID(0xf0, 0x01) 0x10400 0x8>; ranges = <0 MBUS_ID(0x01, 0x2f) 0 0xffffffff>; @@ -125,7 +127,7 @@ status = "disabled"; }; - devbus-cs0 { + devbus_cs0: devbus-cs0 { compatible = "marvell,mvebu-devbus"; reg = <MBUS_ID(0xf0, 0x01) 0x10408 0x8>; ranges = <0 MBUS_ID(0x01, 0x3e) 0 0xffffffff>; @@ -135,7 +137,7 @@ status = "disabled"; }; - devbus-cs1 { + devbus_cs1: devbus-cs1 { compatible = "marvell,mvebu-devbus"; reg = <MBUS_ID(0xf0, 0x01) 0x10410 0x8>; ranges = <0 MBUS_ID(0x01, 0x3d) 0 0xffffffff>; @@ -145,7 +147,7 @@ status = "disabled"; }; - devbus-cs2 { + devbus_cs2: devbus-cs2 { compatible = "marvell,mvebu-devbus"; reg = <MBUS_ID(0xf0, 0x01) 0x10418 0x8>; ranges = <0 MBUS_ID(0x01, 0x3b) 0 0xffffffff>; @@ -155,7 +157,7 @@ status = "disabled"; }; - devbus-cs3 { + devbus_cs3: devbus-cs3 { compatible = "marvell,mvebu-devbus"; reg = <MBUS_ID(0xf0, 0x01) 0x10420 0x8>; ranges = <0 MBUS_ID(0x01, 0x37) 0 0xffffffff>; @@ -182,12 +184,12 @@ prefetch-data = <1>; }; - scu@c000 { + scu: scu@c000 { compatible = "arm,cortex-a9-scu"; reg = <0xc000 0x58>; }; - timer@c600 { + timer0: timer@c600 { compatible = "arm,cortex-a9-twd-timer"; reg = <0xc600 0x20>; interrupts = <GIC_PPI 13 (IRQ_TYPE_EDGE_RISING | GIC_CPU_MASK_SIMPLE(2))>; @@ -203,7 +205,7 @@ <0xc100 0x100>; }; - mdio { + mdio: mdio@c0054 { #address-cells = <1>; #size-cells = <0>; compatible = "marvell,orion-mdio"; @@ -212,7 +214,7 @@ }; /* Network controller */ - ethernet@f0000 { + ethernet: ethernet@f0000 { compatible = "marvell,armada-375-pp2"; reg = <0xf0000 0xa000>, /* Packet Processor regs */ <0xc0000 0x3060>, /* LMS regs */ @@ -222,20 +224,20 @@ clock-names = "pp_clk", "gop_clk"; status = "disabled"; - eth0: eth0@c4000 { + eth0: eth0 { interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>; port-id = <0>; status = "disabled"; }; - eth1: eth1@c5000 { + eth1: eth1 { interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>; port-id = <1>; status = "disabled"; }; }; - rtc@10300 { + rtc: rtc@10300 { compatible = "marvell,orion-rtc"; reg = <0x10300 0x20>; interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>; @@ -307,7 +309,7 @@ status = "disabled"; }; - pinctrl { + pinctrl: pinctrl@18000 { compatible = "marvell,mv88f6720-pinctrl"; reg = <0x18000 0x24>; @@ -382,7 +384,7 @@ interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>; }; - system-controller@18200 { + systemc: system-controller@18200 { compatible = "marvell,armada-375-system-controller"; reg = <0x18200 0x100>; }; @@ -415,7 +417,7 @@ interrupts = <GIC_PPI 15 IRQ_TYPE_LEVEL_HIGH>; }; - timer@20300 { + timer1: timer@20300 { compatible = "marvell,armada-375-timer", "marvell,armada-370-timer"; reg = <0x20300 0x30>, <0x21040 0x30>; interrupts-extended = <&gic GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>, @@ -428,24 +430,24 @@ clock-names = "nbclk", "fixed"; }; - watchdog@20300 { + watchdog: watchdog@20300 { compatible = "marvell,armada-375-wdt"; reg = <0x20300 0x34>, <0x20704 0x4>, <0x18254 0x4>; clocks = <&coreclk 0>, <&refclk>; clock-names = "nbclk", "fixed"; }; - cpurst@20800 { + cpurst: cpurst@20800 { compatible = "marvell,armada-370-cpu-reset"; reg = <0x20800 0x10>; }; - coherency-fabric@21010 { + coherencyfab: coherency-fabric@21010 { compatible = "marvell,armada-375-coherency-fabric"; reg = <0x21010 0x1c>; }; - usb@50000 { + usb0: usb@50000 { compatible = "marvell,orion-ehci"; reg = <0x50000 0x500>; interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>; @@ -455,7 +457,7 @@ status = "disabled"; }; - usb@54000 { + usb1: usb@54000 { compatible = "marvell,orion-ehci"; reg = <0x54000 0x500>; interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>; @@ -463,7 +465,7 @@ status = "disabled"; }; - usb3@58000 { + usb2: usb3@58000 { compatible = "marvell,armada-375-xhci"; reg = <0x58000 0x20000>,<0x5b880 0x80>; interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>; @@ -473,7 +475,7 @@ status = "disabled"; }; - xor@60800 { + xor0: xor@60800 { compatible = "marvell,orion-xor"; reg = <0x60800 0x100 0x60A00 0x100>; @@ -493,7 +495,7 @@ }; }; - xor@60900 { + xor1: xor@60900 { compatible = "marvell,orion-xor"; reg = <0x60900 0x100 0x60b00 0x100>; @@ -513,7 +515,7 @@ }; }; - crypto@90000 { + cesa: crypto@90000 { compatible = "marvell,armada-375-crypto"; reg = <0x90000 0x10000>; reg-names = "regs"; @@ -528,7 +530,7 @@ marvell,crypto-sram-size = <0x800>; }; - sata@a0000 { + sata: sata@a0000 { compatible = "marvell,armada-370-sata"; reg = <0xa0000 0x5000>; interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>; @@ -537,7 +539,7 @@ status = "disabled"; }; - nand@d0000 { + nand: nand@d0000 { compatible = "marvell,armada370-nand"; reg = <0xd0000 0x54>; #address-cells = <1>; @@ -547,7 +549,7 @@ status = "disabled"; }; - mvsdio@d4000 { + sdio: mvsdio@d4000 { compatible = "marvell,orion-sdio"; reg = <0xd4000 0x200>; interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>; @@ -559,7 +561,7 @@ status = "disabled"; }; - thermal@e8078 { + thermal: thermal@e8078 { compatible = "marvell,armada375-thermal"; reg = <0xe8078 0x4>, <0xe807c 0x8>; status = "okay"; @@ -580,7 +582,7 @@ }; }; - pcie-controller { + pciec: pcie-controller@82000000 { compatible = "marvell,armada-370-pcie"; status = "disabled"; device_type = "pci"; @@ -599,7 +601,7 @@ 0x82000000 0x2 0 MBUS_ID(0x04, 0xd8) 0 1 0 /* Port 1 MEM */ 0x81000000 0x2 0 MBUS_ID(0x04, 0xd0) 0 1 0 /* Port 1 IO */>; - pcie@1,0 { + pcie0: pcie@1,0 { device_type = "pci"; assigned-addresses = <0x82000800 0 0x40000 0 0x2000>; reg = <0x0800 0 0 0 0>; @@ -616,7 +618,7 @@ status = "disabled"; }; - pcie@2,0 { + pcie1: pcie@2,0 { device_type = "pci"; assigned-addresses = <0x82000800 0 0x44000 0 0x2000>; reg = <0x1000 0 0 0 0>; diff --git a/arch/arm/boot/dts/armada-38x.dtsi b/arch/arm/boot/dts/armada-38x.dtsi index 2d7668848c5a..7450e9fea45d 100644 --- a/arch/arm/boot/dts/armada-38x.dtsi +++ b/arch/arm/boot/dts/armada-38x.dtsi @@ -661,7 +661,7 @@ }; clocks { - /* 2 GHz fixed main PLL */ + /* 1 GHz fixed main PLL */ mainpll: mainpll { compatible = "fixed-clock"; #clock-cells = <0>; diff --git a/arch/arm/boot/dts/armada-39x.dtsi b/arch/arm/boot/dts/armada-39x.dtsi index 34cba87f9200..de171baffcf6 100644 --- a/arch/arm/boot/dts/armada-39x.dtsi +++ b/arch/arm/boot/dts/armada-39x.dtsi @@ -573,7 +573,7 @@ }; clocks { - /* 2 GHz fixed main PLL */ + /* 1 GHz fixed main PLL */ mainpll: mainpll { compatible = "fixed-clock"; #clock-cells = <0>; diff --git a/arch/arm/boot/dts/armada-xp-axpwifiap.dts b/arch/arm/boot/dts/armada-xp-axpwifiap.dts index ce152719bc28..1e1fc4fccbad 100644 --- a/arch/arm/boot/dts/armada-xp-axpwifiap.dts +++ b/arch/arm/boot/dts/armada-xp-axpwifiap.dts @@ -62,7 +62,7 @@ stdout-path = "serial0:115200n8"; }; - memory { + memory@0 { device_type = "memory"; reg = <0x00000000 0x00000000 0x00000000 0x40000000>; /* 1GB */ }; @@ -73,28 +73,6 @@ MBUS_ID(0x09, 0x09) 0 0 0xf1100000 0x10000 MBUS_ID(0x09, 0x05) 0 0 0xf1110000 0x10000>; - pcie-controller { - status = "okay"; - - /* First mini-PCIe port */ - pcie@1,0 { - /* Port 0, Lane 0 */ - status = "okay"; - }; - - /* Second mini-PCIe port */ - pcie@2,0 { - /* Port 0, Lane 1 */ - status = "okay"; - }; - - /* Renesas uPD720202 USB 3.0 controller */ - pcie@3,0 { - /* Port 0, Lane 3 */ - status = "okay"; - }; - }; - internal-regs { /* UART0 */ serial@12000 { @@ -111,16 +89,6 @@ status = "okay"; }; - mdio { - phy0: ethernet-phy@0 { - reg = <0>; - }; - - phy1: ethernet-phy@1 { - reg = <1>; - }; - }; - ethernet@70000 { pinctrl-0 = <&ge0_rgmii_pins>; pinctrl-names = "default"; @@ -145,7 +113,7 @@ pinctrl-0 = <&keys_pin>; pinctrl-names = "default"; - button@1 { + reset { label = "Factory Reset Button"; linux,code = <KEY_SETUP>; gpios = <&gpio1 1 GPIO_ACTIVE_LOW>; @@ -153,6 +121,38 @@ }; }; +&mdio { + phy0: ethernet-phy@0 { + reg = <0>; + }; + + phy1: ethernet-phy@1 { + reg = <1>; + }; +}; + +&pciec { + status = "okay"; + + /* First mini-PCIe port */ + pcie@1,0 { + /* Port 0, Lane 0 */ + status = "okay"; + }; + + /* Second mini-PCIe port */ + pcie@2,0 { + /* Port 0, Lane 1 */ + status = "okay"; + }; + + /* Renesas uPD720202 USB 3.0 controller */ + pcie@3,0 { + /* Port 0, Lane 3 */ + status = "okay"; + }; +}; + &pinctrl { pinctrl-0 = <&phy_int_pin>; pinctrl-names = "default"; diff --git a/arch/arm/boot/dts/armada-xp-db.dts b/arch/arm/boot/dts/armada-xp-db.dts index 075120bc3ec4..44a724d39dbe 100644 --- a/arch/arm/boot/dts/armada-xp-db.dts +++ b/arch/arm/boot/dts/armada-xp-db.dts @@ -67,7 +67,7 @@ stdout-path = "serial0:115200n8"; }; - memory { + memory@0 { device_type = "memory"; reg = <0 0x00000000 0 0x80000000>; /* 2 GB */ }; @@ -108,39 +108,6 @@ }; }; - pcie-controller { - status = "okay"; - - /* - * All 6 slots are physically present as - * standard PCIe slots on the board. - */ - pcie@1,0 { - /* Port 0, Lane 0 */ - status = "okay"; - }; - pcie@2,0 { - /* Port 0, Lane 1 */ - status = "okay"; - }; - pcie@3,0 { - /* Port 0, Lane 2 */ - status = "okay"; - }; - pcie@4,0 { - /* Port 0, Lane 3 */ - status = "okay"; - }; - pcie@9,0 { - /* Port 2, Lane 0 */ - status = "okay"; - }; - pcie@10,0 { - /* Port 3, Lane 0 */ - status = "okay"; - }; - }; - internal-regs { serial@12000 { status = "okay"; @@ -160,24 +127,6 @@ status = "okay"; }; - mdio { - phy0: ethernet-phy@0 { - reg = <0>; - }; - - phy1: ethernet-phy@1 { - reg = <1>; - }; - - phy2: ethernet-phy@2 { - reg = <25>; - }; - - phy3: ethernet-phy@3 { - reg = <27>; - }; - }; - ethernet@70000 { status = "okay"; phy = <&phy0>; @@ -266,6 +215,57 @@ }; }; +&pciec { + status = "okay"; + + /* + * All 6 slots are physically present as + * standard PCIe slots on the board. + */ + pcie@1,0 { + /* Port 0, Lane 0 */ + status = "okay"; + }; + pcie@2,0 { + /* Port 0, Lane 1 */ + status = "okay"; + }; + pcie@3,0 { + /* Port 0, Lane 2 */ + status = "okay"; + }; + pcie@4,0 { + /* Port 0, Lane 3 */ + status = "okay"; + }; + pcie@9,0 { + /* Port 2, Lane 0 */ + status = "okay"; + }; + pcie@10,0 { + /* Port 3, Lane 0 */ + status = "okay"; + }; +}; + +&mdio { + phy0: ethernet-phy@0 { + reg = <0>; + }; + + phy1: ethernet-phy@1 { + reg = <1>; + }; + + phy2: ethernet-phy@2 { + reg = <25>; + }; + + phy3: ethernet-phy@3 { + reg = <27>; + }; +}; + &spi0 { status = "okay"; diff --git a/arch/arm/boot/dts/armada-xp-gp.dts b/arch/arm/boot/dts/armada-xp-gp.dts index 190e4eccb180..72cb8fa377e3 100644 --- a/arch/arm/boot/dts/armada-xp-gp.dts +++ b/arch/arm/boot/dts/armada-xp-gp.dts @@ -68,7 +68,7 @@ stdout-path = "serial0:115200n8"; }; - memory { + memory@0 { device_type = "memory"; /* * 8 GB of plug-in RAM modules by default.The amount @@ -127,27 +127,6 @@ }; }; - pcie-controller { - status = "okay"; - - /* - * The 3 slots are physically present as - * standard PCIe slots on the board. - */ - pcie@1,0 { - /* Port 0, Lane 0 */ - status = "okay"; - }; - pcie@9,0 { - /* Port 2, Lane 0 */ - status = "okay"; - }; - pcie@10,0 { - /* Port 3, Lane 0 */ - status = "okay"; - }; - }; - internal-regs { serial@12000 { status = "okay"; @@ -175,24 +154,6 @@ status = "okay"; }; - mdio { - phy0: ethernet-phy@0 { - reg = <16>; - }; - - phy1: ethernet-phy@1 { - reg = <17>; - }; - - phy2: ethernet-phy@2 { - reg = <18>; - }; - - phy3: ethernet-phy@3 { - reg = <19>; - }; - }; - ethernet@70000 { status = "okay"; phy = <&phy0>; @@ -251,6 +212,45 @@ }; }; +&pciec { + status = "okay"; + + /* + * The 3 slots are physically present as + * standard PCIe slots on the board. + */ + pcie@1,0 { + /* Port 0, Lane 0 */ + status = "okay"; + }; + pcie@9,0 { + /* Port 2, Lane 0 */ + status = "okay"; + }; + pcie@10,0 { + /* Port 3, Lane 0 */ + status = "okay"; + }; +}; + +&mdio { + phy0: ethernet-phy@0 { + reg = <16>; + }; + + phy1: ethernet-phy@1 { + reg = <17>; + }; + + phy2: ethernet-phy@2 { + reg = <18>; + }; + + phy3: ethernet-phy@3 { + reg = <19>; + }; +}; + &spi0 { status = "okay"; diff --git a/arch/arm/boot/dts/armada-xp-lenovo-ix4-300d.dts b/arch/arm/boot/dts/armada-xp-lenovo-ix4-300d.dts index 8af463f26ea1..d848ae9007db 100644 --- a/arch/arm/boot/dts/armada-xp-lenovo-ix4-300d.dts +++ b/arch/arm/boot/dts/armada-xp-lenovo-ix4-300d.dts @@ -57,7 +57,7 @@ stdout-path = "serial0:115200n8"; }; - memory { + memory@0 { device_type = "memory"; reg = <0 0x00000000 0 0x20000000>; /* 512MB */ }; @@ -68,37 +68,11 @@ MBUS_ID(0x09, 0x09) 0 0 0xf1100000 0x10000 MBUS_ID(0x09, 0x05) 0 0 0xf1110000 0x10000>; - pcie-controller { - status = "okay"; - - /* Quad port sata: Marvell 88SX7042 */ - pcie@1,0 { - /* Port 0, Lane 0 */ - status = "okay"; - }; - - /* USB 3.0 xHCI controller: NEC D720200F1 */ - pcie@5,0 { - /* Port 1, Lane 0 */ - status = "okay"; - }; - }; - internal-regs { serial@12000 { status = "okay"; }; - mdio { - phy0: ethernet-phy@0 { /* Marvell 88E1318 */ - reg = <0>; - }; - - phy1: ethernet-phy@1 { /* Marvell 88E1318 */ - reg = <1>; - }; - }; - ethernet@70000 { pinctrl-0 = <&ge0_rgmii_pins>; pinctrl-names = "default"; @@ -295,6 +269,31 @@ gpios = <&gpio0 24 GPIO_ACTIVE_HIGH>; }; }; +&pciec { + status = "okay"; + + /* Quad port sata: Marvell 88SX7042 */ + pcie@1,0 { + /* Port 0, Lane 0 */ + status = "okay"; + }; + + /* USB 3.0 xHCI controller: NEC D720200F1 */ + pcie@5,0 { + /* Port 1, Lane 0 */ + status = "okay"; + }; +}; + +&mdio { + phy0: ethernet-phy@0 { /* Marvell 88E1318 */ + reg = <0>; + }; + + phy1: ethernet-phy@1 { /* Marvell 88E1318 */ + reg = <1>; + }; +}; &pinctrl { poweroff_pin: poweroff-pin { diff --git a/arch/arm/boot/dts/armada-xp-linksys-mamba.dts b/arch/arm/boot/dts/armada-xp-linksys-mamba.dts index 076f27f22c3b..83ac884c0f8a 100644 --- a/arch/arm/boot/dts/armada-xp-linksys-mamba.dts +++ b/arch/arm/boot/dts/armada-xp-linksys-mamba.dts @@ -62,7 +62,7 @@ stdout-path = &uart0; }; - memory { + memory@0 { device_type = "memory"; reg = <0x00000000 0x00000000 0x00000000 0x10000000>; /* 256MB */ }; @@ -73,28 +73,6 @@ MBUS_ID(0x09, 0x09) 0 0 0xf1100000 0x10000 MBUS_ID(0x09, 0x05) 0 0 0xf1110000 0x10000>; - pcie-controller { - status = "okay"; - - /* Etron EJ168 USB 3.0 controller */ - pcie@1,0 { - /* Port 0, Lane 0 */ - status = "okay"; - }; - - /* First mini-PCIe port */ - pcie@2,0 { - /* Port 0, Lane 1 */ - status = "okay"; - }; - - /* Second mini-PCIe port */ - pcie@3,0 { - /* Port 0, Lane 3 */ - status = "okay"; - }; - }; - internal-regs { rtc@10300 { @@ -289,13 +267,13 @@ pinctrl-0 = <&keys_pin>; pinctrl-names = "default"; - button@1 { + wps { label = "WPS"; linux,code = <KEY_WPS_BUTTON>; gpios = <&gpio1 0 GPIO_ACTIVE_LOW>; }; - button@2 { + reset { label = "Factory Reset Button"; linux,code = <KEY_RESTART>; gpios = <&gpio1 1 GPIO_ACTIVE_LOW>; @@ -323,7 +301,7 @@ 4500 1>; }; - dsa@0 { + dsa { compatible = "marvell,dsa"; #address-cells = <2>; #size-cells = <0>; @@ -369,6 +347,28 @@ }; }; +&pciec { + status = "okay"; + + /* Etron EJ168 USB 3.0 controller */ + pcie@1,0 { + /* Port 0, Lane 0 */ + status = "okay"; + }; + + /* First mini-PCIe port */ + pcie@2,0 { + /* Port 0, Lane 1 */ + status = "okay"; + }; + + /* Second mini-PCIe port */ + pcie@3,0 { + /* Port 0, Lane 3 */ + status = "okay"; + }; +}; + &pinctrl { keys_pin: keys-pin { diff --git a/arch/arm/boot/dts/armada-xp-matrix.dts b/arch/arm/boot/dts/armada-xp-matrix.dts index 6522b04f4a8e..16277380e714 100644 --- a/arch/arm/boot/dts/armada-xp-matrix.dts +++ b/arch/arm/boot/dts/armada-xp-matrix.dts @@ -55,7 +55,7 @@ stdout-path = "serial0:115200n8"; }; - memory { + memory@0 { device_type = "memory"; /* * This board has 4 GB of RAM, but the last 256 MB of @@ -99,18 +99,18 @@ }; }; - pcie-controller { - status = "okay"; - - pcie@1,0 { - /* Port 0, Lane 0 */ - status = "okay"; - }; - }; - usb@50000 { status = "okay"; }; }; }; }; + +&pciec { + status = "okay"; + + pcie@1,0 { + /* Port 0, Lane 0 */ + status = "okay"; + }; +}; diff --git a/arch/arm/boot/dts/armada-xp-mv78230.dtsi b/arch/arm/boot/dts/armada-xp-mv78230.dtsi index 6e6d0f04bf2b..05c164b5786d 100644 --- a/arch/arm/boot/dts/armada-xp-mv78230.dtsi +++ b/arch/arm/boot/dts/armada-xp-mv78230.dtsi @@ -86,7 +86,7 @@ * configured as x4 or quad x1 lanes. One unit is * x1 only. */ - pcie-controller { + pciec: pcie-controller@82000000 { compatible = "marvell,armada-xp-pcie"; status = "disabled"; device_type = "pci"; @@ -114,7 +114,7 @@ 0x82000000 0x5 0 MBUS_ID(0x08, 0xe8) 0 1 0 /* Port 1.0 MEM */ 0x81000000 0x5 0 MBUS_ID(0x08, 0xe0) 0 1 0 /* Port 1.0 IO */>; - pcie@1,0 { + pcie1: pcie@1,0 { device_type = "pci"; assigned-addresses = <0x82000800 0 0x40000 0 0x2000>; reg = <0x0800 0 0 0 0>; @@ -131,7 +131,7 @@ status = "disabled"; }; - pcie@2,0 { + pcie2: pcie@2,0 { device_type = "pci"; assigned-addresses = <0x82000800 0 0x44000 0 0x2000>; reg = <0x1000 0 0 0 0>; @@ -148,7 +148,7 @@ status = "disabled"; }; - pcie@3,0 { + pcie3: pcie@3,0 { device_type = "pci"; assigned-addresses = <0x82000800 0 0x48000 0 0x2000>; reg = <0x1800 0 0 0 0>; @@ -165,7 +165,7 @@ status = "disabled"; }; - pcie@4,0 { + pcie4: pcie@4,0 { device_type = "pci"; assigned-addresses = <0x82000800 0 0x4c000 0 0x2000>; reg = <0x2000 0 0 0 0>; @@ -182,7 +182,7 @@ status = "disabled"; }; - pcie@5,0 { + pcie5: pcie@5,0 { device_type = "pci"; assigned-addresses = <0x82000800 0 0x80000 0 0x2000>; reg = <0x2800 0 0 0 0>; diff --git a/arch/arm/boot/dts/armada-xp-mv78260.dtsi b/arch/arm/boot/dts/armada-xp-mv78260.dtsi index c5fdc99f0dbe..07894b0d3e59 100644 --- a/arch/arm/boot/dts/armada-xp-mv78260.dtsi +++ b/arch/arm/boot/dts/armada-xp-mv78260.dtsi @@ -87,7 +87,7 @@ * configured as x4 or quad x1 lanes. One unit is * x4 only. */ - pcie-controller { + pciec: pcie-controller@82000000 { compatible = "marvell,armada-xp-pcie"; status = "disabled"; device_type = "pci"; @@ -129,7 +129,7 @@ 0x82000000 0x9 0 MBUS_ID(0x04, 0xf8) 0 1 0 /* Port 2.0 MEM */ 0x81000000 0x9 0 MBUS_ID(0x04, 0xf0) 0 1 0 /* Port 2.0 IO */>; - pcie@1,0 { + pcie1: pcie@1,0 { device_type = "pci"; assigned-addresses = <0x82000800 0 0x40000 0 0x2000>; reg = <0x0800 0 0 0 0>; @@ -146,7 +146,7 @@ status = "disabled"; }; - pcie@2,0 { + pcie2: pcie@2,0 { device_type = "pci"; assigned-addresses = <0x82000800 0 0x44000 0 0x2000>; reg = <0x1000 0 0 0 0>; @@ -163,7 +163,7 @@ status = "disabled"; }; - pcie@3,0 { + pcie3: pcie@3,0 { device_type = "pci"; assigned-addresses = <0x82000800 0 0x48000 0 0x2000>; reg = <0x1800 0 0 0 0>; @@ -180,7 +180,7 @@ status = "disabled"; }; - pcie@4,0 { + pcie4: pcie@4,0 { device_type = "pci"; assigned-addresses = <0x82000800 0 0x4c000 0 0x2000>; reg = <0x2000 0 0 0 0>; @@ -197,7 +197,7 @@ status = "disabled"; }; - pcie@5,0 { + pcie5: pcie@5,0 { device_type = "pci"; assigned-addresses = <0x82000800 0 0x80000 0 0x2000>; reg = <0x2800 0 0 0 0>; @@ -214,7 +214,7 @@ status = "disabled"; }; - pcie@6,0 { + pcie6: pcie@6,0 { device_type = "pci"; assigned-addresses = <0x82000800 0 0x84000 0 0x2000>; reg = <0x3000 0 0 0 0>; @@ -231,7 +231,7 @@ status = "disabled"; }; - pcie@7,0 { + pcie7: pcie@7,0 { device_type = "pci"; assigned-addresses = <0x82000800 0 0x88000 0 0x2000>; reg = <0x3800 0 0 0 0>; @@ -248,7 +248,7 @@ status = "disabled"; }; - pcie@8,0 { + pcie8: pcie@8,0 { device_type = "pci"; assigned-addresses = <0x82000800 0 0x8c000 0 0x2000>; reg = <0x4000 0 0 0 0>; @@ -265,7 +265,7 @@ status = "disabled"; }; - pcie@9,0 { + pcie9: pcie@9,0 { device_type = "pci"; assigned-addresses = <0x82000800 0 0x42000 0 0x2000>; reg = <0x4800 0 0 0 0>; diff --git a/arch/arm/boot/dts/armada-xp-mv78460.dtsi b/arch/arm/boot/dts/armada-xp-mv78460.dtsi index 0e24f1a38540..775bee53ce86 100644 --- a/arch/arm/boot/dts/armada-xp-mv78460.dtsi +++ b/arch/arm/boot/dts/armada-xp-mv78460.dtsi @@ -104,7 +104,7 @@ * configured as x4 or quad x1 lanes. Two units are * x4/x1. */ - pcie-controller { + pciec: pcie-controller@82000000 { compatible = "marvell,armada-xp-pcie"; status = "disabled"; device_type = "pci"; @@ -150,7 +150,7 @@ 0x82000000 0xa 0 MBUS_ID(0x08, 0xf8) 0 1 0 /* Port 3.0 MEM */ 0x81000000 0xa 0 MBUS_ID(0x08, 0xf0) 0 1 0 /* Port 3.0 IO */>; - pcie@1,0 { + pcie1: pcie@1,0 { device_type = "pci"; assigned-addresses = <0x82000800 0 0x40000 0 0x2000>; reg = <0x0800 0 0 0 0>; @@ -167,7 +167,7 @@ status = "disabled"; }; - pcie@2,0 { + pcie2: pcie@2,0 { device_type = "pci"; assigned-addresses = <0x82001000 0 0x44000 0 0x2000>; reg = <0x1000 0 0 0 0>; @@ -184,7 +184,7 @@ status = "disabled"; }; - pcie@3,0 { + pcie3: pcie@3,0 { device_type = "pci"; assigned-addresses = <0x82001800 0 0x48000 0 0x2000>; reg = <0x1800 0 0 0 0>; @@ -201,7 +201,7 @@ status = "disabled"; }; - pcie@4,0 { + pcie4: pcie@4,0 { device_type = "pci"; assigned-addresses = <0x82002000 0 0x4c000 0 0x2000>; reg = <0x2000 0 0 0 0>; @@ -218,7 +218,7 @@ status = "disabled"; }; - pcie@5,0 { + pcie5: pcie@5,0 { device_type = "pci"; assigned-addresses = <0x82002800 0 0x80000 0 0x2000>; reg = <0x2800 0 0 0 0>; @@ -235,7 +235,7 @@ status = "disabled"; }; - pcie@6,0 { + pcie6: pcie@6,0 { device_type = "pci"; assigned-addresses = <0x82003000 0 0x84000 0 0x2000>; reg = <0x3000 0 0 0 0>; @@ -252,7 +252,7 @@ status = "disabled"; }; - pcie@7,0 { + pcie7: pcie@7,0 { device_type = "pci"; assigned-addresses = <0x82003800 0 0x88000 0 0x2000>; reg = <0x3800 0 0 0 0>; @@ -269,7 +269,7 @@ status = "disabled"; }; - pcie@8,0 { + pcie8: pcie@8,0 { device_type = "pci"; assigned-addresses = <0x82004000 0 0x8c000 0 0x2000>; reg = <0x4000 0 0 0 0>; @@ -286,7 +286,7 @@ status = "disabled"; }; - pcie@9,0 { + pcie9: pcie@9,0 { device_type = "pci"; assigned-addresses = <0x82004800 0 0x42000 0 0x2000>; reg = <0x4800 0 0 0 0>; @@ -303,7 +303,7 @@ status = "disabled"; }; - pcie@10,0 { + pcie10: pcie@10,0 { device_type = "pci"; assigned-addresses = <0x82005000 0 0x82000 0 0x2000>; reg = <0x5000 0 0 0 0>; diff --git a/arch/arm/boot/dts/armada-xp-netgear-rn2120.dts b/arch/arm/boot/dts/armada-xp-netgear-rn2120.dts index d19f44c70925..a2f0e789465d 100644 --- a/arch/arm/boot/dts/armada-xp-netgear-rn2120.dts +++ b/arch/arm/boot/dts/armada-xp-netgear-rn2120.dts @@ -56,7 +56,7 @@ stdout-path = "serial0:115200n8"; }; - memory { + memory@0 { device_type = "memory"; reg = <0 0x00000000 0 0x80000000>; /* 2GB */ }; @@ -67,28 +67,6 @@ MBUS_ID(0x09, 0x09) 0 0 0xf1100000 0x10000 MBUS_ID(0x09, 0x05) 0 0 0xf1110000 0x10000>; - pcie-controller { - status = "okay"; - - /* Connected to first Marvell 88SE9170 SATA controller */ - pcie@1,0 { - /* Port 0, Lane 0 */ - status = "okay"; - }; - - /* Connected to second Marvell 88SE9170 SATA controller */ - pcie@2,0 { - /* Port 0, Lane 1 */ - status = "okay"; - }; - - /* Connected to Fresco Logic FL1009 USB 3.0 controller */ - pcie@5,0 { - /* Port 1, Lane 0 */ - status = "okay"; - }; - }; - internal-regs { /* RTC is provided by Intersil ISL12057 I2C RTC chip */ @@ -97,7 +75,6 @@ }; i2c@11000 { - compatible = "marvell,mv64xxx-i2c"; clock-frequency = <400000>; status = "okay"; @@ -154,23 +131,19 @@ status = "okay"; }; - mdio { - phy0: ethernet-phy@0 { /* Marvell 88E1318 */ - reg = <0>; - }; - - phy1: ethernet-phy@1 { /* Marvell 88E1318 */ - reg = <1>; - }; - }; - ethernet@70000 { + pinctrl-0 = <&ge0_rgmii_pins>; + pinctrl-names = "default"; + status = "okay"; phy = <&phy0>; phy-mode = "rgmii-id"; }; ethernet@74000 { + pinctrl-0 = <&ge1_rgmii_pins>; + pinctrl-names = "default"; + status = "okay"; phy = <&phy1>; phy-mode = "rgmii-id"; @@ -295,6 +268,39 @@ }; }; +&pciec { + status = "okay"; + + /* Connected to first Marvell 88SE9170 SATA controller */ + pcie@1,0 { + /* Port 0, Lane 0 */ + status = "okay"; + }; + + /* Connected to second Marvell 88SE9170 SATA controller */ + pcie@2,0 { + /* Port 0, Lane 1 */ + status = "okay"; + }; + + /* Connected to Fresco Logic FL1009 USB 3.0 controller */ + pcie@5,0 { + /* Port 1, Lane 0 */ + status = "okay"; + }; +}; + +&mdio { + phy0: ethernet-phy@0 { /* Marvell 88E1318 */ + reg = <0>; + }; + + phy1: ethernet-phy@1 { /* Marvell 88E1318 */ + reg = <1>; + }; +}; + + &pinctrl { poweroff: poweroff { marvell,pins = "mpp42"; diff --git a/arch/arm/boot/dts/armada-xp-openblocks-ax3-4.dts b/arch/arm/boot/dts/armada-xp-openblocks-ax3-4.dts index ed3b889d16ce..b577c9fb03a4 100644 --- a/arch/arm/boot/dts/armada-xp-openblocks-ax3-4.dts +++ b/arch/arm/boot/dts/armada-xp-openblocks-ax3-4.dts @@ -57,7 +57,7 @@ stdout-path = "serial0:115200n8"; }; - memory { + memory@0 { device_type = "memory"; reg = <0 0x00000000 0 0x40000000>; /* 1 GB soldered on */ }; @@ -98,15 +98,6 @@ }; }; - pcie-controller { - status = "okay"; - /* Internal mini-PCIe connector */ - pcie@1,0 { - /* Port 0, Lane 0 */ - status = "okay"; - }; - }; - internal-regs { rtc@10300 { /* No crystal connected to the internal RTC */ @@ -148,31 +139,13 @@ #address-cells = <1>; #size-cells = <0>; - button@1 { + init { label = "Init Button"; linux,code = <KEY_POWER>; gpios = <&gpio1 28 GPIO_ACTIVE_HIGH>; }; }; - mdio { - phy0: ethernet-phy@0 { - reg = <0>; - }; - - phy1: ethernet-phy@1 { - reg = <1>; - }; - - phy2: ethernet-phy@2 { - reg = <2>; - }; - - phy3: ethernet-phy@3 { - reg = <3>; - }; - }; - ethernet@70000 { status = "okay"; phy = <&phy0>; @@ -240,6 +213,33 @@ }; }; +&pciec { + status = "okay"; + /* Internal mini-PCIe connector */ + pcie@1,0 { + /* Port 0, Lane 0 */ + status = "okay"; + }; +}; + +&mdio { + phy0: ethernet-phy@0 { + reg = <0>; + }; + + phy1: ethernet-phy@1 { + reg = <1>; + }; + + phy2: ethernet-phy@2 { + reg = <2>; + }; + + phy3: ethernet-phy@3 { + reg = <3>; + }; +}; + &pinctrl { led_pins: led-pins-0 { marvell,pins = "mpp49", "mpp51", "mpp53"; diff --git a/arch/arm/boot/dts/armada-xp-synology-ds414.dts b/arch/arm/boot/dts/armada-xp-synology-ds414.dts index ae286736b90a..e803da03146a 100644 --- a/arch/arm/boot/dts/armada-xp-synology-ds414.dts +++ b/arch/arm/boot/dts/armada-xp-synology-ds414.dts @@ -70,7 +70,7 @@ stdout-path = "serial0:115200n8"; }; - memory { + memory@0 { device_type = "memory"; reg = <0 0x00000000 0 0x40000000>; /* 1GB */ }; @@ -81,28 +81,6 @@ MBUS_ID(0x09, 0x09) 0 0 0xf1100000 0x10000 MBUS_ID(0x09, 0x05) 0 0 0xf1110000 0x10000>; - pcie-controller { - status = "okay"; - - /* - * Connected to Marvell 88SX7042 SATA-II controller - * handling the four disks. - */ - pcie@1,0 { - /* Port 0, Lane 0 */ - status = "okay"; - }; - - /* - * Connected to EtronTech EJ168A XHCI controller - * providing the two rear USB 3.0 ports. - */ - pcie@5,0 { - /* Port 1, Lane 0 */ - status = "okay"; - }; - }; - internal-regs { /* RTC is provided by Seiko S-35390A below */ @@ -150,16 +128,6 @@ status = "okay"; }; - mdio { - phy0: ethernet-phy@0 { /* Marvell 88E1512 */ - reg = <0>; - }; - - phy1: ethernet-phy@1 { /* Marvell 88E1512 */ - reg = <1>; - }; - }; - ethernet@70000 { status = "okay"; pinctrl-0 = <&ge0_rgmii_pins>; @@ -186,7 +154,7 @@ &sata3_pwr_pin &sata4_pwr_pin>; pinctrl-names = "default"; - sata1_regulator: sata1-regulator { + sata1_regulator: sata1-regulator@1 { compatible = "regulator-fixed"; reg = <1>; regulator-name = "SATA1 Power"; @@ -199,7 +167,7 @@ gpio = <&gpio1 10 GPIO_ACTIVE_HIGH>; }; - sata2_regulator: sata2-regulator { + sata2_regulator: sata2-regulator@2 { compatible = "regulator-fixed"; reg = <2>; regulator-name = "SATA2 Power"; @@ -212,7 +180,7 @@ gpio = <&gpio1 12 GPIO_ACTIVE_HIGH>; }; - sata3_regulator: sata3-regulator { + sata3_regulator: sata3-regulator@3 { compatible = "regulator-fixed"; reg = <3>; regulator-name = "SATA3 Power"; @@ -225,7 +193,7 @@ gpio = <&gpio1 13 GPIO_ACTIVE_HIGH>; }; - sata4_regulator: sata4-regulator { + sata4_regulator: sata4-regulator@4 { compatible = "regulator-fixed"; reg = <4>; regulator-name = "SATA4 Power"; @@ -240,6 +208,39 @@ }; }; +&pciec { + status = "okay"; + + /* + * Connected to Marvell 88SX7042 SATA-II controller + * handling the four disks. + */ + pcie@1,0 { + /* Port 0, Lane 0 */ + status = "okay"; + }; + + /* + * Connected to EtronTech EJ168A XHCI controller + * providing the two rear USB 3.0 ports. + */ + pcie@5,0 { + /* Port 1, Lane 0 */ + status = "okay"; + }; +}; + + +&mdio { + phy0: ethernet-phy@0 { /* Marvell 88E1512 */ + reg = <0>; + }; + + phy1: ethernet-phy@1 { /* Marvell 88E1512 */ + reg = <1>; + }; +}; + &pinctrl { sata1_pwr_pin: sata1-pwr-pin { marvell,pins = "mpp42"; diff --git a/arch/arm/boot/dts/armada-xp.dtsi b/arch/arm/boot/dts/armada-xp.dtsi index 4a5f99e65b51..5274e4ff5d62 100644 --- a/arch/arm/boot/dts/armada-xp.dtsi +++ b/arch/arm/boot/dts/armada-xp.dtsi @@ -53,6 +53,9 @@ #include "armada-370-xp.dtsi" / { + #address-cells = <2>; + #size-cells = <2>; + model = "Marvell Armada XP family SoC"; compatible = "marvell,armadaxp", "marvell,armada-370-xp"; @@ -75,7 +78,7 @@ reg = <0x1400 0x500>; }; - L2: l2-cache { + L2: l2-cache@8000 { compatible = "marvell,aurora-system-cache"; reg = <0x08000 0x1000>; cache-id-part = <0x100>; @@ -84,16 +87,6 @@ wt-override; }; - i2c0: i2c@11000 { - compatible = "marvell,mv78230-i2c", "marvell,mv64xxx-i2c"; - reg = <0x11000 0x100>; - }; - - i2c1: i2c@11100 { - compatible = "marvell,mv78230-i2c", "marvell,mv64xxx-i2c"; - reg = <0x11100 0x100>; - }; - uart2: serial@12200 { compatible = "snps,dw-apb-uart"; pinctrl-0 = <&uart2_pins>; @@ -118,7 +111,7 @@ status = "disabled"; }; - system-controller@18200 { + systemc: system-controller@18200 { compatible = "marvell,armada-370-xp-system-controller"; reg = <0x18200 0x500>; }; @@ -136,7 +129,7 @@ #clock-cells = <1>; }; - thermal@182b0 { + thermal: thermal@182b0 { compatible = "marvell,armadaxp-thermal"; reg = <0x182b0 0x4 0x184d0 0x4>; @@ -150,27 +143,6 @@ clocks = <&coreclk 1>; }; - interrupt-controller@20a00 { - reg = <0x20a00 0x2d0>, <0x21070 0x58>; - }; - - timer@20300 { - compatible = "marvell,armada-xp-timer"; - clocks = <&coreclk 2>, <&refclk>; - clock-names = "nbclk", "fixed"; - }; - - watchdog@20300 { - compatible = "marvell,armada-xp-wdt"; - clocks = <&coreclk 2>, <&refclk>; - clock-names = "nbclk", "fixed"; - }; - - cpurst@20800 { - compatible = "marvell,armada-370-cpu-reset"; - reg = <0x20800 0x20>; - }; - cpu-config@21000 { compatible = "marvell,armada-xp-cpu-config"; reg = <0x21000 0x8>; @@ -184,15 +156,7 @@ status = "disabled"; }; - usb@50000 { - clocks = <&gateclk 18>; - }; - - usb@51000 { - clocks = <&gateclk 19>; - }; - - usb@52000 { + usb2: usb@52000 { compatible = "marvell,orion-ehci"; reg = <0x52000 0x500>; interrupts = <47>; @@ -200,7 +164,7 @@ status = "disabled"; }; - xor@60900 { + xor1: xor@60900 { compatible = "marvell,orion-xor"; reg = <0x60900 0x100 0x60b00 0x100>; @@ -228,7 +192,7 @@ compatible = "marvell,armada-xp-neta"; }; - crypto@90000 { + cesa: crypto@90000 { compatible = "marvell,armada-xp-crypto"; reg = <0x90000 0x10000>; reg-names = "regs"; @@ -248,7 +212,7 @@ status = "disabled"; }; - xor@f0900 { + xor0: xor@f0900 { compatible = "marvell,orion-xor"; reg = <0xF0900 0x100 0xF0B00 0x100>; @@ -309,6 +273,44 @@ }; }; +&i2c0 { + compatible = "marvell,mv78230-i2c", "marvell,mv64xxx-i2c"; + reg = <0x11000 0x100>; +}; + +&i2c1 { + compatible = "marvell,mv78230-i2c", "marvell,mv64xxx-i2c"; + reg = <0x11100 0x100>; +}; + +&mpic { + reg = <0x20a00 0x2d0>, <0x21070 0x58>; +}; + +&timer { + compatible = "marvell,armada-xp-timer"; + clocks = <&coreclk 2>, <&refclk>; + clock-names = "nbclk", "fixed"; +}; + +&watchdog { + compatible = "marvell,armada-xp-wdt"; + clocks = <&coreclk 2>, <&refclk>; + clock-names = "nbclk", "fixed"; +}; + +&cpurst { + reg = <0x20800 0x20>; +}; + +&usb0 { + clocks = <&gateclk 18>; +}; + +&usb1 { + clocks = <&gateclk 19>; +}; + &pinctrl { ge0_gmii_pins: ge0-gmii-pins { marvell,pins = diff --git a/arch/arm/boot/dts/artpec6-devboard.dts b/arch/arm/boot/dts/artpec6-devboard.dts index f823ed382ac7..9dfe845694cf 100644 --- a/arch/arm/boot/dts/artpec6-devboard.dts +++ b/arch/arm/boot/dts/artpec6-devboard.dts @@ -46,6 +46,10 @@ status = "okay"; }; +&pcie { + status = "okay"; +}; + ðernet { status = "okay"; diff --git a/arch/arm/boot/dts/artpec6.dtsi b/arch/arm/boot/dts/artpec6.dtsi index 3489019cc0dc..767cbe8d8557 100644 --- a/arch/arm/boot/dts/artpec6.dtsi +++ b/arch/arm/boot/dts/artpec6.dtsi @@ -67,7 +67,7 @@ }; }; - syscon { + syscon: syscon@f8000000 { compatible = "axis,artpec6-syscon", "syscon"; reg = <0xf8000000 0x48>; }; @@ -154,6 +154,33 @@ interrupt-parent = <&intc>; }; + pcie: pcie@f8050000 { + compatible = "axis,artpec6-pcie", "snps,dw-pcie"; + reg = <0xf8050000 0x2000 + 0xf8040000 0x1000 + 0xc0000000 0x2000>; + reg-names = "dbi", "phy", "config"; + #address-cells = <3>; + #size-cells = <2>; + device_type = "pci"; + /* downstream I/O */ + ranges = <0x81000000 0 0 0xc0002000 0 0x00010000 + /* non-prefetchable memory */ + 0x82000000 0 0xc0012000 0xc0012000 0 0x1ffee000>; + num-lanes = <2>; + bus-range = <0x00 0xff>; + interrupts = <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "msi"; + #interrupt-cells = <1>; + interrupt-map-mask = <0 0 0 0x7>; + interrupt-map = <0 0 0 1 &intc GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>, + <0 0 0 2 &intc GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>, + <0 0 0 3 &intc GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>, + <0 0 0 4 &intc GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>; + axis,syscon-pcie = <&syscon>; + status = "disabled"; + }; + amba@0 { compatible = "simple-bus"; #address-cells = <0x1>; diff --git a/arch/arm/boot/dts/at91-sama5d4_ma5d4.dtsi b/arch/arm/boot/dts/at91-sama5d4_ma5d4.dtsi index a92c6e0ca854..b5a5a91bc2ef 100644 --- a/arch/arm/boot/dts/at91-sama5d4_ma5d4.dtsi +++ b/arch/arm/boot/dts/at91-sama5d4_ma5d4.dtsi @@ -12,8 +12,8 @@ #include "sama5d4.dtsi" / { - model = "DENX MA5D4"; - compatible = "denx,ma5d4", "atmel,sama5d4", "atmel,sama5"; + model = "Aries/DENX MA5D4"; + compatible = "aries,ma5d4", "denx,ma5d4", "atmel,sama5d4", "atmel,sama5"; memory { reg = <0x20000000 0x10000000>; diff --git a/arch/arm/boot/dts/at91-sama5d4_ma5d4evk.dts b/arch/arm/boot/dts/at91-sama5d4_ma5d4evk.dts index eac4ea2744cc..84be29f38dae 100644 --- a/arch/arm/boot/dts/at91-sama5d4_ma5d4evk.dts +++ b/arch/arm/boot/dts/at91-sama5d4_ma5d4evk.dts @@ -13,8 +13,8 @@ #include "at91-sama5d4_ma5d4.dtsi" / { - model = "DENX MA5D4EVK"; - compatible = "denx,ma5d4evk", "atmel,sama5d4", "atmel,sama5"; + model = "Aries/DENX MA5D4EVK"; + compatible = "aries,ma5d4evk", "denx,ma5d4evk", "atmel,sama5d4", "atmel,sama5"; chosen { stdout-path = "serial3:115200n8"; diff --git a/arch/arm/boot/dts/at91rm9200.dtsi b/arch/arm/boot/dts/at91rm9200.dtsi index 4e913c2ccb79..f057e0b15a6f 100644 --- a/arch/arm/boot/dts/at91rm9200.dtsi +++ b/arch/arm/boot/dts/at91rm9200.dtsi @@ -481,8 +481,8 @@ dbgu { pinctrl_dbgu: dbgu-0 { atmel,pins = - <AT91_PIOA 30 AT91_PERIPH_A AT91_PINCTRL_NONE /* PA30 periph A */ - AT91_PIOA 31 AT91_PERIPH_A AT91_PINCTRL_PULL_UP>; /* PA31 periph with pullup */ + <AT91_PIOA 30 AT91_PERIPH_A AT91_PINCTRL_PULL_UP + AT91_PIOA 31 AT91_PERIPH_A AT91_PINCTRL_NONE>; }; }; diff --git a/arch/arm/boot/dts/at91sam9260.dtsi b/arch/arm/boot/dts/at91sam9260.dtsi index a3e363d79122..9e035b21e1b6 100644 --- a/arch/arm/boot/dts/at91sam9260.dtsi +++ b/arch/arm/boot/dts/at91sam9260.dtsi @@ -412,8 +412,8 @@ dbgu { pinctrl_dbgu: dbgu-0 { atmel,pins = - <AT91_PIOB 14 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB14 periph A */ - AT91_PIOB 15 AT91_PERIPH_A AT91_PINCTRL_PULL_UP>; /* PB15 periph with pullup */ + <AT91_PIOB 14 AT91_PERIPH_A AT91_PINCTRL_PULL_UP + AT91_PIOB 15 AT91_PERIPH_A AT91_PINCTRL_NONE>; }; }; diff --git a/arch/arm/boot/dts/at91sam9260ek.dts b/arch/arm/boot/dts/at91sam9260ek.dts index 2c87f58448e7..b2578feceb08 100644 --- a/arch/arm/boot/dts/at91sam9260ek.dts +++ b/arch/arm/boot/dts/at91sam9260ek.dts @@ -174,14 +174,14 @@ label = "Button 3"; gpios = <&pioA 30 GPIO_ACTIVE_LOW>; linux,code = <0x103>; - gpio-key,wakeup; + wakeup-source; }; btn4 { label = "Button 4"; gpios = <&pioA 31 GPIO_ACTIVE_LOW>; linux,code = <0x104>; - gpio-key,wakeup; + wakeup-source; }; }; diff --git a/arch/arm/boot/dts/at91sam9261.dtsi b/arch/arm/boot/dts/at91sam9261.dtsi index 32752d7883f1..3fe77c38bd0d 100644 --- a/arch/arm/boot/dts/at91sam9261.dtsi +++ b/arch/arm/boot/dts/at91sam9261.dtsi @@ -302,8 +302,8 @@ dbgu { pinctrl_dbgu: dbgu-0 { atmel,pins = - <AT91_PIOA 9 AT91_PERIPH_A AT91_PINCTRL_NONE>, - <AT91_PIOA 10 AT91_PERIPH_A AT91_PINCTRL_PULL_UP>; + <AT91_PIOA 9 AT91_PERIPH_A AT91_PINCTRL_PULL_UP>, + <AT91_PIOA 10 AT91_PERIPH_A AT91_PINCTRL_NONE>; }; }; diff --git a/arch/arm/boot/dts/at91sam9263.dtsi b/arch/arm/boot/dts/at91sam9263.dtsi index aeb1a36373f4..a1888f6d892b 100644 --- a/arch/arm/boot/dts/at91sam9263.dtsi +++ b/arch/arm/boot/dts/at91sam9263.dtsi @@ -412,8 +412,8 @@ dbgu { pinctrl_dbgu: dbgu-0 { atmel,pins = - <AT91_PIOC 30 AT91_PERIPH_A AT91_PINCTRL_NONE /* PC30 periph A */ - AT91_PIOC 31 AT91_PERIPH_A AT91_PINCTRL_PULL_UP>; /* PC31 periph with pullup */ + <AT91_PIOC 30 AT91_PERIPH_A AT91_PINCTRL_PULL_UP + AT91_PIOC 31 AT91_PERIPH_A AT91_PINCTRL_NONE>; }; }; diff --git a/arch/arm/boot/dts/at91sam9g45.dtsi b/arch/arm/boot/dts/at91sam9g45.dtsi index b3501ae2a3bd..e567d5fd3f9d 100644 --- a/arch/arm/boot/dts/at91sam9g45.dtsi +++ b/arch/arm/boot/dts/at91sam9g45.dtsi @@ -478,8 +478,8 @@ dbgu { pinctrl_dbgu: dbgu-0 { atmel,pins = - <AT91_PIOB 12 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB12 periph A */ - AT91_PIOB 13 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PB13 periph A */ + <AT91_PIOB 12 AT91_PERIPH_A AT91_PINCTRL_PULL_UP + AT91_PIOB 13 AT91_PERIPH_A AT91_PINCTRL_NONE>; }; }; diff --git a/arch/arm/boot/dts/at91sam9n12.dtsi b/arch/arm/boot/dts/at91sam9n12.dtsi index 3b3eb3edcb47..f43d7695352d 100644 --- a/arch/arm/boot/dts/at91sam9n12.dtsi +++ b/arch/arm/boot/dts/at91sam9n12.dtsi @@ -500,8 +500,8 @@ dbgu { pinctrl_dbgu: dbgu-0 { atmel,pins = - <AT91_PIOA 9 AT91_PERIPH_A AT91_PINCTRL_NONE /* PA9 periph A */ - AT91_PIOA 10 AT91_PERIPH_A AT91_PINCTRL_PULL_UP>; /* PA10 periph with pullup */ + <AT91_PIOA 9 AT91_PERIPH_A AT91_PINCTRL_PULL_UP + AT91_PIOA 10 AT91_PERIPH_A AT91_PINCTRL_NONE>; }; }; diff --git a/arch/arm/boot/dts/at91sam9rl.dtsi b/arch/arm/boot/dts/at91sam9rl.dtsi index 70adf940d98c..f4c129a98f17 100644 --- a/arch/arm/boot/dts/at91sam9rl.dtsi +++ b/arch/arm/boot/dts/at91sam9rl.dtsi @@ -438,8 +438,8 @@ dbgu { pinctrl_dbgu: dbgu-0 { atmel,pins = - <AT91_PIOA 21 AT91_PERIPH_A AT91_PINCTRL_NONE>, - <AT91_PIOA 22 AT91_PERIPH_A AT91_PINCTRL_PULL_UP>; + <AT91_PIOA 21 AT91_PERIPH_A AT91_PINCTRL_PULL_UP>, + <AT91_PIOA 22 AT91_PERIPH_A AT91_PINCTRL_NONE>; }; }; diff --git a/arch/arm/boot/dts/at91sam9x5.dtsi b/arch/arm/boot/dts/at91sam9x5.dtsi index ed4e4bd8a8f1..f66bae925705 100644 --- a/arch/arm/boot/dts/at91sam9x5.dtsi +++ b/arch/arm/boot/dts/at91sam9x5.dtsi @@ -460,8 +460,8 @@ dbgu { pinctrl_dbgu: dbgu-0 { atmel,pins = - <AT91_PIOA 9 AT91_PERIPH_A AT91_PINCTRL_NONE /* PA9 periph A */ - AT91_PIOA 10 AT91_PERIPH_A AT91_PINCTRL_PULL_UP>; /* PA10 periph A with pullup */ + <AT91_PIOA 9 AT91_PERIPH_A AT91_PINCTRL_PULL_UP + AT91_PIOA 10 AT91_PERIPH_A AT91_PINCTRL_NONE>; }; }; diff --git a/arch/arm/boot/dts/cloudengines-pogoplug-series-3.dts b/arch/arm/boot/dts/cloudengines-pogoplug-series-3.dts new file mode 100644 index 000000000000..bfde32e37123 --- /dev/null +++ b/arch/arm/boot/dts/cloudengines-pogoplug-series-3.dts @@ -0,0 +1,94 @@ +/* + * cloudengines-pogoplug-series-3.dtsi - Device tree file for Cloud Engines PogoPlug Series 3 + * + * Copyright (C) 2016 Neil Armstrong <narmstrong@baylibre.com> + * + * Licensed under GPLv2 or later + */ + +/dts-v1/; +#include "ox820.dtsi" + +/ { + model = "Cloud Engines PogoPlug Series 3"; + + compatible = "cloudengines,pogoplugv3", "oxsemi,ox820"; + + chosen { + bootargs = "earlyprintk"; + stdout-path = "serial0:115200n8"; + }; + + memory { + /* 128Mbytes DDR */ + reg = <0x60000000 0x8000000>; + }; + + aliases { + serial0 = &uart0; + gpio0 = &gpio0; + gpio1 = &gpio1; + }; + + leds { + compatible = "gpio-leds"; + + blue { + label = "pogoplug:blue"; + gpios = <&gpio0 2 0>; + default-state = "keep"; + }; + + orange { + label = "pogoplug:orange"; + gpios = <&gpio1 16 1>; + default-state = "keep"; + }; + + green { + label = "pogoplug:green"; + gpios = <&gpio1 17 1>; + default-state = "keep"; + }; + }; +}; + +&uart0 { + status = "okay"; + + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart0>; +}; + +&nandc { + status = "okay"; + + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_nand>; + + nand@0 { + reg = <0>; + #address-cells = <1>; + #size-cells = <1>; + nand-ecc-mode = "soft"; + nand-ecc-algo = "hamming"; + + partition@0 { + label = "boot"; + reg = <0x00000000 0x00e00000>; + read-only; + }; + + partition@e00000 { + label = "ubi"; + reg = <0x00e00000 0x07200000>; + }; + }; +}; + +ða { + status = "okay"; + + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_etha_mdio>; +}; diff --git a/arch/arm/boot/dts/da850.dtsi b/arch/arm/boot/dts/da850.dtsi index ffc6e1abd1b7..4070619d823b 100644 --- a/arch/arm/boot/dts/da850.dtsi +++ b/arch/arm/boot/dts/da850.dtsi @@ -36,6 +36,7 @@ reg = <0x14120 0x50>; #address-cells = <1>; #size-cells = <0>; + #pinctrl-cells = <2>; pinctrl-single,bit-per-mux; pinctrl-single,register-width = <32>; pinctrl-single,function-mask = <0xf>; diff --git a/arch/arm/boot/dts/dm814x.dtsi b/arch/arm/boot/dts/dm814x.dtsi index ff90a6ce6bdc..1facc5f12cef 100644 --- a/arch/arm/boot/dts/dm814x.dtsi +++ b/arch/arm/boot/dts/dm814x.dtsi @@ -373,6 +373,7 @@ reg = <0x800 0x438>; #address-cells = <1>; #size-cells = <0>; + #pinctrl-cells = <1>; pinctrl-single,register-width = <32>; pinctrl-single,function-mask = <0x307ff>; }; diff --git a/arch/arm/boot/dts/dm816x.dtsi b/arch/arm/boot/dts/dm816x.dtsi index f1e0f771ff29..61dd2f6b02bc 100644 --- a/arch/arm/boot/dts/dm816x.dtsi +++ b/arch/arm/boot/dts/dm816x.dtsi @@ -83,6 +83,7 @@ reg = <0x48140000 0x21000>; #address-cells = <1>; #size-cells = <1>; + #pinctrl-cells = <1>; ranges = <0 0x48140000 0x21000>; dm816x_pinmux: pinmux@800 { @@ -90,6 +91,7 @@ reg = <0x800 0x50a>; #address-cells = <1>; #size-cells = <0>; + #pinctrl-cells = <1>; pinctrl-single,register-width = <16>; pinctrl-single,function-mask = <0xf>; }; diff --git a/arch/arm/boot/dts/dra7.dtsi b/arch/arm/boot/dts/dra7.dtsi index d4fcd68f6349..addb7530cfbe 100644 --- a/arch/arm/boot/dts/dra7.dtsi +++ b/arch/arm/boot/dts/dra7.dtsi @@ -171,6 +171,7 @@ reg = <0x1400 0x0468>; #address-cells = <1>; #size-cells = <0>; + #pinctrl-cells = <1>; #interrupt-cells = <1>; interrupt-controller; pinctrl-single,register-width = <32>; diff --git a/arch/arm/boot/dts/dra71-evm.dts b/arch/arm/boot/dts/dra71-evm.dts new file mode 100644 index 000000000000..2b9a5a8d69ad --- /dev/null +++ b/arch/arm/boot/dts/dra71-evm.dts @@ -0,0 +1,230 @@ +/* + * Copyright (C) 2016 Texas Instruments Incorporated - http://www.ti.com/ + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#include "dra72-evm-common.dtsi" +#include <dt-bindings/net/ti-dp83867.h> + +/ { + compatible = "ti,dra718-evm", "ti,dra718", "ti,dra722", "ti,dra72", "ti,dra7"; + model = "TI DRA718 EVM"; + + memory { + device_type = "memory"; + reg = <0x0 0x80000000 0x0 0x80000000>; /* 2GB */ + }; + + vpo_sd_1v8_3v3: gpio-regulator-TPS74801 { + compatible = "regulator-gpio"; + + regulator-name = "vddshv8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3000000>; + regulator-boot-on; + vin-supply = <&evm_5v0>; + + gpios = <&gpio7 11 GPIO_ACTIVE_HIGH>; + states = <1800000 0x0 + 3000000 0x1>; + }; + + poweroff: gpio-poweroff { + compatible = "gpio-poweroff"; + gpios = <&gpio7 30 GPIO_ACTIVE_HIGH>; + input; + }; +}; + +&i2c1 { + status = "okay"; + clock-frequency = <400000>; + + lp8733: lp8733@60 { + compatible = "ti,lp8733"; + reg = <0x60>; + + buck0-in-supply =<&vsys_3v3>; + buck1-in-supply =<&vsys_3v3>; + ldo0-in-supply =<&evm_5v0>; + ldo1-in-supply =<&evm_5v0>; + + lp8733_regulators: regulators { + lp8733_buck0_reg: buck0 { + /* FB_B0 -> LP8733-BUCK1 - VPO_S1_AVS - VDD_CORE_AVS (core, mpu, gpu) */ + regulator-name = "lp8733-buck0"; + regulator-min-microvolt = <850000>; + regulator-max-microvolt = <1250000>; + regulator-always-on; + regulator-boot-on; + }; + + lp8733_buck1_reg: buck1 { + /* FB_B1 -> LP8733-BUCK2 - VPO_S2_AVS - VDD_DSP_AVS (DSP/eve/iva) */ + regulator-name = "lp8733-buck1"; + regulator-min-microvolt = <850000>; + regulator-max-microvolt = <1250000>; + regulator-boot-on; + regulator-always-on; + }; + + lp8733_ldo0_reg: ldo0 { + /* LDO0 -> LP8733-LDO1 - VPO_L1_3V3 - VDDSHV8 (optional) */ + regulator-name = "lp8733-ldo0"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + }; + + lp8733_ldo1_reg: ldo1 { + /* LDO1 -> LP8733-LDO2 - VPO_L2_3V3 - VDDA_USB3V3 */ + regulator-name = "lp8733-ldo1"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + regulator-boot-on; + }; + }; + }; + + lp8732: lp8732@61 { + compatible = "ti,lp8732"; + reg = <0x61>; + + buck0-in-supply =<&vsys_3v3>; + buck1-in-supply =<&vsys_3v3>; + ldo0-in-supply =<&vsys_3v3>; + ldo1-in-supply =<&vsys_3v3>; + + lp8732_regulators: regulators { + lp8732_buck0_reg: buck0 { + /* FB_B0 -> LP8732-BUCK1 - VPO_S3_1V8 - VDDS_1V8 */ + regulator-name = "lp8732-buck0"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + regulator-boot-on; + }; + + lp8732_buck1_reg: buck1 { + /* FB_B1 -> LP8732-BUCK2 - VPO_S4_DDR - VDD_DDR_1V35 */ + regulator-name = "lp8732-buck1"; + regulator-min-microvolt = <1350000>; + regulator-max-microvolt = <1350000>; + regulator-boot-on; + regulator-always-on; + }; + + lp8732_ldo0_reg: ldo0 { + /* LDO0 -> LP8732-LDO1 - VPO_L3_1V8 - VDA_1V8_PLL */ + regulator-name = "lp8732-ldo0"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-boot-on; + regulator-always-on; + }; + + lp8732_ldo1_reg: ldo1 { + /* LDO1 -> LP8732-LDO2 - VPO_L4_1V8 - VDA_1V8_PHY */ + regulator-name = "lp8732-ldo1"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + regulator-boot-on; + }; + }; + }; +}; + +&pcf_gpio_21 { + interrupt-parent = <&gpio7>; + interrupts = <31 IRQ_TYPE_EDGE_FALLING>; +}; + +&pcf_hdmi { + p0 { + /* + * PM_OEn to High: Disable routing I2C3 to PM_I2C + * With this PM_SEL(p3) should not matter + */ + gpio-hog; + gpios = <0 GPIO_ACTIVE_LOW>; + output-high; + line-name = "pm_oe_n"; + }; +}; + +&mmc1 { + vmmc_aux-supply = <&vpo_sd_1v8_3v3>; +}; + +&mac { + mode-gpios = <&pcf_gpio_21 4 GPIO_ACTIVE_LOW>, + <&pcf_hdmi 9 GPIO_ACTIVE_LOW>, /* P11 */ + <&pcf_hdmi 10 GPIO_ACTIVE_LOW>; /* P12 */ + dual_emac; +}; + +&cpsw_emac0 { + phy_id = <&davinci_mdio>, <2>; + phy-mode = "rgmii-id"; + dual_emac_res_vlan = <1>; +}; + +&cpsw_emac1 { + phy_id = <&davinci_mdio>, <3>; + phy-mode = "rgmii-id"; + dual_emac_res_vlan = <2>; +}; + +&davinci_mdio { + dp83867_0: ethernet-phy@2 { + reg = <2>; + ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_25_NS>; + ti,tx-internal-delay = <DP83867_RGMIIDCTL_250_PS>; + ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_8_B_NIB>; + ti,impedance-control = <0x1f>; + }; + + dp83867_1: ethernet-phy@3 { + reg = <3>; + ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_25_NS>; + ti,tx-internal-delay = <DP83867_RGMIIDCTL_250_PS>; + ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_8_B_NIB>; + ti,impedance-control = <0x1f>; + }; +}; + +/* No Sata on this device */ +&sata_phy { + status = "disabled"; +}; + +&sata { + status = "disabled"; +}; + +/* No RTC on this device */ +&rtc { + status = "disabled"; +}; + +&usb2_phy1 { + phy-supply = <&lp8733_ldo1_reg>; +}; + +&usb2_phy2 { + phy-supply = <&lp8733_ldo1_reg>; +}; + +&dss { + /* Supplied by VDA_1V8_PLL */ + vdda_video-supply = <&lp8732_ldo0_reg>; +}; + +&hdmi { + /* Supplied by VDA_1V8_PHY */ + vdda_video-supply = <&lp8732_ldo1_reg>; +}; diff --git a/arch/arm/boot/dts/dra72-evm-common.dtsi b/arch/arm/boot/dts/dra72-evm-common.dtsi index c94d8d64710d..e50fbeea96e0 100644 --- a/arch/arm/boot/dts/dra72-evm-common.dtsi +++ b/arch/arm/boot/dts/dra72-evm-common.dtsi @@ -18,11 +18,49 @@ display0 = &hdmi0; }; + evm_12v0: fixedregulator-evm12v0 { + /* main supply */ + compatible = "regulator-fixed"; + regulator-name = "evm_12v0"; + regulator-min-microvolt = <12000000>; + regulator-max-microvolt = <12000000>; + regulator-always-on; + regulator-boot-on; + }; + + evm_5v0: fixedregulator-evm5v0 { + /* Output 1 of TPS43351QDAPRQ1 on dra72-evm */ + /* Output 1 of LM5140QRWGTQ1 on dra71-evm */ + compatible = "regulator-fixed"; + regulator-name = "evm_5v0"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + vin-supply = <&evm_12v0>; + regulator-always-on; + regulator-boot-on; + }; + + vsys_3v3: fixedregulator-vsys3v3 { + /* Output 2 of TPS43351QDAPRQ1 on dra72-evm */ + /* Output 2 of LM5140QRWGTQ1 on dra71-evm */ + compatible = "regulator-fixed"; + regulator-name = "vsys_3v3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + vin-supply = <&evm_12v0>; + regulator-always-on; + regulator-boot-on; + }; + evm_3v3_sw: fixedregulator-evm_3v3 { + /* TPS22965DSG */ compatible = "regulator-fixed"; regulator-name = "evm_3v3"; regulator-min-microvolt = <3300000>; regulator-max-microvolt = <3300000>; + vin-supply = <&vsys_3v3>; + regulator-always-on; + regulator-boot-on; }; aic_dvdd: fixedregulator-aic_dvdd { @@ -39,6 +77,7 @@ regulator-name = "evm_3v3_sd"; regulator-min-microvolt = <3300000>; regulator-max-microvolt = <3300000>; + vin-supply = <&evm_3v3_sw>; enable-active-high; gpio = <&pcf_gpio_21 5 GPIO_ACTIVE_HIGH>; }; @@ -69,9 +108,6 @@ tpd12s015: encoder { compatible = "ti,tpd12s015"; - pinctrl-names = "default"; - pinctrl-0 = <&tpd12s015_pins>; - gpios = <&pcf_hdmi 4 GPIO_ACTIVE_HIGH>, /* P4, CT CP HPD */ <&pcf_hdmi 5 GPIO_ACTIVE_HIGH>, /* P5, LS OE */ <&gpio7 12 GPIO_ACTIVE_HIGH>; /* gpio7_12/sp1_cs2, HPD */ @@ -134,72 +170,6 @@ }; &dra7_pmx_core { - i2c1_pins: pinmux_i2c1_pins { - pinctrl-single,pins = < - DRA7XX_CORE_IOPAD(0x3800, PIN_INPUT | MUX_MODE0) /* i2c1_sda.i2c1_sda */ - DRA7XX_CORE_IOPAD(0x3804, PIN_INPUT | MUX_MODE0) /* i2c1_scl.i2c1_scl */ - >; - }; - - i2c5_pins: pinmux_i2c5_pins { - pinctrl-single,pins = < - DRA7XX_CORE_IOPAD(0x36b4, PIN_INPUT | MUX_MODE10) /* mcasp1_axr0.i2c5_sda */ - DRA7XX_CORE_IOPAD(0x36b8, PIN_INPUT | MUX_MODE10) /* mcasp1_axr1.i2c5_scl */ - >; - }; - - i2c5_pins: pinmux_i2c5_pins { - pinctrl-single,pins = < - DRA7XX_CORE_IOPAD(0x36b4, PIN_INPUT | MUX_MODE10) /* mcasp1_axr0.i2c5_sda */ - DRA7XX_CORE_IOPAD(0x36b8, PIN_INPUT | MUX_MODE10) /* mcasp1_axr1.i2c5_scl */ - >; - }; - - nand_default: nand_default { - pinctrl-single,pins = < - DRA7XX_CORE_IOPAD(0x3400, PIN_INPUT | MUX_MODE0) /* gpmc_ad0 */ - DRA7XX_CORE_IOPAD(0x3404, PIN_INPUT | MUX_MODE0) /* gpmc_ad1 */ - DRA7XX_CORE_IOPAD(0x3408, PIN_INPUT | MUX_MODE0) /* gpmc_ad2 */ - DRA7XX_CORE_IOPAD(0x340c, PIN_INPUT | MUX_MODE0) /* gpmc_ad3 */ - DRA7XX_CORE_IOPAD(0x3410, PIN_INPUT | MUX_MODE0) /* gpmc_ad4 */ - DRA7XX_CORE_IOPAD(0x3414, PIN_INPUT | MUX_MODE0) /* gpmc_ad5 */ - DRA7XX_CORE_IOPAD(0x3418, PIN_INPUT | MUX_MODE0) /* gpmc_ad6 */ - DRA7XX_CORE_IOPAD(0x341c, PIN_INPUT | MUX_MODE0) /* gpmc_ad7 */ - DRA7XX_CORE_IOPAD(0x3420, PIN_INPUT | MUX_MODE0) /* gpmc_ad8 */ - DRA7XX_CORE_IOPAD(0x3424, PIN_INPUT | MUX_MODE0) /* gpmc_ad9 */ - DRA7XX_CORE_IOPAD(0x3428, PIN_INPUT | MUX_MODE0) /* gpmc_ad10 */ - DRA7XX_CORE_IOPAD(0x342c, PIN_INPUT | MUX_MODE0) /* gpmc_ad11 */ - DRA7XX_CORE_IOPAD(0x3430, PIN_INPUT | MUX_MODE0) /* gpmc_ad12 */ - DRA7XX_CORE_IOPAD(0x3434, PIN_INPUT | MUX_MODE0) /* gpmc_ad13 */ - DRA7XX_CORE_IOPAD(0x3438, PIN_INPUT | MUX_MODE0) /* gpmc_ad14 */ - DRA7XX_CORE_IOPAD(0x343c, PIN_INPUT | MUX_MODE0) /* gpmc_ad15 */ - DRA7XX_CORE_IOPAD(0x34b4, PIN_OUTPUT | MUX_MODE0) /* gpmc_cs0 */ - DRA7XX_CORE_IOPAD(0x34c4, PIN_OUTPUT | MUX_MODE0) /* gpmc_advn_ale */ - DRA7XX_CORE_IOPAD(0x34cc, PIN_OUTPUT | MUX_MODE0) /* gpmc_wen */ - DRA7XX_CORE_IOPAD(0x34c8, PIN_OUTPUT | MUX_MODE0) /* gpmc_oen_ren */ - DRA7XX_CORE_IOPAD(0x34d0, PIN_OUTPUT | MUX_MODE0) /* gpmc_ben0 */ - DRA7XX_CORE_IOPAD(0x34d8, PIN_INPUT | MUX_MODE0) /* gpmc_wait0 */ - >; - }; - - usb1_pins: pinmux_usb1_pins { - pinctrl-single,pins = < - DRA7XX_CORE_IOPAD(0x3680, PIN_INPUT_SLEW | MUX_MODE0) /* usb1_drvvbus */ - >; - }; - - usb2_pins: pinmux_usb2_pins { - pinctrl-single,pins = < - DRA7XX_CORE_IOPAD(0x3684, PIN_INPUT_SLEW | MUX_MODE0) /* usb2_drvvbus */ - >; - }; - - tps65917_pins_default: tps65917_pins_default { - pinctrl-single,pins = < - DRA7XX_CORE_IOPAD(0x3824, PIN_INPUT_PULLUP | MUX_MODE1) /* wakeup3.sys_nirq1 */ - >; - }; - mmc1_pins_default: mmc1_pins_default { pinctrl-single,pins = < DRA7XX_CORE_IOPAD(0x376c, PIN_INPUT | MUX_MODE14) /* mmc1sdcd.gpio219 */ @@ -240,161 +210,12 @@ DRA7XX_CORE_IOPAD(0x3818, MUX_MODE15 | PULL_UP) /* wakeup0.off */ >; }; - - hdmi_pins: pinmux_hdmi_pins { - pinctrl-single,pins = < - DRA7XX_CORE_IOPAD(0x3808, PIN_INPUT | MUX_MODE1) /* i2c2_sda.hdmi1_ddc_scl */ - DRA7XX_CORE_IOPAD(0x380c, PIN_INPUT | MUX_MODE1) /* i2c2_scl.hdmi1_ddc_sda */ - >; - }; - - tpd12s015_pins: pinmux_tpd12s015_pins { - pinctrl-single,pins = < - DRA7XX_CORE_IOPAD(0x37b8, PIN_INPUT_PULLDOWN | MUX_MODE14) /* gpio7_12 HPD */ - >; - }; - - atl_pins: pinmux_atl_pins { - pinctrl-single,pins = < - DRA7XX_CORE_IOPAD(0x3698, PIN_OUTPUT | MUX_MODE5) /* xref_clk1.atl_clk1 */ - DRA7XX_CORE_IOPAD(0x369c, PIN_OUTPUT | MUX_MODE5) /* xref_clk2.atl_clk2 */ - >; - }; - - mcasp3_pins: pinmux_mcasp3_pins { - pinctrl-single,pins = < - DRA7XX_CORE_IOPAD(0x3724, PIN_OUTPUT_PULLDOWN | MUX_MODE0) /* mcasp3_aclkx */ - DRA7XX_CORE_IOPAD(0x3728, PIN_OUTPUT_PULLDOWN | MUX_MODE0) /* mcasp3_fsx */ - DRA7XX_CORE_IOPAD(0x372c, PIN_OUTPUT_PULLDOWN | MUX_MODE0) /* mcasp3_axr0 */ - DRA7XX_CORE_IOPAD(0x3730, PIN_INPUT_PULLDOWN | MUX_MODE0) /* mcasp3_axr1 */ - >; - }; - - mcasp3_sleep_pins: pinmux_mcasp3_sleep_pins { - pinctrl-single,pins = < - DRA7XX_CORE_IOPAD(0x3724, PIN_INPUT_PULLDOWN | MUX_MODE15) - DRA7XX_CORE_IOPAD(0x3728, PIN_INPUT_PULLDOWN | MUX_MODE15) - DRA7XX_CORE_IOPAD(0x372c, PIN_INPUT_PULLDOWN | MUX_MODE15) - DRA7XX_CORE_IOPAD(0x3730, PIN_INPUT_PULLDOWN | MUX_MODE15) - >; - }; }; &i2c1 { status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&i2c1_pins>; clock-frequency = <400000>; - tps65917: tps65917@58 { - compatible = "ti,tps65917"; - reg = <0x58>; - - pinctrl-names = "default"; - pinctrl-0 = <&tps65917_pins_default>; - - interrupts = <GIC_SPI 2 IRQ_TYPE_NONE>; /* IRQ_SYS_1N */ - interrupt-controller; - #interrupt-cells = <2>; - - ti,system-power-controller; - - tps65917_pmic { - compatible = "ti,tps65917-pmic"; - - tps65917_regulators: regulators { - smps1_reg: smps1 { - /* VDD_MPU */ - regulator-name = "smps1"; - regulator-min-microvolt = <850000>; - regulator-max-microvolt = <1250000>; - regulator-always-on; - regulator-boot-on; - }; - - smps2_reg: smps2 { - /* VDD_CORE */ - regulator-name = "smps2"; - regulator-min-microvolt = <850000>; - regulator-max-microvolt = <1150000>; - regulator-boot-on; - regulator-always-on; - }; - - smps3_reg: smps3 { - /* VDD_GPU IVA DSPEVE */ - regulator-name = "smps3"; - regulator-min-microvolt = <850000>; - regulator-max-microvolt = <1250000>; - regulator-boot-on; - regulator-always-on; - }; - - smps4_reg: smps4 { - /* VDDS1V8 */ - regulator-name = "smps4"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-always-on; - regulator-boot-on; - }; - - smps5_reg: smps5 { - /* VDD_DDR */ - regulator-name = "smps5"; - regulator-min-microvolt = <1350000>; - regulator-max-microvolt = <1350000>; - regulator-boot-on; - regulator-always-on; - }; - - ldo1_reg: ldo1 { - /* LDO1_OUT --> SDIO */ - regulator-name = "ldo1"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - regulator-boot-on; - regulator-allow-bypass; - }; - - ldo3_reg: ldo3 { - /* VDDA_1V8_PHY */ - regulator-name = "ldo3"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-boot-on; - regulator-always-on; - }; - - ldo5_reg: ldo5 { - /* VDDA_1V8_PLL */ - regulator-name = "ldo5"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-always-on; - regulator-boot-on; - }; - - ldo4_reg: ldo4 { - /* VDDA_3V_USB: VDDA_USBHS33 */ - regulator-name = "ldo4"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-boot-on; - }; - }; - }; - - tps65917_power_button { - compatible = "ti,palmas-pwrbutton"; - interrupt-parent = <&tps65917>; - interrupts = <1 IRQ_TYPE_NONE>; - wakeup-source; - ti,palmas-long-press-seconds = <6>; - }; - }; - pcf_gpio_21: gpio@21 { compatible = "ti,pcf8575", "nxp,pcf8575"; reg = <0x21>; @@ -423,8 +244,6 @@ &i2c5 { status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&i2c5_pins>; clock-frequency = <400000>; pcf_hdmi: pcf8575@26 { @@ -462,8 +281,6 @@ &gpmc { status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&nand_default>; ranges = <0 0 0x08000000 0x01000000>; /* minimum GPMC partition = 16MB */ nand@0,0 { /* To use NAND, DIP switch SW5 must be set like so: @@ -548,14 +365,6 @@ }; }; -&usb2_phy1 { - phy-supply = <&ldo4_reg>; -}; - -&usb2_phy2 { - phy-supply = <&ldo4_reg>; -}; - &omap_dwc3_1 { extcon = <&extcon_usb1>; }; @@ -566,14 +375,10 @@ &usb1 { dr_mode = "peripheral"; - pinctrl-names = "default"; - pinctrl-0 = <&usb1_pins>; }; &usb2 { dr_mode = "host"; - pinctrl-names = "default"; - pinctrl-0 = <&usb2_pins>; }; &mmc1 { @@ -581,7 +386,6 @@ pinctrl-names = "default"; pinctrl-0 = <&mmc1_pins_default>; vmmc-supply = <&evm_3v3_sd>; - vmmc_aux-supply = <&ldo1_reg>; bus-width = <4>; /* * SDCD signal is not being used here - using the fact that GPIO mode @@ -603,71 +407,8 @@ max-frequency = <192000000>; }; -&dra7_pmx_core { - cpsw_default: cpsw_default { - pinctrl-single,pins = < - /* Slave 2 */ - DRA7XX_CORE_IOPAD(0x3598, PIN_OUTPUT | MUX_MODE3) /* vin2a_d12.rgmii1_txc */ - DRA7XX_CORE_IOPAD(0x359c, PIN_OUTPUT | MUX_MODE3) /* vin2a_d13.rgmii1_tctl */ - DRA7XX_CORE_IOPAD(0x35a0, PIN_OUTPUT | MUX_MODE3) /* vin2a_d14.rgmii1_td3 */ - DRA7XX_CORE_IOPAD(0x35a4, PIN_OUTPUT | MUX_MODE3) /* vin2a_d15.rgmii1_td2 */ - DRA7XX_CORE_IOPAD(0x35a8, PIN_OUTPUT | MUX_MODE3) /* vin2a_d16.rgmii1_td1 */ - DRA7XX_CORE_IOPAD(0x35ac, PIN_OUTPUT | MUX_MODE3) /* vin2a_d17.rgmii1_td0 */ - DRA7XX_CORE_IOPAD(0x35b0, PIN_INPUT | MUX_MODE3) /* vin2a_d18.rgmii1_rclk */ - DRA7XX_CORE_IOPAD(0x35b4, PIN_INPUT | MUX_MODE3) /* vin2a_d19.rgmii1_rctl */ - DRA7XX_CORE_IOPAD(0x35b8, PIN_INPUT | MUX_MODE3) /* vin2a_d20.rgmii1_rd3 */ - DRA7XX_CORE_IOPAD(0x35bc, PIN_INPUT | MUX_MODE3) /* vin2a_d21.rgmii1_rd2 */ - DRA7XX_CORE_IOPAD(0x35c0, PIN_INPUT | MUX_MODE3) /* vin2a_d22.rgmii1_rd1 */ - DRA7XX_CORE_IOPAD(0x35c4, PIN_INPUT | MUX_MODE3) /* vin2a_d23.rgmii1_rd0 */ - >; - - }; - - cpsw_sleep: cpsw_sleep { - pinctrl-single,pins = < - /* Slave 2 */ - DRA7XX_CORE_IOPAD(0x3598, MUX_MODE15) - DRA7XX_CORE_IOPAD(0x359c, MUX_MODE15) - DRA7XX_CORE_IOPAD(0x35a0, MUX_MODE15) - DRA7XX_CORE_IOPAD(0x35a4, MUX_MODE15) - DRA7XX_CORE_IOPAD(0x35a8, MUX_MODE15) - DRA7XX_CORE_IOPAD(0x35ac, MUX_MODE15) - DRA7XX_CORE_IOPAD(0x35b0, MUX_MODE15) - DRA7XX_CORE_IOPAD(0x35b4, MUX_MODE15) - DRA7XX_CORE_IOPAD(0x35b8, MUX_MODE15) - DRA7XX_CORE_IOPAD(0x35bc, MUX_MODE15) - DRA7XX_CORE_IOPAD(0x35c0, MUX_MODE15) - DRA7XX_CORE_IOPAD(0x35c4, MUX_MODE15) - >; - }; - - davinci_mdio_default: davinci_mdio_default { - pinctrl-single,pins = < - /* MDIO */ - DRA7XX_CORE_IOPAD(0x363c, PIN_OUTPUT_PULLUP | MUX_MODE0) /* mdio_d.mdio_d */ - DRA7XX_CORE_IOPAD(0x3640, PIN_INPUT_PULLUP | MUX_MODE0) /* mdio_clk.mdio_clk */ - >; - }; - - davinci_mdio_sleep: davinci_mdio_sleep { - pinctrl-single,pins = < - DRA7XX_CORE_IOPAD(0x363c, MUX_MODE15) - DRA7XX_CORE_IOPAD(0x3640, MUX_MODE15) - >; - }; -}; - &mac { status = "okay"; - pinctrl-names = "default", "sleep"; - pinctrl-0 = <&cpsw_default>; - pinctrl-1 = <&cpsw_sleep>; -}; - -&davinci_mdio { - pinctrl-names = "default", "sleep"; - pinctrl-0 = <&davinci_mdio_default>; - pinctrl-1 = <&davinci_mdio_sleep>; }; &dcan1 { @@ -741,16 +482,11 @@ &dss { status = "ok"; - - vdda_video-supply = <&ldo5_reg>; }; &hdmi { status = "ok"; - pinctrl-names = "default"; - pinctrl-0 = <&hdmi_pins>; - port { hdmi_out: endpoint { remote-endpoint = <&tpd12s015_in>; @@ -759,9 +495,6 @@ }; &atl { - pinctrl-names = "default"; - pinctrl-0 = <&atl_pins>; - assigned-clocks = <&abe_dpll_sys_clk_mux>, <&atl_gfclk_mux>, <&dpll_abe_ck>, @@ -780,9 +513,6 @@ &mcasp3 { #sound-dai-cells = <0>; - pinctrl-names = "default", "sleep"; - pinctrl-0 = <&mcasp3_pins>; - pinctrl-1 = <&mcasp3_sleep_pins>; assigned-clocks = <&mcasp3_ahclkx_mux>; assigned-clock-parents = <&atl_clkin2_ck>; diff --git a/arch/arm/boot/dts/dra72-evm-revc.dts b/arch/arm/boot/dts/dra72-evm-revc.dts index 064b322a7a04..4ea2a0c7819e 100644 --- a/arch/arm/boot/dts/dra72-evm-revc.dts +++ b/arch/arm/boot/dts/dra72-evm-revc.dts @@ -17,17 +17,22 @@ }; }; -&tps65917_regulators { - ldo2_reg: ldo2 { - /* LDO2_OUT --> VDDA_1V8_PHY2 */ - regulator-name = "ldo2"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-always-on; - regulator-boot-on; +&i2c1 { + tps65917: tps65917@58 { + reg = <0x58>; + + interrupts = <GIC_SPI 2 IRQ_TYPE_NONE>; /* IRQ_SYS_1N */ }; }; +#include "dra72-evm-tps65917.dtsi" + +&ldo2_reg { + /* LDO2_OUT --> VDDA_1V8_PHY2 */ + regulator-always-on; + regulator-boot-on; +}; + &hdmi { vdda-supply = <&ldo2_reg>; }; diff --git a/arch/arm/boot/dts/dra72-evm-tps65917.dtsi b/arch/arm/boot/dts/dra72-evm-tps65917.dtsi new file mode 100644 index 000000000000..ee6dac44edf1 --- /dev/null +++ b/arch/arm/boot/dts/dra72-evm-tps65917.dtsi @@ -0,0 +1,134 @@ +/* + * Copyright (C) 2016 Texas Instruments Incorporated - http://www.ti.com/ + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +/* + * Integrated Power Management Chip + * http://www.ti.com/lit/ds/symlink/tps65917-q1.pdf + */ + +&tps65917 { + compatible = "ti,tps65917"; + + interrupt-controller; + #interrupt-cells = <2>; + + ti,system-power-controller; + + tps65917_pmic { + compatible = "ti,tps65917-pmic"; + + smps1-in-supply = <&vsys_3v3>; + smps2-in-supply = <&vsys_3v3>; + smps3-in-supply = <&vsys_3v3>; + smps4-in-supply = <&vsys_3v3>; + smps5-in-supply = <&vsys_3v3>; + ldo1-in-supply = <&vsys_3v3>; + ldo2-in-supply = <&vsys_3v3>; + ldo3-in-supply = <&vsys_3v3>; + ldo4-in-supply = <&evm_5v0>; + ldo5-in-supply = <&vsys_3v3>; + + tps65917_regulators: regulators { + smps1_reg: smps1 { + /* VDD_MPU */ + regulator-name = "smps1"; + regulator-min-microvolt = <850000>; + regulator-max-microvolt = <1250000>; + regulator-always-on; + regulator-boot-on; + }; + + smps2_reg: smps2 { + /* VDD_CORE */ + regulator-name = "smps2"; + regulator-min-microvolt = <850000>; + regulator-max-microvolt = <1150000>; + regulator-boot-on; + regulator-always-on; + }; + + smps3_reg: smps3 { + /* VDD_GPU IVA DSPEVE */ + regulator-name = "smps3"; + regulator-min-microvolt = <850000>; + regulator-max-microvolt = <1250000>; + regulator-boot-on; + regulator-always-on; + }; + + smps4_reg: smps4 { + /* VDDS1V8 */ + regulator-name = "smps4"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + regulator-boot-on; + }; + + smps5_reg: smps5 { + /* VDD_DDR */ + regulator-name = "smps5"; + regulator-min-microvolt = <1350000>; + regulator-max-microvolt = <1350000>; + regulator-boot-on; + regulator-always-on; + }; + + ldo1_reg: ldo1 { + /* LDO1_OUT --> SDIO */ + regulator-name = "ldo1"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + regulator-boot-on; + regulator-allow-bypass; + }; + + ldo2_reg: ldo2 { + regulator-name = "ldo2"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-allow-bypass; + }; + + ldo3_reg: ldo3 { + /* VDDA_1V8_PHY */ + regulator-name = "ldo3"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-boot-on; + regulator-always-on; + }; + + ldo5_reg: ldo5 { + /* VDDA_1V8_PLL */ + regulator-name = "ldo5"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + regulator-boot-on; + }; + + ldo4_reg: ldo4 { + /* VDDA_3V_USB: VDDA_USBHS33 */ + regulator-name = "ldo4"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-boot-on; + }; + }; + }; + + tps65917_power_button { + compatible = "ti,palmas-pwrbutton"; + interrupt-parent = <&tps65917>; + interrupts = <1 IRQ_TYPE_NONE>; + wakeup-source; + ti,palmas-long-press-seconds = <6>; + }; +}; diff --git a/arch/arm/boot/dts/dra72-evm.dts b/arch/arm/boot/dts/dra72-evm.dts index e3a9b6985693..cd9c4ff12654 100644 --- a/arch/arm/boot/dts/dra72-evm.dts +++ b/arch/arm/boot/dts/dra72-evm.dts @@ -15,16 +15,16 @@ }; }; -&tps65917_regulators { - ldo2_reg: ldo2 { - /* LDO2_OUT --> TP1017 (UNUSED) */ - regulator-name = "ldo2"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <3300000>; - regulator-allow-bypass; +&i2c1 { + tps65917: tps65917@58 { + reg = <0x58>; + + interrupts = <GIC_SPI 2 IRQ_TYPE_NONE>; /* IRQ_SYS_1N */ }; }; +#include "dra72-evm-tps65917.dtsi" + &hdmi { vdda-supply = <&ldo3_reg>; }; diff --git a/arch/arm/boot/dts/emev2.dtsi b/arch/arm/boot/dts/emev2.dtsi index cd119400f440..0124faf175c8 100644 --- a/arch/arm/boot/dts/emev2.dtsi +++ b/arch/arm/boot/dts/emev2.dtsi @@ -8,13 +8,14 @@ * kind, whether express or implied. */ -#include "skeleton.dtsi" #include <dt-bindings/interrupt-controller/arm-gic.h> #include <dt-bindings/interrupt-controller/irq.h> / { compatible = "renesas,emev2"; interrupt-parent = <&gic>; + #address-cells = <1>; + #size-cells = <1>; aliases { gpio0 = &gpio0; diff --git a/arch/arm/boot/dts/exynos3250-pinctrl.dtsi b/arch/arm/boot/dts/exynos3250-pinctrl.dtsi index ec331169c3d9..a149f148e659 100644 --- a/arch/arm/boot/dts/exynos3250-pinctrl.dtsi +++ b/arch/arm/boot/dts/exynos3250-pinctrl.dtsi @@ -362,8 +362,14 @@ interrupt-controller; interrupt-parent = <&gic>; - interrupts = <0 32 0>, <0 33 0>, <0 34 0>, <0 35 0>, - <0 36 0>, <0 37 0>, <0 38 0>, <0 39 0>; + interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>; #interrupt-cells = <2>; }; @@ -373,8 +379,14 @@ interrupt-controller; interrupt-parent = <&gic>; - interrupts = <0 40 0>, <0 41 0>, <0 42 0>, <0 43 0>, - <0 44 0>, <0 45 0>, <0 46 0>, <0 47 0>; + interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>; #interrupt-cells = <2>; }; diff --git a/arch/arm/boot/dts/exynos3250.dtsi b/arch/arm/boot/dts/exynos3250.dtsi index e9d2556c0dfd..ba17ee1eb749 100644 --- a/arch/arm/boot/dts/exynos3250.dtsi +++ b/arch/arm/boot/dts/exynos3250.dtsi @@ -20,6 +20,8 @@ #include "exynos4-cpu-thermal.dtsi" #include "exynos-syscon-restart.dtsi" #include <dt-bindings/clock/exynos3250.h> +#include <dt-bindings/interrupt-controller/arm-gic.h> +#include <dt-bindings/interrupt-controller/irq.h> / { compatible = "samsung,exynos3250"; @@ -211,7 +213,8 @@ rtc: rtc@10070000 { compatible = "samsung,s3c6410-rtc"; reg = <0x10070000 0x100>; - interrupts = <0 73 0>, <0 74 0>; + interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>; interrupt-parent = <&pmu_system_controller>; status = "disabled"; }; @@ -219,7 +222,7 @@ tmu: tmu@100C0000 { compatible = "samsung,exynos3250-tmu"; reg = <0x100C0000 0x100>; - interrupts = <0 216 0>; + interrupts = <GIC_SPI 216 IRQ_TYPE_LEVEL_HIGH>; clocks = <&cmu CLK_TMU_APBIF>; clock-names = "tmu_apbif"; #include "exynos4412-tmu-sensor-conf.dtsi" @@ -234,14 +237,21 @@ <0x10482000 0x1000>, <0x10484000 0x2000>, <0x10486000 0x2000>; - interrupts = <1 9 0xf04>; + interrupts = <GIC_PPI 9 + (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; }; mct@10050000 { compatible = "samsung,exynos4210-mct"; reg = <0x10050000 0x800>; - interrupts = <0 218 0>, <0 219 0>, <0 220 0>, <0 221 0>, - <0 223 0>, <0 226 0>, <0 227 0>, <0 228 0>; + interrupts = <GIC_SPI 218 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 219 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 220 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 221 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 223 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 226 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 227 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 228 IRQ_TYPE_LEVEL_HIGH>; clocks = <&cmu CLK_FIN_PLL>, <&cmu CLK_MCT>; clock-names = "fin_pll", "mct"; }; @@ -249,24 +259,24 @@ pinctrl_1: pinctrl@11000000 { compatible = "samsung,exynos3250-pinctrl"; reg = <0x11000000 0x1000>; - interrupts = <0 225 0>; + interrupts = <GIC_SPI 225 IRQ_TYPE_LEVEL_HIGH>; wakeup-interrupt-controller { compatible = "samsung,exynos4210-wakeup-eint"; - interrupts = <0 48 0>; + interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>; }; }; pinctrl_0: pinctrl@11400000 { compatible = "samsung,exynos3250-pinctrl"; reg = <0x11400000 0x1000>; - interrupts = <0 240 0>; + interrupts = <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>; }; jpeg: codec@11830000 { compatible = "samsung,exynos3250-jpeg"; reg = <0x11830000 0x1000>; - interrupts = <0 171 0>; + interrupts = <GIC_SPI 171 IRQ_TYPE_LEVEL_HIGH>; clocks = <&cmu CLK_JPEG>, <&cmu CLK_SCLK_JPEG>; clock-names = "jpeg", "sclk"; power-domains = <&pd_cam>; @@ -280,7 +290,8 @@ sysmmu_jpeg: sysmmu@11A60000 { compatible = "samsung,exynos-sysmmu"; reg = <0x11a60000 0x1000>; - interrupts = <0 156 0>, <0 161 0>; + interrupts = <GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>; clock-names = "sysmmu", "master"; clocks = <&cmu CLK_SMMUJPEG>, <&cmu CLK_JPEG>; power-domains = <&pd_cam>; @@ -291,7 +302,9 @@ compatible = "samsung,exynos3250-fimd"; reg = <0x11c00000 0x30000>; interrupt-names = "fifo", "vsync", "lcd_sys"; - interrupts = <0 84 0>, <0 85 0>, <0 86 0>; + interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>; clocks = <&cmu CLK_SCLK_FIMD0>, <&cmu CLK_FIMD0>; clock-names = "sclk_fimd", "fimd"; power-domains = <&pd_lcd0>; @@ -303,7 +316,7 @@ dsi_0: dsi@11C80000 { compatible = "samsung,exynos3250-mipi-dsi"; reg = <0x11C80000 0x10000>; - interrupts = <0 83 0>; + interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>; samsung,phy-type = <0>; power-domains = <&pd_lcd0>; phys = <&mipi_phy 1>; @@ -318,7 +331,8 @@ sysmmu_fimd0: sysmmu@11E20000 { compatible = "samsung,exynos-sysmmu"; reg = <0x11e20000 0x1000>; - interrupts = <0 80 0>, <0 81 0>; + interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>; clock-names = "sysmmu", "master"; clocks = <&cmu CLK_SMMUFIMD0>, <&cmu CLK_FIMD0>; power-domains = <&pd_lcd0>; @@ -328,7 +342,7 @@ hsotg: hsotg@12480000 { compatible = "snps,dwc2"; reg = <0x12480000 0x20000>; - interrupts = <0 141 0>; + interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>; clocks = <&cmu CLK_USBOTG>; clock-names = "otg"; phys = <&exynos_usbphy 0>; @@ -339,7 +353,7 @@ mshc_0: mshc@12510000 { compatible = "samsung,exynos5420-dw-mshc"; reg = <0x12510000 0x1000>; - interrupts = <0 142 0>; + interrupts = <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>; clocks = <&cmu CLK_SDMMC0>, <&cmu CLK_SCLK_MMC0>; clock-names = "biu", "ciu"; fifo-depth = <0x80>; @@ -351,7 +365,7 @@ mshc_1: mshc@12520000 { compatible = "samsung,exynos5420-dw-mshc"; reg = <0x12520000 0x1000>; - interrupts = <0 143 0>; + interrupts = <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>; clocks = <&cmu CLK_SDMMC1>, <&cmu CLK_SCLK_MMC1>; clock-names = "biu", "ciu"; fifo-depth = <0x80>; @@ -363,7 +377,7 @@ mshc_2: mshc@12530000 { compatible = "samsung,exynos5250-dw-mshc"; reg = <0x12530000 0x1000>; - interrupts = <0 144 0>; + interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>; clocks = <&cmu CLK_SDMMC2>, <&cmu CLK_SCLK_MMC2>; clock-names = "biu", "ciu"; fifo-depth = <0x80>; @@ -391,7 +405,7 @@ pdma0: pdma@12680000 { compatible = "arm,pl330", "arm,primecell"; reg = <0x12680000 0x1000>; - interrupts = <0 138 0>; + interrupts = <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>; clocks = <&cmu CLK_PDMA0>; clock-names = "apb_pclk"; #dma-cells = <1>; @@ -402,7 +416,7 @@ pdma1: pdma@12690000 { compatible = "arm,pl330", "arm,primecell"; reg = <0x12690000 0x1000>; - interrupts = <0 139 0>; + interrupts = <GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH>; clocks = <&cmu CLK_PDMA1>; clock-names = "apb_pclk"; #dma-cells = <1>; @@ -415,7 +429,7 @@ compatible = "samsung,exynos3250-adc", "samsung,exynos-adc-v2"; reg = <0x126C0000 0x100>; - interrupts = <0 137 0>; + interrupts = <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>; clock-names = "adc", "sclk"; clocks = <&cmu CLK_TSADC>, <&cmu CLK_SCLK_TSADC>; #io-channel-cells = <1>; @@ -427,7 +441,7 @@ mfc: codec@13400000 { compatible = "samsung,mfc-v7"; reg = <0x13400000 0x10000>; - interrupts = <0 102 0>; + interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>; clock-names = "mfc", "sclk_mfc"; clocks = <&cmu CLK_MFC>, <&cmu CLK_SCLK_MFC>; power-domains = <&pd_mfc>; @@ -437,7 +451,8 @@ sysmmu_mfc: sysmmu@13620000 { compatible = "samsung,exynos-sysmmu"; reg = <0x13620000 0x1000>; - interrupts = <0 96 0>, <0 98 0>; + interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>; clock-names = "sysmmu", "master"; clocks = <&cmu CLK_SMMUMFC_L>, <&cmu CLK_MFC>; power-domains = <&pd_mfc>; @@ -447,7 +462,7 @@ serial_0: serial@13800000 { compatible = "samsung,exynos4210-uart"; reg = <0x13800000 0x100>; - interrupts = <0 109 0>; + interrupts = <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>; clocks = <&cmu CLK_UART0>, <&cmu CLK_SCLK_UART0>; clock-names = "uart", "clk_uart_baud0"; pinctrl-names = "default"; @@ -458,7 +473,7 @@ serial_1: serial@13810000 { compatible = "samsung,exynos4210-uart"; reg = <0x13810000 0x100>; - interrupts = <0 110 0>; + interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>; clocks = <&cmu CLK_UART1>, <&cmu CLK_SCLK_UART1>; clock-names = "uart", "clk_uart_baud0"; pinctrl-names = "default"; @@ -469,7 +484,7 @@ serial_2: serial@13820000 { compatible = "samsung,exynos4210-uart"; reg = <0x13820000 0x100>; - interrupts = <0 111 0>; + interrupts = <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>; clocks = <&cmu CLK_UART2>, <&cmu CLK_SCLK_UART2>; clock-names = "uart", "clk_uart_baud0"; pinctrl-names = "default"; @@ -482,7 +497,7 @@ #size-cells = <0>; compatible = "samsung,s3c2440-i2c"; reg = <0x13860000 0x100>; - interrupts = <0 113 0>; + interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>; clocks = <&cmu CLK_I2C0>; clock-names = "i2c"; pinctrl-names = "default"; @@ -495,7 +510,7 @@ #size-cells = <0>; compatible = "samsung,s3c2440-i2c"; reg = <0x13870000 0x100>; - interrupts = <0 114 0>; + interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>; clocks = <&cmu CLK_I2C1>; clock-names = "i2c"; pinctrl-names = "default"; @@ -508,7 +523,7 @@ #size-cells = <0>; compatible = "samsung,s3c2440-i2c"; reg = <0x13880000 0x100>; - interrupts = <0 115 0>; + interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>; clocks = <&cmu CLK_I2C2>; clock-names = "i2c"; pinctrl-names = "default"; @@ -521,7 +536,7 @@ #size-cells = <0>; compatible = "samsung,s3c2440-i2c"; reg = <0x13890000 0x100>; - interrupts = <0 116 0>; + interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>; clocks = <&cmu CLK_I2C3>; clock-names = "i2c"; pinctrl-names = "default"; @@ -534,7 +549,7 @@ #size-cells = <0>; compatible = "samsung,s3c2440-i2c"; reg = <0x138A0000 0x100>; - interrupts = <0 117 0>; + interrupts = <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>; clocks = <&cmu CLK_I2C4>; clock-names = "i2c"; pinctrl-names = "default"; @@ -547,7 +562,7 @@ #size-cells = <0>; compatible = "samsung,s3c2440-i2c"; reg = <0x138B0000 0x100>; - interrupts = <0 118 0>; + interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>; clocks = <&cmu CLK_I2C5>; clock-names = "i2c"; pinctrl-names = "default"; @@ -560,7 +575,7 @@ #size-cells = <0>; compatible = "samsung,s3c2440-i2c"; reg = <0x138C0000 0x100>; - interrupts = <0 119 0>; + interrupts = <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>; clocks = <&cmu CLK_I2C6>; clock-names = "i2c"; pinctrl-names = "default"; @@ -573,7 +588,7 @@ #size-cells = <0>; compatible = "samsung,s3c2440-i2c"; reg = <0x138D0000 0x100>; - interrupts = <0 120 0>; + interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>; clocks = <&cmu CLK_I2C7>; clock-names = "i2c"; pinctrl-names = "default"; @@ -584,7 +599,7 @@ spi_0: spi@13920000 { compatible = "samsung,exynos4210-spi"; reg = <0x13920000 0x100>; - interrupts = <0 121 0>; + interrupts = <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>; dmas = <&pdma0 7>, <&pdma0 6>; dma-names = "tx", "rx"; #address-cells = <1>; @@ -600,7 +615,7 @@ spi_1: spi@13930000 { compatible = "samsung,exynos4210-spi"; reg = <0x13930000 0x100>; - interrupts = <0 122 0>; + interrupts = <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>; dmas = <&pdma1 7>, <&pdma1 6>; dma-names = "tx", "rx"; #address-cells = <1>; @@ -616,7 +631,7 @@ i2s2: i2s@13970000 { compatible = "samsung,s3c6410-i2s"; reg = <0x13970000 0x100>; - interrupts = <0 126 0>; + interrupts = <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>; clocks = <&cmu CLK_I2S>, <&cmu CLK_SCLK_I2S>; clock-names = "iis", "i2s_opclk0"; dmas = <&pdma0 14>, <&pdma0 13>; @@ -629,15 +644,19 @@ pwm: pwm@139D0000 { compatible = "samsung,exynos4210-pwm"; reg = <0x139D0000 0x1000>; - interrupts = <0 104 0>, <0 105 0>, <0 106 0>, - <0 107 0>, <0 108 0>; + interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>; #pwm-cells = <3>; status = "disabled"; }; pmu { compatible = "arm,cortex-a7-pmu"; - interrupts = <0 18 0>, <0 19 0>; + interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>; }; ppmu_dmc0: ppmu_dmc0@106a0000 { diff --git a/arch/arm/boot/dts/exynos4.dtsi b/arch/arm/boot/dts/exynos4.dtsi index 5f034eb5a5e2..c64737baa45e 100644 --- a/arch/arm/boot/dts/exynos4.dtsi +++ b/arch/arm/boot/dts/exynos4.dtsi @@ -21,6 +21,8 @@ #include <dt-bindings/clock/exynos4.h> #include <dt-bindings/clock/exynos-audss-clk.h> +#include <dt-bindings/interrupt-controller/arm-gic.h> +#include <dt-bindings/interrupt-controller/irq.h> #include "exynos-syscon-restart.dtsi" / { @@ -78,6 +80,11 @@ reg = <0x10000000 0x100>; }; + scu: snoop-control-unit@10500000 { + compatible = "arm,cortex-a9-scu"; + reg = <0x10500000 0x2000>; + }; + memory-controller@12570000 { compatible = "samsung,exynos4210-srom"; reg = <0x12570000 0x14>; @@ -168,7 +175,7 @@ dsi_0: dsi@11C80000 { compatible = "samsung,exynos4210-mipi-dsi"; reg = <0x11C80000 0x10000>; - interrupts = <0 79 0>; + interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>; power-domains = <&pd_lcd0>; phys = <&mipi_phy 1>; phy-names = "dsim"; @@ -191,7 +198,7 @@ fimc_0: fimc@11800000 { compatible = "samsung,exynos4210-fimc"; reg = <0x11800000 0x1000>; - interrupts = <0 84 0>; + interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>; clocks = <&clock CLK_FIMC0>, <&clock CLK_SCLK_FIMC0>; clock-names = "fimc", "sclk_fimc"; power-domains = <&pd_cam>; @@ -203,7 +210,7 @@ fimc_1: fimc@11810000 { compatible = "samsung,exynos4210-fimc"; reg = <0x11810000 0x1000>; - interrupts = <0 85 0>; + interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>; clocks = <&clock CLK_FIMC1>, <&clock CLK_SCLK_FIMC1>; clock-names = "fimc", "sclk_fimc"; power-domains = <&pd_cam>; @@ -215,7 +222,7 @@ fimc_2: fimc@11820000 { compatible = "samsung,exynos4210-fimc"; reg = <0x11820000 0x1000>; - interrupts = <0 86 0>; + interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>; clocks = <&clock CLK_FIMC2>, <&clock CLK_SCLK_FIMC2>; clock-names = "fimc", "sclk_fimc"; power-domains = <&pd_cam>; @@ -227,7 +234,7 @@ fimc_3: fimc@11830000 { compatible = "samsung,exynos4210-fimc"; reg = <0x11830000 0x1000>; - interrupts = <0 87 0>; + interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>; clocks = <&clock CLK_FIMC3>, <&clock CLK_SCLK_FIMC3>; clock-names = "fimc", "sclk_fimc"; power-domains = <&pd_cam>; @@ -239,7 +246,7 @@ csis_0: csis@11880000 { compatible = "samsung,exynos4210-csis"; reg = <0x11880000 0x4000>; - interrupts = <0 78 0>; + interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>; clocks = <&clock CLK_CSIS0>, <&clock CLK_SCLK_CSIS0>; clock-names = "csis", "sclk_csis"; bus-width = <4>; @@ -254,7 +261,7 @@ csis_1: csis@11890000 { compatible = "samsung,exynos4210-csis"; reg = <0x11890000 0x4000>; - interrupts = <0 80 0>; + interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>; clocks = <&clock CLK_CSIS1>, <&clock CLK_SCLK_CSIS1>; clock-names = "csis", "sclk_csis"; bus-width = <2>; @@ -270,7 +277,7 @@ watchdog: watchdog@10060000 { compatible = "samsung,s3c2410-wdt"; reg = <0x10060000 0x100>; - interrupts = <0 43 0>; + interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>; clocks = <&clock CLK_WDT>; clock-names = "watchdog"; status = "disabled"; @@ -280,7 +287,8 @@ compatible = "samsung,s3c6410-rtc"; reg = <0x10070000 0x100>; interrupt-parent = <&pmu_system_controller>; - interrupts = <0 44 0>, <0 45 0>; + interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>; clocks = <&clock CLK_RTC>; clock-names = "rtc"; status = "disabled"; @@ -289,7 +297,7 @@ keypad: keypad@100A0000 { compatible = "samsung,s5pv210-keypad"; reg = <0x100A0000 0x100>; - interrupts = <0 109 0>; + interrupts = <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>; clocks = <&clock CLK_KEYIF>; clock-names = "keypad"; status = "disabled"; @@ -298,7 +306,7 @@ sdhci_0: sdhci@12510000 { compatible = "samsung,exynos4210-sdhci"; reg = <0x12510000 0x100>; - interrupts = <0 73 0>; + interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>; clocks = <&clock CLK_SDMMC0>, <&clock CLK_SCLK_MMC0>; clock-names = "hsmmc", "mmc_busclk.2"; status = "disabled"; @@ -307,7 +315,7 @@ sdhci_1: sdhci@12520000 { compatible = "samsung,exynos4210-sdhci"; reg = <0x12520000 0x100>; - interrupts = <0 74 0>; + interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>; clocks = <&clock CLK_SDMMC1>, <&clock CLK_SCLK_MMC1>; clock-names = "hsmmc", "mmc_busclk.2"; status = "disabled"; @@ -316,7 +324,7 @@ sdhci_2: sdhci@12530000 { compatible = "samsung,exynos4210-sdhci"; reg = <0x12530000 0x100>; - interrupts = <0 75 0>; + interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>; clocks = <&clock CLK_SDMMC2>, <&clock CLK_SCLK_MMC2>; clock-names = "hsmmc", "mmc_busclk.2"; status = "disabled"; @@ -325,7 +333,7 @@ sdhci_3: sdhci@12540000 { compatible = "samsung,exynos4210-sdhci"; reg = <0x12540000 0x100>; - interrupts = <0 76 0>; + interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>; clocks = <&clock CLK_SDMMC3>, <&clock CLK_SCLK_MMC3>; clock-names = "hsmmc", "mmc_busclk.2"; status = "disabled"; @@ -344,7 +352,7 @@ hsotg: hsotg@12480000 { compatible = "samsung,s3c6400-hsotg"; reg = <0x12480000 0x20000>; - interrupts = <0 71 0>; + interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>; clocks = <&clock CLK_USB_DEVICE>; clock-names = "otg"; phys = <&exynos_usbphy 0>; @@ -355,7 +363,7 @@ ehci: ehci@12580000 { compatible = "samsung,exynos4210-ehci"; reg = <0x12580000 0x100>; - interrupts = <0 70 0>; + interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>; clocks = <&clock CLK_USB_HOST>; clock-names = "usbhost"; status = "disabled"; @@ -381,7 +389,7 @@ ohci: ohci@12590000 { compatible = "samsung,exynos4210-ohci"; reg = <0x12590000 0x100>; - interrupts = <0 70 0>; + interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>; clocks = <&clock CLK_USB_HOST>; clock-names = "usbhost"; status = "disabled"; @@ -423,7 +431,7 @@ mfc: codec@13400000 { compatible = "samsung,mfc-v5"; reg = <0x13400000 0x10000>; - interrupts = <0 94 0>; + interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>; power-domains = <&pd_mfc>; clocks = <&clock CLK_MFC>, <&clock CLK_SCLK_MFC>; clock-names = "mfc", "sclk_mfc"; @@ -434,7 +442,7 @@ serial_0: serial@13800000 { compatible = "samsung,exynos4210-uart"; reg = <0x13800000 0x100>; - interrupts = <0 52 0>; + interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>; clocks = <&clock CLK_UART0>, <&clock CLK_SCLK_UART0>; clock-names = "uart", "clk_uart_baud0"; dmas = <&pdma0 15>, <&pdma0 16>; @@ -445,7 +453,7 @@ serial_1: serial@13810000 { compatible = "samsung,exynos4210-uart"; reg = <0x13810000 0x100>; - interrupts = <0 53 0>; + interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>; clocks = <&clock CLK_UART1>, <&clock CLK_SCLK_UART1>; clock-names = "uart", "clk_uart_baud0"; dmas = <&pdma1 15>, <&pdma1 16>; @@ -456,7 +464,7 @@ serial_2: serial@13820000 { compatible = "samsung,exynos4210-uart"; reg = <0x13820000 0x100>; - interrupts = <0 54 0>; + interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>; clocks = <&clock CLK_UART2>, <&clock CLK_SCLK_UART2>; clock-names = "uart", "clk_uart_baud0"; dmas = <&pdma0 17>, <&pdma0 18>; @@ -467,7 +475,7 @@ serial_3: serial@13830000 { compatible = "samsung,exynos4210-uart"; reg = <0x13830000 0x100>; - interrupts = <0 55 0>; + interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>; clocks = <&clock CLK_UART3>, <&clock CLK_SCLK_UART3>; clock-names = "uart", "clk_uart_baud0"; dmas = <&pdma1 17>, <&pdma1 18>; @@ -480,7 +488,7 @@ #size-cells = <0>; compatible = "samsung,s3c2440-i2c"; reg = <0x13860000 0x100>; - interrupts = <0 58 0>; + interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>; clocks = <&clock CLK_I2C0>; clock-names = "i2c"; pinctrl-names = "default"; @@ -493,7 +501,7 @@ #size-cells = <0>; compatible = "samsung,s3c2440-i2c"; reg = <0x13870000 0x100>; - interrupts = <0 59 0>; + interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>; clocks = <&clock CLK_I2C1>; clock-names = "i2c"; pinctrl-names = "default"; @@ -506,7 +514,7 @@ #size-cells = <0>; compatible = "samsung,s3c2440-i2c"; reg = <0x13880000 0x100>; - interrupts = <0 60 0>; + interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>; clocks = <&clock CLK_I2C2>; clock-names = "i2c"; pinctrl-names = "default"; @@ -519,7 +527,7 @@ #size-cells = <0>; compatible = "samsung,s3c2440-i2c"; reg = <0x13890000 0x100>; - interrupts = <0 61 0>; + interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>; clocks = <&clock CLK_I2C3>; clock-names = "i2c"; pinctrl-names = "default"; @@ -532,7 +540,7 @@ #size-cells = <0>; compatible = "samsung,s3c2440-i2c"; reg = <0x138A0000 0x100>; - interrupts = <0 62 0>; + interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>; clocks = <&clock CLK_I2C4>; clock-names = "i2c"; pinctrl-names = "default"; @@ -545,7 +553,7 @@ #size-cells = <0>; compatible = "samsung,s3c2440-i2c"; reg = <0x138B0000 0x100>; - interrupts = <0 63 0>; + interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>; clocks = <&clock CLK_I2C5>; clock-names = "i2c"; pinctrl-names = "default"; @@ -558,7 +566,7 @@ #size-cells = <0>; compatible = "samsung,s3c2440-i2c"; reg = <0x138C0000 0x100>; - interrupts = <0 64 0>; + interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>; clocks = <&clock CLK_I2C6>; clock-names = "i2c"; pinctrl-names = "default"; @@ -571,7 +579,7 @@ #size-cells = <0>; compatible = "samsung,s3c2440-i2c"; reg = <0x138D0000 0x100>; - interrupts = <0 65 0>; + interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>; clocks = <&clock CLK_I2C7>; clock-names = "i2c"; pinctrl-names = "default"; @@ -584,7 +592,7 @@ #size-cells = <0>; compatible = "samsung,s3c2440-hdmiphy-i2c"; reg = <0x138E0000 0x100>; - interrupts = <0 93 0>; + interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>; clocks = <&clock CLK_I2C_HDMI>; clock-names = "i2c"; status = "disabled"; @@ -598,7 +606,7 @@ spi_0: spi@13920000 { compatible = "samsung,exynos4210-spi"; reg = <0x13920000 0x100>; - interrupts = <0 66 0>; + interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>; dmas = <&pdma0 7>, <&pdma0 6>; dma-names = "tx", "rx"; #address-cells = <1>; @@ -613,7 +621,7 @@ spi_1: spi@13930000 { compatible = "samsung,exynos4210-spi"; reg = <0x13930000 0x100>; - interrupts = <0 67 0>; + interrupts = <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>; dmas = <&pdma1 7>, <&pdma1 6>; dma-names = "tx", "rx"; #address-cells = <1>; @@ -628,7 +636,7 @@ spi_2: spi@13940000 { compatible = "samsung,exynos4210-spi"; reg = <0x13940000 0x100>; - interrupts = <0 68 0>; + interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>; dmas = <&pdma0 9>, <&pdma0 8>; dma-names = "tx", "rx"; #address-cells = <1>; @@ -643,7 +651,11 @@ pwm: pwm@139D0000 { compatible = "samsung,exynos4210-pwm"; reg = <0x139D0000 0x1000>; - interrupts = <0 37 0>, <0 38 0>, <0 39 0>, <0 40 0>, <0 41 0>; + interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>; clocks = <&clock CLK_PWM>; clock-names = "timers"; #pwm-cells = <3>; @@ -660,7 +672,7 @@ pdma0: pdma@12680000 { compatible = "arm,pl330", "arm,primecell"; reg = <0x12680000 0x1000>; - interrupts = <0 35 0>; + interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>; clocks = <&clock CLK_PDMA0>; clock-names = "apb_pclk"; #dma-cells = <1>; @@ -671,7 +683,7 @@ pdma1: pdma@12690000 { compatible = "arm,pl330", "arm,primecell"; reg = <0x12690000 0x1000>; - interrupts = <0 36 0>; + interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>; clocks = <&clock CLK_PDMA1>; clock-names = "apb_pclk"; #dma-cells = <1>; @@ -682,7 +694,7 @@ mdma1: mdma@12850000 { compatible = "arm,pl330", "arm,primecell"; reg = <0x12850000 0x1000>; - interrupts = <0 34 0>; + interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>; clocks = <&clock CLK_MDMA>; clock-names = "apb_pclk"; #dma-cells = <1>; @@ -712,7 +724,7 @@ jpeg_codec: jpeg-codec@11840000 { compatible = "samsung,exynos4210-jpeg"; reg = <0x11840000 0x1000>; - interrupts = <0 88 0>; + interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>; clocks = <&clock CLK_JPEG>; clock-names = "jpeg"; power-domains = <&pd_cam>; @@ -722,7 +734,7 @@ rotator: rotator@12810000 { compatible = "samsung,exynos4210-rotator"; reg = <0x12810000 0x64>; - interrupts = <0 83 0>; + interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>; clocks = <&clock CLK_ROTATOR>; clock-names = "rotator"; iommus = <&sysmmu_rotator>; @@ -731,7 +743,7 @@ hdmi: hdmi@12D00000 { compatible = "samsung,exynos4210-hdmi"; reg = <0x12D00000 0x70000>; - interrupts = <0 92 0>; + interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>; clock-names = "hdmi", "sclk_hdmi", "sclk_pixel", "sclk_hdmiphy", "mout_hdmi"; clocks = <&clock CLK_HDMI>, <&clock CLK_SCLK_HDMI>, @@ -746,7 +758,7 @@ hdmicec: cec@100B0000 { compatible = "samsung,s5p-cec"; reg = <0x100B0000 0x200>; - interrupts = <0 114 0>; + interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>; clocks = <&clock CLK_HDMI_CEC>; clock-names = "hdmicec"; samsung,syscon-phandle = <&pmu_system_controller>; @@ -757,7 +769,7 @@ mixer: mixer@12C10000 { compatible = "samsung,exynos4210-mixer"; - interrupts = <0 91 0>; + interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>; reg = <0x12C10000 0x2100>, <0x12c00000 0x300>; power-domains = <&pd_tv>; iommus = <&sysmmu_tv>; @@ -984,7 +996,7 @@ sss: sss@10830000 { compatible = "samsung,exynos4210-secss"; reg = <0x10830000 0x300>; - interrupts = <0 112 0>; + interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>; clocks = <&clock CLK_SSS>; clock-names = "secss"; }; diff --git a/arch/arm/boot/dts/exynos4210-pinctrl.dtsi b/arch/arm/boot/dts/exynos4210-pinctrl.dtsi index d9b6d25e4abe..f280954b260a 100644 --- a/arch/arm/boot/dts/exynos4210-pinctrl.dtsi +++ b/arch/arm/boot/dts/exynos4210-pinctrl.dtsi @@ -537,8 +537,14 @@ interrupt-controller; interrupt-parent = <&gic>; - interrupts = <0 16 0>, <0 17 0>, <0 18 0>, <0 19 0>, - <0 20 0>, <0 21 0>, <0 22 0>, <0 23 0>; + interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>; #interrupt-cells = <2>; }; @@ -548,8 +554,14 @@ interrupt-controller; interrupt-parent = <&gic>; - interrupts = <0 24 0>, <0 25 0>, <0 26 0>, <0 27 0>, - <0 28 0>, <0 29 0>, <0 30 0>, <0 31 0>; + interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>; #interrupt-cells = <2>; }; diff --git a/arch/arm/boot/dts/exynos4210.dtsi b/arch/arm/boot/dts/exynos4210.dtsi index 2d9b02967105..7f3a18c8f60f 100644 --- a/arch/arm/boot/dts/exynos4210.dtsi +++ b/arch/arm/boot/dts/exynos4210.dtsi @@ -109,12 +109,12 @@ #interrupt-cells = <1>; #address-cells = <0>; #size-cells = <0>; - interrupt-map = <0 &gic 0 57 0>, - <1 &gic 0 69 0>, + interrupt-map = <0 &gic 0 57 IRQ_TYPE_LEVEL_HIGH>, + <1 &gic 0 69 IRQ_TYPE_LEVEL_HIGH>, <2 &combiner 12 6>, <3 &combiner 12 7>, - <4 &gic 0 42 0>, - <5 &gic 0 48 0>; + <4 &gic 0 42 IRQ_TYPE_LEVEL_HIGH>, + <5 &gic 0 48 IRQ_TYPE_LEVEL_HIGH>; }; }; @@ -127,18 +127,18 @@ pinctrl_0: pinctrl@11400000 { compatible = "samsung,exynos4210-pinctrl"; reg = <0x11400000 0x1000>; - interrupts = <0 47 0>; + interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>; }; pinctrl_1: pinctrl@11000000 { compatible = "samsung,exynos4210-pinctrl"; reg = <0x11000000 0x1000>; - interrupts = <0 46 0>; + interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>; wakup_eint: wakeup-interrupt-controller { compatible = "samsung,exynos4210-wakeup-eint"; interrupt-parent = <&gic>; - interrupts = <0 32 0>; + interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>; }; }; @@ -182,7 +182,7 @@ g2d: g2d@12800000 { compatible = "samsung,s5pv210-g2d"; reg = <0x12800000 0x1000>; - interrupts = <0 89 0>; + interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>; clocks = <&clock CLK_SCLK_FIMG2D>, <&clock CLK_G2D>; clock-names = "sclk_fimg2d", "fimg2d"; power-domains = <&pd_lcd0>; @@ -424,10 +424,22 @@ &combiner { samsung,combiner-nr = <16>; - interrupts = <0 0 0>, <0 1 0>, <0 2 0>, <0 3 0>, - <0 4 0>, <0 5 0>, <0 6 0>, <0 7 0>, - <0 8 0>, <0 9 0>, <0 10 0>, <0 11 0>, - <0 12 0>, <0 13 0>, <0 14 0>, <0 15 0>; + interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>; }; &mdma1 { diff --git a/arch/arm/boot/dts/exynos4412-itop-elite.dts b/arch/arm/boot/dts/exynos4412-itop-elite.dts new file mode 100644 index 000000000000..76d87f397178 --- /dev/null +++ b/arch/arm/boot/dts/exynos4412-itop-elite.dts @@ -0,0 +1,240 @@ +/* + * TOPEET's Exynos4412 based itop board device tree source + * + * Copyright (c) 2016 SUMOMO Computer Association + * https://www.sumomo.mobi + * Randy Li <ayaka@soulik.info> + * + * Device tree source file for TOPEET iTop Exynos 4412 core board + * which is based on Samsung's Exynos4412 SoC. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +/dts-v1/; +#include <dt-bindings/pwm/pwm.h> +#include <dt-bindings/sound/samsung-i2s.h> +#include "exynos4412-itop-scp-core.dtsi" + +/ { + model = "TOPEET iTop 4412 Elite board based on Exynos4412"; + compatible = "topeet,itop4412-elite", "samsung,exynos4412", "samsung,exynos4"; + + chosen { + bootargs = "root=/dev/mmcblk0p2 rw rootfstype=ext4 rootdelay=1 rootwait"; + stdout-path = "serial2:115200n8"; + }; + + leds { + compatible = "gpio-leds"; + + led2 { + label = "red:system"; + gpios = <&gpx1 0 GPIO_ACTIVE_HIGH>; + default-state = "off"; + linux,default-trigger = "heartbeat"; + }; + + led3 { + label = "red:user"; + gpios = <&gpk1 1 GPIO_ACTIVE_HIGH>; + default-state = "off"; + }; + }; + + gpio-keys { + compatible = "gpio-keys"; + + home { + label = "GPIO Key Home"; + linux,code = <KEY_HOME>; + gpios = <&gpx1 1 GPIO_ACTIVE_LOW>; + }; + + back { + label = "GPIO Key Back"; + linux,code = <KEY_BACK>; + gpios = <&gpx1 2 GPIO_ACTIVE_LOW>; + }; + + sleep { + label = "GPIO Key Sleep"; + linux,code = <KEY_POWER>; + gpios = <&gpx3 3 GPIO_ACTIVE_LOW>; + }; + + vol-up { + label = "GPIO Key Vol+"; + linux,code = <KEY_UP>; + gpios = <&gpx2 1 GPIO_ACTIVE_LOW>; + }; + + vol-down { + label = "GPIO Key Vol-"; + linux,code = <KEY_DOWN>; + gpios = <&gpx2 0 GPIO_ACTIVE_LOW>; + }; + }; + + sound { + compatible = "simple-audio-card"; + simple-audio-card,name = "wm-sound"; + + assigned-clocks = <&clock_audss EXYNOS_MOUT_AUDSS>, + <&clock_audss EXYNOS_MOUT_I2S>, + <&clock_audss EXYNOS_DOUT_SRP>, + <&clock_audss EXYNOS_DOUT_AUD_BUS>; + assigned-clock-parents = <&clock CLK_FOUT_EPLL>, + <&clock_audss EXYNOS_MOUT_AUDSS>; + assigned-clock-rates = <0>, + <0>, + <112896000>, + <11289600>; + + simple-audio-card,format = "i2s"; + simple-audio-card,bitclock-master = <&link0_codec>; + simple-audio-card,frame-master = <&link0_codec>; + + simple-audio-card,widgets = + "Microphone", "Mic Jack", + "Line", "Line In", + "Line", "Line Out", + "Speaker", "Speaker", + "Headphone", "Headphone Jack"; + simple-audio-card,routing = + "Headphone Jack", "HP_L", + "Headphone Jack", "HP_R", + "Speaker", "SPK_LP", + "Speaker", "SPK_LN", + "Speaker", "SPK_RP", + "Speaker", "SPK_RN", + "LINPUT1", "Mic Jack", + "LINPUT3", "Mic Jack", + "RINPUT1", "Mic Jack", + "RINPUT2", "Mic Jack"; + + simple-audio-card,cpu { + sound-dai = <&i2s0 0>; + }; + + link0_codec: simple-audio-card,codec { + sound-dai = <&codec>; + clocks = <&i2s0 CLK_I2S_CDCLK>; + system-clock-frequency = <11289600>; + }; + }; + + beep { + compatible = "pwm-beeper"; + pwms = <&pwm 0 4000000 PWM_POLARITY_INVERTED>; + }; + + camera: camera { + pinctrl-0 = <&cam_port_a_clk_active>; + pinctrl-names = "default"; + status = "okay"; + assigned-clocks = <&clock CLK_MOUT_CAM0>; + assigned-clock-parents = <&clock CLK_XUSBXTI>; + }; +}; + +&adc { + vdd-supply = <&ldo3_reg>; + status = "okay"; +}; + +&ehci { + status = "okay"; + /* In order to reset USB ethernet */ + samsung,vbus-gpio = <&gpc0 1 GPIO_ACTIVE_HIGH>; + + port@0 { + status = "okay"; + }; + + port@2 { + status = "okay"; + }; +}; + +&exynos_usbphy { + status = "okay"; +}; + +&fimc_0 { + status = "okay"; + assigned-clocks = <&clock CLK_MOUT_FIMC0>, + <&clock CLK_SCLK_FIMC0>; + assigned-clock-parents = <&clock CLK_MOUT_MPLL_USER_T>; + assigned-clock-rates = <0>, <176000000>; +}; + +&hsotg { + dr_mode = "peripheral"; + status = "okay"; +}; + +&i2c_4 { + samsung,i2c-sda-delay = <100>; + samsung,i2c-slave-addr = <0x10>; + samsung,i2c-max-bus-freq = <100000>; + pinctrl-0 = <&i2c4_bus>; + pinctrl-names = "default"; + status = "okay"; + + codec: wm8960@1a { + compatible = "wlf,wm8960"; + reg = <0x1a>; + clocks = <&pmu_system_controller 0>; + clock-names = "MCLK1"; + wlf,shared-lrclk; + #sound-dai-cells = <0>; + }; +}; + +&i2s0 { + pinctrl-0 = <&i2s0_bus>; + pinctrl-names = "default"; + status = "okay"; + clocks = <&clock_audss EXYNOS_I2S_BUS>, + <&clock_audss EXYNOS_DOUT_AUD_BUS>, + <&clock_audss EXYNOS_SCLK_I2S>; + clock-names = "iis", "i2s_opclk0", "i2s_opclk1"; +}; + +&pinctrl_1 { + ether-reset { + samsung,pins = "gpc0-1"; + samsung,pin-function = <EXYNOS_PIN_FUNC_INPUT>; + samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>; + samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>; + }; +}; + +&pwm { + status = "okay"; + pinctrl-0 = <&pwm0_out>; + pinctrl-names = "default"; + samsung,pwm-outputs = <0>; +}; + +&sdhci_2 { + bus-width = <4>; + pinctrl-0 = <&sd2_clk &sd2_cmd &sd2_bus4>; + pinctrl-names = "default"; + cd-gpio = <&gpx0 7 GPIO_ACTIVE_LOW>; + cap-sd-highspeed; + vmmc-supply = <&ldo23_reg>; + vqmmc-supply = <&ldo17_reg>; + status = "okay"; +}; + +&serial_1 { + status = "okay"; +}; + +&serial_2 { + status = "okay"; +}; diff --git a/arch/arm/boot/dts/exynos4412-itop-scp-core.dtsi b/arch/arm/boot/dts/exynos4412-itop-scp-core.dtsi new file mode 100644 index 000000000000..a36cd36a26b8 --- /dev/null +++ b/arch/arm/boot/dts/exynos4412-itop-scp-core.dtsi @@ -0,0 +1,501 @@ +/* + * TOPEET's Exynos4412 based itop board device tree source + * + * Copyright (c) 2016 SUMOMO Computer Association + * https://www.sumomo.mobi + * Randy Li <ayaka@soulik.info> + * + * Device tree source file for TOPEET iTop Exynos 4412 SCP package core + * board which is based on Samsung's Exynos4412 SoC. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#include <dt-bindings/clock/samsung,s2mps11.h> +#include <dt-bindings/gpio/gpio.h> +#include <dt-bindings/input/input.h> +#include "exynos4412.dtsi" +#include "exynos4412-ppmu-common.dtsi" +#include "exynos-mfc-reserved-memory.dtsi" + +/ { + memory@40000000 { + device_type = "memory"; + reg = <0x40000000 0x40000000>; + }; + + firmware@0203F000 { + compatible = "samsung,secure-firmware"; + reg = <0x0203F000 0x1000>; + }; + + fixed-rate-clocks { + xxti { + compatible = "samsung,clock-xxti"; + clock-frequency = <0>; + }; + + xusbxti { + compatible = "samsung,clock-xusbxti"; + clock-frequency = <24000000>; + }; + }; + + thermal-zones { + cpu_thermal: cpu-thermal { + cooling-maps { + map0 { + /* Corresponds to 800MHz at freq_table */ + cooling-device = <&cpu0 7 7>; + }; + map1 { + /* Corresponds to 200MHz at freq_table */ + cooling-device = <&cpu0 13 13>; + }; + }; + }; + }; + + usb-hub { + compatible = "smsc,usb3503a"; + reset-gpios = <&gpm2 4 GPIO_ACTIVE_LOW>; + connect-gpios = <&gpm3 3 GPIO_ACTIVE_HIGH>; + intn-gpios = <&gpx2 3 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&hsic_reset>; + }; +}; + +&bus_dmc { + devfreq-events = <&ppmu_dmc0_3>, <&ppmu_dmc1_3>; + vdd-supply = <&buck1_reg>; + status = "okay"; +}; + +&bus_acp { + devfreq = <&bus_dmc>; + status = "okay"; +}; + +&bus_c2c { + devfreq = <&bus_dmc>; + status = "okay"; +}; + +&bus_leftbus { + devfreq-events = <&ppmu_leftbus_3>, <&ppmu_rightbus_3>; + vdd-supply = <&buck3_reg>; + status = "okay"; +}; + +&bus_rightbus { + devfreq = <&bus_leftbus>; + status = "okay"; +}; + +&bus_fsys { + devfreq = <&bus_leftbus>; + status = "okay"; +}; + +&bus_peri { + devfreq = <&bus_leftbus>; + status = "okay"; +}; + +&bus_mfc { + devfreq = <&bus_leftbus>; + status = "okay"; +}; + +&cpu0 { + cpu0-supply = <&buck2_reg>; +}; + +&hsotg { + vusb_d-supply = <&ldo15_reg>; + vusb_a-supply = <&ldo12_reg>; +}; + +&i2c_1 { + #address-cells = <1>; + #size-cells = <0>; + samsung,i2c-sda-delay = <100>; + samsung,i2c-max-bus-freq = <400000>; + pinctrl-0 = <&i2c1_bus>; + pinctrl-names = "default"; + status = "okay"; + + s5m8767: s5m8767-pmic@66 { + compatible = "samsung,s5m8767-pmic"; + reg = <0x66>; + + s5m8767,pmic-buck-default-dvs-idx = <3>; + + s5m8767,pmic-buck-dvs-gpios = <&gpb 5 GPIO_ACTIVE_HIGH>, + <&gpb 6 GPIO_ACTIVE_HIGH>, + <&gpb 7 GPIO_ACTIVE_HIGH>; + + s5m8767,pmic-buck-ds-gpios = <&gpm3 5 GPIO_ACTIVE_HIGH>, + <&gpm3 6 GPIO_ACTIVE_HIGH>, + <&gpm3 7 GPIO_ACTIVE_HIGH>; + + /* VDD_ARM */ + s5m8767,pmic-buck2-dvs-voltage = <1356250>, <1300000>, + <1243750>, <1118750>, + <1068750>, <1012500>, + <956250>, <900000>; + /* VDD_INT */ + s5m8767,pmic-buck3-dvs-voltage = <1000000>, <1000000>, + <925000>, <925000>, + <887500>, <887500>, + <850000>, <850000>; + /* VDD_G3D */ + s5m8767,pmic-buck4-dvs-voltage = <1081250>, <1081250>, + <1025000>, <950000>, + <918750>, <900000>, + <875000>, <831250>; + + regulators { + ldo1_reg: LDO1 { + regulator-name = "VDD_ALIVE"; + regulator-min-microvolt = <1100000>; + regulator-max-microvolt = <1100000>; + regulator-always-on; + regulator-boot-on; + op_mode = <1>; /* Normal Mode */ + }; + + /* SCP uses 1.5v, POP uses 1.2v */ + ldo2_reg: LDO2 { + regulator-name = "VDDQ_M12"; + regulator-min-microvolt = <1500000>; + regulator-max-microvolt = <1500000>; + regulator-always-on; + regulator-boot-on; + op_mode = <1>; /* Normal Mode */ + }; + + ldo3_reg: LDO3 { + regulator-name = "VDDIOAP_18"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + op_mode = <1>; /* Normal Mode */ + }; + + ldo4_reg: LDO4 { + regulator-name = "VDDQ_PRE"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + op_mode = <1>; /* Normal Mode */ + }; + + ldo5_reg: LDO5 { + regulator-name = "VDD_LDO5"; + op_mode = <0>; /* Always off Mode */ + }; + + ldo6_reg: LDO6 { + regulator-name = "VDD10_MPLL"; + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <1000000>; + regulator-always-on; + op_mode = <1>; /* Normal Mode */ + }; + + ldo7_reg: LDO7 { + regulator-name = "VDD10_XPLL"; + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <1000000>; + regulator-always-on; + op_mode = <1>; /* Normal Mode */ + }; + + ldo8_reg: LDO8 { + regulator-name = "VDD10_MIPI"; + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <1000000>; + op_mode = <1>; /* Normal Mode */ + }; + + ldo9_reg: LDO9 { + regulator-name = "VDD33_LCD"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + op_mode = <1>; /* Normal Mode */ + }; + + ldo10_reg: LDO10 { + regulator-name = "VDD18_MIPI"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + op_mode = <1>; /* Normal Mode */ + }; + + ldo11_reg: LDO11 { + regulator-name = "VDD18_ABB1"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + op_mode = <1>; /* Normal Mode */ + }; + + ldo12_reg: LDO12 { + regulator-name = "VDD33_UOTG"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + op_mode = <1>; /* Normal Mode */ + }; + + ldo13_reg: LDO13 { + regulator-name = "VDDIOPERI_18"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + op_mode = <1>; /* Normal Mode */ + }; + + ldo14_reg: LDO14 { + regulator-name = "VDD18_ABB02"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + op_mode = <1>; /* Normal Mode */ + }; + + ldo15_reg: LDO15 { + regulator-name = "VDD10_USH"; + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <1000000>; + regulator-always-on; + op_mode = <1>; /* Normal Mode */ + }; + + ldo16_reg: LDO16 { + regulator-name = "VDD18_HSIC"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + op_mode = <1>; /* Normal Mode */ + }; + + ldo17_reg: LDO17 { + regulator-name = "VDDIOAP_MMC012_28"; + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <2800000>; + op_mode = <1>; /* Normal Mode */ + }; + + /* Used by HSIC */ + ldo18_reg: LDO18 { + regulator-name = "VDDIOPERI_28"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + op_mode = <1>; /* Normal Mode */ + }; + + ldo19_reg: LDO19 { + regulator-name = "VDD_LDO19"; + op_mode = <0>; /* Always off Mode */ + }; + + ldo20_reg: LDO20 { + regulator-name = "VDD28_CAM"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <2800000>; + op_mode = <1>; /* Normal Mode */ + }; + + ldo21_reg: LDO21 { + regulator-name = "VDD28_AF"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <2800000>; + op_mode = <1>; /* Normal Mode */ + }; + + ldo22_reg: LDO22 { + regulator-name = "VDDA28_2M"; + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <2800000>; + op_mode = <1>; /* Normal Mode */ + }; + + ldo23_reg: LDO23 { + regulator-name = "VDD28_TF"; + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <2800000>; + op_mode = <1>; /* Normal Mode */ + }; + + ldo24_reg: LDO24 { + regulator-name = "VDD33_A31"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + op_mode = <1>; /* Normal Mode */ + }; + + ldo25_reg: LDO25 { + regulator-name = "VDD18_CAM"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + op_mode = <1>; /* Normal Mode */ + }; + + ldo26_reg: LDO26 { + regulator-name = "VDD18_A31"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + op_mode = <1>; /* Normal Mode */ + }; + + ldo27_reg: LDO27 { + regulator-name = "GPS_1V8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + op_mode = <1>; /* Normal Mode */ + }; + + ldo28_reg: LDO28 { + regulator-name = "DVDD12"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + op_mode = <1>; /* Normal Mode */ + }; + + buck1_reg: BUCK1 { + regulator-name = "vdd_mif"; + regulator-min-microvolt = <850000>; + regulator-max-microvolt = <1100000>; + regulator-always-on; + regulator-boot-on; + op_mode = <1>; /* Normal Mode */ + }; + + buck2_reg: BUCK2 { + regulator-name = "vdd_arm"; + regulator-min-microvolt = <850000>; + regulator-max-microvolt = <1456250>; + regulator-always-on; + regulator-boot-on; + op_mode = <1>; /* Normal Mode */ + }; + + buck3_reg: BUCK3 { + regulator-name = "vdd_int"; + regulator-min-microvolt = <875000>; + regulator-max-microvolt = <1200000>; + regulator-always-on; + regulator-boot-on; + op_mode = <1>; /* Normal Mode */ + }; + + buck4_reg: BUCK4 { + regulator-name = "vdd_g3d"; + regulator-min-microvolt = <750000>; + regulator-max-microvolt = <1500000>; + regulator-always-on; + regulator-boot-on; + op_mode = <1>; /* Normal Mode */ + }; + + buck5_reg: BUCK5 { + regulator-name = "vdd_m12"; + regulator-min-microvolt = <750000>; + regulator-max-microvolt = <1500000>; + regulator-always-on; + regulator-boot-on; + op_mode = <1>; /* Normal Mode */ + }; + + buck6_reg: BUCK6 { + regulator-name = "vdd12_5m"; + regulator-min-microvolt = <750000>; + regulator-max-microvolt = <1500000>; + regulator-always-on; + regulator-boot-on; + op_mode = <1>; /* Normal Mode */ + }; + + buck7_reg: BUCK7 { + regulator-name = "pvdd_buck7"; + regulator-min-microvolt = <750000>; + regulator-max-microvolt = <2000000>; + regulator-boot-on; + regulator-always-on; + op_mode = <1>; /* Normal Mode */ + }; + + buck8_reg: BUCK8 { + regulator-name = "pvdd_buck8"; + regulator-min-microvolt = <750000>; + regulator-max-microvolt = <1500000>; + regulator-boot-on; + regulator-always-on; + op_mode = <1>; /* Normal Mode */ + }; + + buck9_reg: BUCK9 { + regulator-name = "vddf28_emmc"; + regulator-min-microvolt = <750000>; + regulator-max-microvolt = <3000000>; + op_mode = <1>; /* Normal Mode */ + }; + }; + + s5m8767_osc: clocks { + #clock-cells = <1>; + clock-output-names = "s5m8767_ap", + "s5m8767_cp", "s5m8767_bt"; + }; + + }; +}; + +&mfc { + status = "okay"; +}; + +&mshc_0 { + pinctrl-0 = <&sd4_clk &sd4_cmd &sd4_bus4 &sd4_bus8>; + pinctrl-names = "default"; + status = "okay"; + vmmc-supply = <&buck9_reg>; + num-slots = <1>; + broken-cd; + card-detect-delay = <200>; + samsung,dw-mshc-ciu-div = <3>; + samsung,dw-mshc-sdr-timing = <2 3>; + samsung,dw-mshc-ddr-timing = <1 2>; + bus-width = <8>; + cap-mmc-highspeed; +}; + +&pinctrl_1 { + hsic_reset: hsic-reset { + samsung,pins = "gpm2-4"; + samsung,pin-function = <EXYNOS_PIN_FUNC_INPUT>; + samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>; + samsung,pin-drv = <EXYNOS4_PIN_DRV_LV4>; + }; +}; + +&rtc { + status = "okay"; + clocks = <&clock CLK_RTC>, <&s5m8767_osc S2MPS11_CLK_AP>; + clock-names = "rtc", "rtc_src"; +}; + +&tmu { + vtmu-supply = <&ldo16_reg>; + status = "okay"; +}; + +&watchdog { + status = "okay"; +}; diff --git a/arch/arm/boot/dts/exynos4415-pinctrl.dtsi b/arch/arm/boot/dts/exynos4415-pinctrl.dtsi deleted file mode 100644 index 76cfd872ead3..000000000000 --- a/arch/arm/boot/dts/exynos4415-pinctrl.dtsi +++ /dev/null @@ -1,575 +0,0 @@ -/* - * Samsung's Exynos4415 SoCs pin-mux and pin-config device tree source - * - * Copyright (c) 2014 Samsung Electronics Co., Ltd. - * - * Samsung's Exynos4415 SoCs pin-mux and pin-config optiosn are listed as device - * tree nodes are listed in this file. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. -*/ - -#include <dt-bindings/pinctrl/samsung.h> - -&pinctrl_0 { - gpa0: gpa0 { - gpio-controller; - #gpio-cells = <2>; - - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpa1: gpa1 { - gpio-controller; - #gpio-cells = <2>; - - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpb: gpb { - gpio-controller; - #gpio-cells = <2>; - - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpc0: gpc0 { - gpio-controller; - #gpio-cells = <2>; - - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpc1: gpc1 { - gpio-controller; - #gpio-cells = <2>; - - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpd0: gpd0 { - gpio-controller; - #gpio-cells = <2>; - - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpd1: gpd1 { - gpio-controller; - #gpio-cells = <2>; - - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpf0: gpf0 { - gpio-controller; - #gpio-cells = <2>; - - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpf1: gpf1 { - gpio-controller; - #gpio-cells = <2>; - - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpf2: gpf2 { - gpio-controller; - #gpio-cells = <2>; - - interrupt-controller; - #interrupt-cells = <2>; - }; - - uart0_data: uart0-data { - samsung,pins = "gpa0-0", "gpa0-1"; - samsung,pin-function = <EXYNOS_PIN_FUNC_2>; - samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>; - samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>; - }; - - uart0_fctl: uart0-fctl { - samsung,pins = "gpa0-2", "gpa0-3"; - samsung,pin-function = <EXYNOS_PIN_FUNC_2>; - samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>; - samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>; - }; - - uart1_data: uart1-data { - samsung,pins = "gpa0-4", "gpa0-5"; - samsung,pin-function = <EXYNOS_PIN_FUNC_2>; - samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>; - samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>; - }; - - uart1_fctl: uart1-fctl { - samsung,pins = "gpa0-6", "gpa0-7"; - samsung,pin-function = <EXYNOS_PIN_FUNC_2>; - samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>; - samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>; - }; - - uart2_data: uart2-data { - samsung,pins = "gpa1-0", "gpa1-1"; - samsung,pin-function = <EXYNOS_PIN_FUNC_2>; - samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>; - samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>; - }; - - uart2_fctl: uart2-fctl { - samsung,pins = "gpa1-2", "gpa1-3"; - samsung,pin-function = <EXYNOS_PIN_FUNC_2>; - samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>; - samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>; - }; - - uart3_data: uart3-data { - samsung,pins = "gpa1-4", "gpa1-5"; - samsung,pin-function = <EXYNOS_PIN_FUNC_2>; - samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>; - samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>; - }; - - i2c2_bus: i2c2-bus { - samsung,pins = "gpa0-6", "gpa0-7"; - samsung,pin-function = <EXYNOS_PIN_FUNC_3>; - samsung,pin-pud = <EXYNOS_PIN_PULL_UP>; - samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>; - }; - - i2c3_bus: i2c3-bus { - samsung,pins = "gpa1-2", "gpa1-3"; - samsung,pin-function = <EXYNOS_PIN_FUNC_3>; - samsung,pin-pud = <EXYNOS_PIN_PULL_UP>; - samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>; - }; - - spi0_bus: spi0-bus { - samsung,pins = "gpb-0", "gpb-2", "gpb-3"; - samsung,pin-function = <EXYNOS_PIN_FUNC_2>; - samsung,pin-pud = <EXYNOS_PIN_PULL_UP>; - samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>; - }; - - i2c4_bus: i2c4-bus { - samsung,pins = "gpb-0", "gpb-1"; - samsung,pin-function = <EXYNOS_PIN_FUNC_3>; - samsung,pin-pud = <EXYNOS_PIN_PULL_UP>; - samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>; - }; - - spi1_bus: spi1-bus { - samsung,pins = "gpb-4", "gpb-6", "gpb-7"; - samsung,pin-function = <EXYNOS_PIN_FUNC_2>; - samsung,pin-pud = <EXYNOS_PIN_PULL_UP>; - samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>; - }; - - i2c5_bus: i2c5-bus { - samsung,pins = "gpb-2", "gpb-3"; - samsung,pin-function = <EXYNOS_PIN_FUNC_3>; - samsung,pin-pud = <EXYNOS_PIN_PULL_UP>; - samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>; - }; - - i2s1_bus: i2s1-bus { - samsung,pins = "gpc0-0", "gpc0-1", "gpc0-2", "gpc0-3", - "gpc0-4"; - samsung,pin-function = <EXYNOS_PIN_FUNC_2>; - samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>; - samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>; - }; - - i2s2_bus: i2s2-bus { - samsung,pins = "gpc1-0", "gpc1-1", "gpc1-2", "gpc1-3", - "gpc1-4"; - samsung,pin-function = <EXYNOS_PIN_FUNC_2>; - samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>; - samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>; - }; - - pcm2_bus: pcm2-bus { - samsung,pins = "gpc1-0", "gpc1-1", "gpc1-2", "gpc1-3", - "gpc1-4"; - samsung,pin-function = <EXYNOS_PIN_FUNC_3>; - samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>; - samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>; - }; - - i2c6_bus: i2c6-bus { - samsung,pins = "gpc1-3", "gpc1-4"; - samsung,pin-function = <EXYNOS_PIN_FUNC_4>; - samsung,pin-pud = <EXYNOS_PIN_PULL_UP>; - samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>; - }; - - spi2_bus: spi2-bus { - samsung,pins = "gpc1-1", "gpc1-3", "gpc1-4"; - samsung,pin-function = <EXYNOS_PIN_FUNC_5>; - samsung,pin-pud = <EXYNOS_PIN_PULL_UP>; - samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>; - }; - - pwm0_out: pwm0-out { - samsung,pins = "gpd0-0"; - samsung,pin-function = <EXYNOS_PIN_FUNC_2>; - samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>; - samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>; - }; - - pwm1_out: pwm1-out { - samsung,pins = "gpd0-1"; - samsung,pin-function = <EXYNOS_PIN_FUNC_2>; - samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>; - samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>; - }; - - pwm2_out: pwm2-out { - samsung,pins = "gpd0-2"; - samsung,pin-function = <EXYNOS_PIN_FUNC_2>; - samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>; - samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>; - }; - - pwm3_out: pwm3-out { - samsung,pins = "gpd0-3"; - samsung,pin-function = <EXYNOS_PIN_FUNC_2>; - samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>; - samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>; - }; - - i2c7_bus: i2c7-bus { - samsung,pins = "gpd0-2", "gpd0-3"; - samsung,pin-function = <EXYNOS_PIN_FUNC_3>; - samsung,pin-pud = <EXYNOS_PIN_PULL_UP>; - samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>; - }; - - i2c0_bus: i2c0-bus { - samsung,pins = "gpd1-0", "gpd1-1"; - samsung,pin-function = <EXYNOS_PIN_FUNC_2>; - samsung,pin-pud = <EXYNOS_PIN_PULL_UP>; - samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>; - }; - - i2c1_bus: i2c1-bus { - samsung,pins = "gpd1-2", "gpd1-3"; - samsung,pin-function = <EXYNOS_PIN_FUNC_2>; - samsung,pin-pud = <EXYNOS_PIN_PULL_UP>; - samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>; - }; -}; - -&pinctrl_1 { - gpk0: gpk0 { - gpio-controller; - #gpio-cells = <2>; - - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpk1: gpk1 { - gpio-controller; - #gpio-cells = <2>; - - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpk2: gpk2 { - gpio-controller; - #gpio-cells = <2>; - - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpk3: gpk3 { - gpio-controller; - #gpio-cells = <2>; - - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpl0: gpl0 { - gpio-controller; - #gpio-cells = <2>; - - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpm0: gpm0 { - gpio-controller; - #gpio-cells = <2>; - - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpm1: gpm1 { - gpio-controller; - #gpio-cells = <2>; - - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpm2: gpm2 { - gpio-controller; - #gpio-cells = <2>; - - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpm3: gpm3 { - gpio-controller; - #gpio-cells = <2>; - - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpm4: gpm4 { - gpio-controller; - #gpio-cells = <2>; - - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpx0: gpx0 { - gpio-controller; - #gpio-cells = <2>; - - interrupt-controller; - interrupt-parent = <&gic>; - interrupts = <0 32 0>, <0 33 0>, <0 34 0>, <0 35 0>, - <0 36 0>, <0 37 0>, <0 38 0>, <0 39 0>; - #interrupt-cells = <2>; - }; - - gpx1: gpx1 { - gpio-controller; - #gpio-cells = <2>; - - interrupt-controller; - interrupt-parent = <&gic>; - interrupts = <0 40 0>, <0 41 0>, <0 42 0>, <0 43 0>, - <0 44 0>, <0 45 0>, <0 46 0>, <0 47 0>; - #interrupt-cells = <2>; - }; - - gpx2: gpx2 { - gpio-controller; - #gpio-cells = <2>; - - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpx3: gpx3 { - gpio-controller; - #gpio-cells = <2>; - - interrupt-controller; - #interrupt-cells = <2>; - }; - - sd0_clk: sd0-clk { - samsung,pins = "gpk0-0"; - samsung,pin-function = <EXYNOS_PIN_FUNC_2>; - samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>; - samsung,pin-drv = <EXYNOS4_PIN_DRV_LV4>; - }; - - sd0_cmd: sd0-cmd { - samsung,pins = "gpk0-1"; - samsung,pin-function = <EXYNOS_PIN_FUNC_2>; - samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>; - samsung,pin-drv = <EXYNOS4_PIN_DRV_LV4>; - }; - - sd0_cd: sd0-cd { - samsung,pins = "gpk0-2"; - samsung,pin-function = <EXYNOS_PIN_FUNC_2>; - samsung,pin-pud = <EXYNOS_PIN_PULL_UP>; - samsung,pin-drv = <EXYNOS4_PIN_DRV_LV4>; - }; - - sd0_rdqs: sd0-rdqs { - samsung,pins = "gpk0-7"; - samsung,pin-function = <EXYNOS_PIN_FUNC_2>; - samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>; - samsung,pin-drv = <EXYNOS4_PIN_DRV_LV4>; - }; - - sd0_bus1: sd0-bus-width1 { - samsung,pins = "gpk0-3"; - samsung,pin-function = <EXYNOS_PIN_FUNC_2>; - samsung,pin-pud = <EXYNOS_PIN_PULL_UP>; - samsung,pin-drv = <EXYNOS4_PIN_DRV_LV4>; - }; - - sd0_bus4: sd0-bus-width4 { - samsung,pins = "gpk0-4", "gpk0-5", "gpk0-6"; - samsung,pin-function = <EXYNOS_PIN_FUNC_2>; - samsung,pin-pud = <EXYNOS_PIN_PULL_UP>; - samsung,pin-drv = <EXYNOS4_PIN_DRV_LV4>; - }; - - sd0_bus8: sd0-bus-width8 { - samsung,pins = "gpl0-0", "gpl0-1", "gpl0-2", "gpl0-3"; - samsung,pin-function = <EXYNOS_PIN_FUNC_2>; - samsung,pin-pud = <EXYNOS_PIN_PULL_UP>; - samsung,pin-drv = <EXYNOS4_PIN_DRV_LV4>; - }; - - sd1_clk: sd1-clk { - samsung,pins = "gpk1-0"; - samsung,pin-function = <EXYNOS_PIN_FUNC_2>; - samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>; - samsung,pin-drv = <EXYNOS4_PIN_DRV_LV4>; - }; - - sd1_cmd: sd1-cmd { - samsung,pins = "gpk1-1"; - samsung,pin-function = <EXYNOS_PIN_FUNC_2>; - samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>; - samsung,pin-drv = <EXYNOS4_PIN_DRV_LV4>; - }; - - sd1_cd: sd1-cd { - samsung,pins = "gpk1-2"; - samsung,pin-function = <EXYNOS_PIN_FUNC_2>; - samsung,pin-pud = <EXYNOS_PIN_PULL_UP>; - samsung,pin-drv = <EXYNOS4_PIN_DRV_LV4>; - }; - - sd1_bus1: sd1-bus-width1 { - samsung,pins = "gpk1-3"; - samsung,pin-function = <EXYNOS_PIN_FUNC_2>; - samsung,pin-pud = <EXYNOS_PIN_PULL_UP>; - samsung,pin-drv = <EXYNOS4_PIN_DRV_LV4>; - }; - - sd1_bus4: sd1-bus-width4 { - samsung,pins = "gpk1-4", "gpk1-5", "gpk1-6"; - samsung,pin-function = <EXYNOS_PIN_FUNC_2>; - samsung,pin-pud = <EXYNOS_PIN_PULL_UP>; - samsung,pin-drv = <EXYNOS4_PIN_DRV_LV4>; - }; - - sd2_clk: sd2-clk { - samsung,pins = "gpk2-0"; - samsung,pin-function = <EXYNOS_PIN_FUNC_2>; - samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>; - samsung,pin-drv = <EXYNOS4_PIN_DRV_LV4>; - }; - - sd2_cmd: sd2-cmd { - samsung,pins = "gpk2-1"; - samsung,pin-function = <EXYNOS_PIN_FUNC_2>; - samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>; - samsung,pin-drv = <EXYNOS4_PIN_DRV_LV4>; - }; - - sd2_cd: sd2-cd { - samsung,pins = "gpk2-2"; - samsung,pin-function = <EXYNOS_PIN_FUNC_2>; - samsung,pin-pud = <EXYNOS_PIN_PULL_UP>; - samsung,pin-drv = <EXYNOS4_PIN_DRV_LV4>; - }; - - sd2_bus1: sd2-bus-width1 { - samsung,pins = "gpk2-3"; - samsung,pin-function = <EXYNOS_PIN_FUNC_2>; - samsung,pin-pud = <EXYNOS_PIN_PULL_UP>; - samsung,pin-drv = <EXYNOS4_PIN_DRV_LV4>; - }; - - sd2_bus4: sd2-bus-width4 { - samsung,pins = "gpk2-4", "gpk2-5", "gpk2-6"; - samsung,pin-function = <EXYNOS_PIN_FUNC_2>; - samsung,pin-pud = <EXYNOS_PIN_PULL_UP>; - samsung,pin-drv = <EXYNOS4_PIN_DRV_LV4>; - }; - - cam_port_b_io: cam-port-b-io { - samsung,pins = "gpm0-0", "gpm0-1", "gpm0-2", "gpm0-3", - "gpm0-4", "gpm0-5", "gpm0-6", "gpm0-7", - "gpm1-0", "gpm1-1", "gpm2-0", "gpm2-1"; - samsung,pin-function = <EXYNOS_PIN_FUNC_3>; - samsung,pin-pud = <EXYNOS_PIN_PULL_UP>; - samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>; - }; - - cam_port_b_clk_active: cam-port-b-clk-active { - samsung,pins = "gpm2-2"; - samsung,pin-function = <EXYNOS_PIN_FUNC_3>; - samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>; - samsung,pin-drv = <EXYNOS4_PIN_DRV_LV4>; - }; - - cam_port_b_clk_idle: cam-port-b-clk-idle { - samsung,pins = "gpm2-2"; - samsung,pin-function = <EXYNOS_PIN_FUNC_INPUT>; - samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>; - samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>; - }; - - fimc_is_i2c0: fimc-is-i2c0 { - samsung,pins = "gpm4-0", "gpm4-1"; - samsung,pin-function = <EXYNOS_PIN_FUNC_2>; - samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>; - samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>; - }; - - fimc_is_i2c1: fimc-is-i2c1 { - samsung,pins = "gpm4-2", "gpm4-3"; - samsung,pin-function = <EXYNOS_PIN_FUNC_2>; - samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>; - samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>; - }; - - fimc_is_uart: fimc-is-uart { - samsung,pins = "gpm3-5", "gpm3-7"; - samsung,pin-function = <EXYNOS_PIN_FUNC_3>; - samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>; - samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>; - }; -}; - -&pinctrl_2 { - gpz: gpz { - gpio-controller; - #gpio-cells = <2>; - - interrupt-controller; - #interrupt-cells = <2>; - }; - - i2s0_bus: i2s0-bus { - samsung,pins = "gpz-0", "gpz-1", "gpz-2", "gpz-3", - "gpz-4", "gpz-5", "gpz-6"; - samsung,pin-function = <EXYNOS_PIN_FUNC_2>; - samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>; - samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>; - }; -}; diff --git a/arch/arm/boot/dts/exynos4415.dtsi b/arch/arm/boot/dts/exynos4415.dtsi deleted file mode 100644 index 3c40f8a956dd..000000000000 --- a/arch/arm/boot/dts/exynos4415.dtsi +++ /dev/null @@ -1,650 +0,0 @@ -/* - * Samsung's Exynos4415 SoC device tree source - * - * Copyright (c) 2014 Samsung Electronics Co., Ltd. - * - * Samsung's Exynos4415 SoC device nodes are listed in this file. Exynos4415 - * based board files can include this file and provide values for board - * specific bindings. - * - * Note: This file does not include device nodes for all the controllers in - * Exynos4415 SoC. As device tree coverage for Exynos4415 increases, additional - * nodes can be added to this file. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - */ - -#include <dt-bindings/clock/exynos4415.h> -#include <dt-bindings/clock/exynos-audss-clk.h> - -/ { - compatible = "samsung,exynos4415"; - interrupt-parent = <&gic>; - #address-cells = <1>; - #size-cells = <1>; - - aliases { - pinctrl0 = &pinctrl_0; - pinctrl1 = &pinctrl_1; - pinctrl2 = &pinctrl_2; - mshc0 = &mshc_0; - mshc1 = &mshc_1; - mshc2 = &mshc_2; - spi0 = &spi_0; - spi1 = &spi_1; - spi2 = &spi_2; - i2c0 = &i2c_0; - i2c1 = &i2c_1; - i2c2 = &i2c_2; - i2c3 = &i2c_3; - i2c4 = &i2c_4; - i2c5 = &i2c_5; - i2c6 = &i2c_6; - i2c7 = &i2c_7; - }; - - cpus { - #address-cells = <1>; - #size-cells = <0>; - - cpu0: cpu@a00 { - device_type = "cpu"; - compatible = "arm,cortex-a9"; - reg = <0xa00>; - clock-frequency = <1600000000>; - }; - - cpu1: cpu@a01 { - device_type = "cpu"; - compatible = "arm,cortex-a9"; - reg = <0xa01>; - clock-frequency = <1600000000>; - }; - - cpu2: cpu@a02 { - device_type = "cpu"; - compatible = "arm,cortex-a9"; - reg = <0xa02>; - clock-frequency = <1600000000>; - }; - - cpu3: cpu@a03 { - device_type = "cpu"; - compatible = "arm,cortex-a9"; - reg = <0xa03>; - clock-frequency = <1600000000>; - }; - }; - - soc: soc { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <1>; - ranges; - - sysram@02020000 { - compatible = "mmio-sram"; - reg = <0x02020000 0x50000>; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0 0x02020000 0x50000>; - - smp-sysram@0 { - compatible = "samsung,exynos4210-sysram"; - reg = <0x0 0x1000>; - }; - - smp-sysram@4f000 { - compatible = "samsung,exynos4210-sysram-ns"; - reg = <0x4f000 0x1000>; - }; - }; - - pinctrl_2: pinctrl@03860000 { - compatible = "samsung,exynos4415-pinctrl"; - reg = <0x03860000 0x1000>; - interrupts = <0 242 0>; - }; - - chipid@10000000 { - compatible = "samsung,exynos4210-chipid"; - reg = <0x10000000 0x100>; - }; - - sysreg_system_controller: syscon@10010000 { - compatible = "samsung,exynos4-sysreg", "syscon"; - reg = <0x10010000 0x400>; - }; - - pmu_system_controller: system-controller@10020000 { - compatible = "samsung,exynos4415-pmu", "syscon"; - reg = <0x10020000 0x4000>; - }; - - mipi_phy: video-phy@10020710 { - compatible = "samsung,s5pv210-mipi-video-phy"; - #phy-cells = <1>; - syscon = <&pmu_system_controller>; - }; - - pd_cam: cam-power-domain@10024000 { - compatible = "samsung,exynos4210-pd"; - reg = <0x10024000 0x20>; - #power-domain-cells = <0>; - }; - - pd_tv: tv-power-domain@10024020 { - compatible = "samsung,exynos4210-pd"; - reg = <0x10024020 0x20>; - #power-domain-cells = <0>; - }; - - pd_mfc: mfc-power-domain@10024040 { - compatible = "samsung,exynos4210-pd"; - reg = <0x10024040 0x20>; - #power-domain-cells = <0>; - }; - - pd_g3d: g3d-power-domain@10024060 { - compatible = "samsung,exynos4210-pd"; - reg = <0x10024060 0x20>; - #power-domain-cells = <0>; - }; - - pd_lcd0: lcd0-power-domain@10024080 { - compatible = "samsung,exynos4210-pd"; - reg = <0x10024080 0x20>; - #power-domain-cells = <0>; - }; - - pd_isp0: isp0-power-domain@100240A0 { - compatible = "samsung,exynos4210-pd"; - reg = <0x100240A0 0x20>; - #power-domain-cells = <0>; - }; - - pd_isp1: isp1-power-domain@100240E0 { - compatible = "samsung,exynos4210-pd"; - reg = <0x100240E0 0x20>; - #power-domain-cells = <0>; - }; - - cmu: clock-controller@10030000 { - compatible = "samsung,exynos4415-cmu"; - reg = <0x10030000 0x18000>; - #clock-cells = <1>; - }; - - rtc: rtc@10070000 { - compatible = "samsung,s3c6410-rtc"; - reg = <0x10070000 0x100>; - interrupts = <0 73 0>, <0 74 0>; - status = "disabled"; - }; - - mct@10050000 { - compatible = "samsung,exynos4210-mct"; - reg = <0x10050000 0x800>; - interrupts = <0 218 0>, <0 219 0>, <0 220 0>, <0 221 0>, - <0 223 0>, <0 226 0>, <0 227 0>, <0 228 0>; - clocks = <&cmu CLK_FIN_PLL>, <&cmu CLK_MCT>; - clock-names = "fin_pll", "mct"; - }; - - gic: interrupt-controller@10481000 { - compatible = "arm,cortex-a9-gic"; - #interrupt-cells = <3>; - interrupt-controller; - reg = <0x10481000 0x1000>, - <0x10482000 0x1000>, - <0x10484000 0x2000>, - <0x10486000 0x2000>; - interrupts = <1 9 0xf04>; - }; - - l2c: l2-cache-controller@10502000 { - compatible = "arm,pl310-cache"; - reg = <0x10502000 0x1000>; - cache-unified; - cache-level = <2>; - arm,tag-latency = <2 2 1>; - arm,data-latency = <3 2 1>; - arm,double-linefill = <1>; - arm,double-linefill-incr = <0>; - arm,double-linefill-wrap = <1>; - arm,prefetch-drop = <1>; - arm,prefetch-offset = <7>; - }; - - cmu_dmc: clock-controller@105C0000 { - compatible = "samsung,exynos4415-cmu-dmc"; - reg = <0x105C0000 0x3000>; - #clock-cells = <1>; - }; - - pinctrl_1: pinctrl@11000000 { - compatible = "samsung,exynos4415-pinctrl"; - reg = <0x11000000 0x1000>; - interrupts = <0 225 0>; - - wakeup-interrupt-controller { - compatible = "samsung,exynos4210-wakeup-eint"; - interrupt-parent = <&gic>; - interrupts = <0 48 0>; - }; - }; - - pinctrl_0: pinctrl@11400000 { - compatible = "samsung,exynos4415-pinctrl"; - reg = <0x11400000 0x1000>; - interrupts = <0 240 0>; - }; - - fimd: fimd@11C00000 { - compatible = "samsung,exynos4415-fimd"; - reg = <0x11C00000 0x30000>; - interrupt-names = "fifo", "vsync", "lcd_sys"; - interrupts = <0 84 0>, <0 85 0>, <0 86 0>; - clocks = <&cmu CLK_SCLK_FIMD0>, <&cmu CLK_FIMD0>; - clock-names = "sclk_fimd", "fimd"; - samsung,power-domain = <&pd_lcd0>; - iommus = <&sysmmu_fimd0>; - samsung,sysreg = <&sysreg_system_controller>; - status = "disabled"; - }; - - dsi_0: dsi@11C80000 { - compatible = "samsung,exynos4415-mipi-dsi"; - reg = <0x11C80000 0x10000>; - interrupts = <0 83 0>; - samsung,phy-type = <0>; - samsung,power-domain = <&pd_lcd0>; - phys = <&mipi_phy 1>; - phy-names = "dsim"; - clocks = <&cmu CLK_DSIM0>, <&cmu CLK_SCLK_MIPI0>; - clock-names = "bus_clk", "pll_clk"; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - sysmmu_fimd0: sysmmu@11E20000 { - compatible = "samsung,exynos-sysmmu"; - reg = <0x11e20000 0x1000>; - interrupts = <0 80 0>, <0 81 0>; - clock-names = "sysmmu", "master"; - clocks = <&cmu CLK_SMMUFIMD0>, <&cmu CLK_FIMD0>; - power-domains = <&pd_lcd0>; - #iommu-cells = <0>; - }; - - hsotg: hsotg@12480000 { - compatible = "samsung,s3c6400-hsotg"; - reg = <0x12480000 0x20000>; - interrupts = <0 141 0>; - clocks = <&cmu CLK_USBDEVICE>; - clock-names = "otg"; - phys = <&exynos_usbphy 0>; - phy-names = "usb2-phy"; - status = "disabled"; - }; - - mshc_0: mshc@12510000 { - compatible = "samsung,exynos5250-dw-mshc"; - reg = <0x12510000 0x1000>; - interrupts = <0 142 0>; - clocks = <&cmu CLK_SDMMC0>, <&cmu CLK_SCLK_MMC0>; - clock-names = "biu", "ciu"; - fifo-depth = <0x80>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - mshc_1: mshc@12520000 { - compatible = "samsung,exynos5250-dw-mshc"; - reg = <0x12520000 0x1000>; - interrupts = <0 143 0>; - clocks = <&cmu CLK_SDMMC1>, <&cmu CLK_SCLK_MMC1>; - clock-names = "biu", "ciu"; - fifo-depth = <0x80>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - mshc_2: mshc@12530000 { - compatible = "samsung,exynos5250-dw-mshc"; - reg = <0x12530000 0x1000>; - interrupts = <0 144 0>; - clocks = <&cmu CLK_SDMMC2>, <&cmu CLK_SCLK_MMC2>; - clock-names = "biu", "ciu"; - fifo-depth = <0x80>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - ehci: ehci@12580000 { - compatible = "samsung,exynos4210-ehci"; - reg = <0x12580000 0x100>; - interrupts = <0 140 0>; - clocks = <&cmu CLK_USBHOST>; - clock-names = "usbhost"; - status = "disabled"; - #address-cells = <1>; - #size-cells = <0>; - port@0 { - reg = <0>; - phys = <&exynos_usbphy 1>; - status = "disabled"; - }; - port@1 { - reg = <1>; - phys = <&exynos_usbphy 2>; - status = "disabled"; - }; - port@2 { - reg = <2>; - phys = <&exynos_usbphy 3>; - status = "disabled"; - }; - }; - - ohci: ohci@12590000 { - compatible = "samsung,exynos4210-ohci"; - reg = <0x12590000 0x100>; - interrupts = <0 140 0>; - clocks = <&cmu CLK_USBHOST>; - clock-names = "usbhost"; - status = "disabled"; - #address-cells = <1>; - #size-cells = <0>; - port@0 { - reg = <0>; - phys = <&exynos_usbphy 1>; - status = "disabled"; - }; - }; - - exynos_usbphy: exynos-usbphy@125B0000 { - compatible = "samsung,exynos4x12-usb2-phy"; - reg = <0x125B0000 0x100>; - samsung,pmureg-phandle = <&pmu_system_controller>; - samsung,sysreg-phandle = <&sysreg_system_controller>; - clocks = <&cmu CLK_USBDEVICE>, <&xusbxti>; - clock-names = "phy", "ref"; - #phy-cells = <1>; - status = "disabled"; - }; - - amba { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <1>; - interrupt-parent = <&gic>; - ranges; - - pdma0: pdma@12680000 { - compatible = "arm,pl330", "arm,primecell"; - reg = <0x12680000 0x1000>; - interrupts = <0 138 0>; - clocks = <&cmu CLK_PDMA0>; - clock-names = "apb_pclk"; - #dma-cells = <1>; - #dma-channels = <8>; - #dma-requests = <32>; - }; - - pdma1: pdma@12690000 { - compatible = "arm,pl330", "arm,primecell"; - reg = <0x12690000 0x1000>; - interrupts = <0 139 0>; - clocks = <&cmu CLK_PDMA1>; - clock-names = "apb_pclk"; - #dma-cells = <1>; - #dma-channels = <8>; - #dma-requests = <32>; - }; - }; - - adc: adc@126C0000 { - compatible = "samsung,exynos3250-adc", - "samsung,exynos-adc-v2"; - reg = <0x126C0000 0x100>, <0x10020718 0x4>; - interrupts = <0 137 0>; - clock-names = "adc", "sclk"; - clocks = <&cmu CLK_TSADC>, <&cmu CLK_SCLK_TSADC>; - #io-channel-cells = <1>; - io-channel-ranges; - status = "disabled"; - }; - - serial_0: serial@13800000 { - compatible = "samsung,exynos4210-uart"; - reg = <0x13800000 0x100>; - interrupts = <0 109 0>; - clocks = <&cmu CLK_UART0>, <&cmu CLK_SCLK_UART0>; - clock-names = "uart", "clk_uart_baud0"; - status = "disabled"; - }; - - serial_1: serial@13810000 { - compatible = "samsung,exynos4210-uart"; - reg = <0x13810000 0x100>; - interrupts = <0 110 0>; - clocks = <&cmu CLK_UART1>, <&cmu CLK_SCLK_UART1>; - clock-names = "uart", "clk_uart_baud0"; - status = "disabled"; - }; - - serial_2: serial@13820000 { - compatible = "samsung,exynos4210-uart"; - reg = <0x13820000 0x100>; - interrupts = <0 111 0>; - clocks = <&cmu CLK_UART2>, <&cmu CLK_SCLK_UART2>; - clock-names = "uart", "clk_uart_baud0"; - status = "disabled"; - }; - - serial_3: serial@13830000 { - compatible = "samsung,exynos4210-uart"; - reg = <0x13830000 0x100>; - interrupts = <0 112 0>; - clocks = <&cmu CLK_UART3>, <&cmu CLK_SCLK_UART3>; - clock-names = "uart", "clk_uart_baud0"; - status = "disabled"; - }; - - i2c_0: i2c@13860000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "samsung,s3c2440-i2c"; - reg = <0x13860000 0x100>; - interrupts = <0 113 0>; - clocks = <&cmu CLK_I2C0>; - clock-names = "i2c"; - pinctrl-names = "default"; - pinctrl-0 = <&i2c0_bus>; - status = "disabled"; - }; - - i2c_1: i2c@13870000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "samsung,s3c2440-i2c"; - reg = <0x13870000 0x100>; - interrupts = <0 114 0>; - clocks = <&cmu CLK_I2C1>; - clock-names = "i2c"; - pinctrl-names = "default"; - pinctrl-0 = <&i2c1_bus>; - status = "disabled"; - }; - - i2c_2: i2c@13880000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "samsung,s3c2440-i2c"; - reg = <0x13880000 0x100>; - interrupts = <0 115 0>; - clocks = <&cmu CLK_I2C2>; - clock-names = "i2c"; - pinctrl-names = "default"; - pinctrl-0 = <&i2c2_bus>; - status = "disabled"; - }; - - i2c_3: i2c@13890000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "samsung,s3c2440-i2c"; - reg = <0x13890000 0x100>; - interrupts = <0 116 0>; - clocks = <&cmu CLK_I2C3>; - clock-names = "i2c"; - pinctrl-names = "default"; - pinctrl-0 = <&i2c3_bus>; - status = "disabled"; - }; - - i2c_4: i2c@138A0000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "samsung,s3c2440-i2c"; - reg = <0x138A0000 0x100>; - interrupts = <0 117 0>; - clocks = <&cmu CLK_I2C4>; - clock-names = "i2c"; - pinctrl-names = "default"; - pinctrl-0 = <&i2c4_bus>; - status = "disabled"; - }; - - i2c_5: i2c@138B0000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "samsung,s3c2440-i2c"; - reg = <0x138B0000 0x100>; - interrupts = <0 118 0>; - clocks = <&cmu CLK_I2C5>; - clock-names = "i2c"; - pinctrl-names = "default"; - pinctrl-0 = <&i2c5_bus>; - status = "disabled"; - }; - - i2c_6: i2c@138C0000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "samsung,s3c2440-i2c"; - reg = <0x138C0000 0x100>; - interrupts = <0 119 0>; - clocks = <&cmu CLK_I2C6>; - clock-names = "i2c"; - pinctrl-names = "default"; - pinctrl-0 = <&i2c6_bus>; - status = "disabled"; - }; - - i2c_7: i2c@138D0000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "samsung,s3c2440-i2c"; - reg = <0x138D0000 0x100>; - interrupts = <0 120 0>; - clocks = <&cmu CLK_I2C7>; - clock-names = "i2c"; - pinctrl-names = "default"; - pinctrl-0 = <&i2c7_bus>; - status = "disabled"; - }; - - spi_0: spi@13920000 { - compatible = "samsung,exynos4210-spi"; - reg = <0x13920000 0x100>; - interrupts = <0 121 0>; - dmas = <&pdma0 7>, <&pdma0 6>; - dma-names = "tx", "rx"; - #address-cells = <1>; - #size-cells = <0>; - clocks = <&cmu CLK_SPI0>, <&cmu CLK_SCLK_SPI0>; - clock-names = "spi", "spi_busclk0"; - samsung,spi-src-clk = <0>; - pinctrl-names = "default"; - pinctrl-0 = <&spi0_bus>; - status = "disabled"; - }; - - spi_1: spi@13930000 { - compatible = "samsung,exynos4210-spi"; - reg = <0x13930000 0x100>; - interrupts = <0 122 0>; - dmas = <&pdma1 7>, <&pdma1 6>; - dma-names = "tx", "rx"; - #address-cells = <1>; - #size-cells = <0>; - clocks = <&cmu CLK_SPI1>, <&cmu CLK_SCLK_SPI1>; - clock-names = "spi", "spi_busclk0"; - samsung,spi-src-clk = <0>; - pinctrl-names = "default"; - pinctrl-0 = <&spi1_bus>; - status = "disabled"; - }; - - spi_2: spi@13940000 { - compatible = "samsung,exynos4210-spi"; - reg = <0x13940000 0x100>; - interrupts = <0 123 0>; - dmas = <&pdma0 9>, <&pdma0 8>; - dma-names = "tx", "rx"; - #address-cells = <1>; - #size-cells = <0>; - clocks = <&cmu CLK_SPI2>, <&cmu CLK_SCLK_SPI2>; - clock-names = "spi", "spi_busclk0"; - samsung,spi-src-clk = <0>; - pinctrl-names = "default"; - pinctrl-0 = <&spi2_bus>; - status = "disabled"; - }; - - clock_audss: clock-controller@03810000 { - compatible = "samsung,exynos4210-audss-clock"; - reg = <0x03810000 0x0C>; - #clock-cells = <1>; - }; - - i2s0: i2s@3830000 { - compatible = "samsung,s5pv210-i2s"; - reg = <0x03830000 0x100>; - interrupts = <0 124 0>; - clocks = <&clock_audss EXYNOS_I2S_BUS>, - <&clock_audss EXYNOS_SCLK_I2S>; - clock-names = "iis", "i2s_opclk0"; - dmas = <&pdma1 10>, <&pdma1 9>, <&pdma1 8>; - dma-names = "tx", "rx", "tx-sec"; - pinctrl-names = "default"; - pinctrl-0 = <&i2s0_bus>; - samsung,idma-addr = <0x03000000>; - status = "disabled"; - }; - - pwm: pwm@139D0000 { - compatible = "samsung,exynos4210-pwm"; - reg = <0x139D0000 0x1000>; - interrupts = <0 104 0>, <0 105 0>, <0 106 0>, - <0 107 0>, <0 108 0>; - #pwm-cells = <3>; - status = "disabled"; - }; - - pmu { - compatible = "arm,cortex-a9-pmu"; - interrupts = <0 18 0>, <0 19 0>, <0 20 0>, <0 21 0>; - }; - }; -}; - -#include "exynos4415-pinctrl.dtsi" diff --git a/arch/arm/boot/dts/exynos4x12-pinctrl.dtsi b/arch/arm/boot/dts/exynos4x12-pinctrl.dtsi index a56bf9b1a412..2f866f6e5838 100644 --- a/arch/arm/boot/dts/exynos4x12-pinctrl.dtsi +++ b/arch/arm/boot/dts/exynos4x12-pinctrl.dtsi @@ -572,8 +572,14 @@ interrupt-controller; interrupt-parent = <&gic>; - interrupts = <0 16 0>, <0 17 0>, <0 18 0>, <0 19 0>, - <0 20 0>, <0 21 0>, <0 22 0>, <0 23 0>; + interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>; #interrupt-cells = <2>; }; @@ -583,8 +589,14 @@ interrupt-controller; interrupt-parent = <&gic>; - interrupts = <0 24 0>, <0 25 0>, <0 26 0>, <0 27 0>, - <0 28 0>, <0 29 0>, <0 30 0>, <0 31 0>; + interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>; #interrupt-cells = <2>; }; diff --git a/arch/arm/boot/dts/exynos4x12.dtsi b/arch/arm/boot/dts/exynos4x12.dtsi index 3394bdcf10ae..85a7122658f1 100644 --- a/arch/arm/boot/dts/exynos4x12.dtsi +++ b/arch/arm/boot/dts/exynos4x12.dtsi @@ -88,11 +88,11 @@ #interrupt-cells = <1>; #address-cells = <0>; #size-cells = <0>; - interrupt-map = <0 &gic 0 57 0>, + interrupt-map = <0 &gic 0 57 IRQ_TYPE_LEVEL_HIGH>, <1 &combiner 12 5>, <2 &combiner 12 6>, <3 &combiner 12 7>, - <4 &gic 1 12 0>; + <4 &gic 1 12 IRQ_TYPE_LEVEL_HIGH>; }; }; @@ -112,7 +112,7 @@ g2d: g2d@10800000 { compatible = "samsung,exynos4212-g2d"; reg = <0x10800000 0x1000>; - interrupts = <0 89 0>; + interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>; clocks = <&clock CLK_SCLK_FIMG2D>, <&clock CLK_G2D>; clock-names = "sclk_fimg2d", "fimg2d"; iommus = <&sysmmu_g2d>; @@ -127,7 +127,7 @@ fimc_lite_0: fimc-lite@12390000 { compatible = "samsung,exynos4212-fimc-lite"; reg = <0x12390000 0x1000>; - interrupts = <0 105 0>; + interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>; power-domains = <&pd_isp>; clocks = <&clock CLK_FIMC_LITE0>; clock-names = "flite"; @@ -138,7 +138,7 @@ fimc_lite_1: fimc-lite@123A0000 { compatible = "samsung,exynos4212-fimc-lite"; reg = <0x123A0000 0x1000>; - interrupts = <0 106 0>; + interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>; power-domains = <&pd_isp>; clocks = <&clock CLK_FIMC_LITE1>; clock-names = "flite"; @@ -147,9 +147,10 @@ }; fimc_is: fimc-is@12000000 { - compatible = "samsung,exynos4212-fimc-is", "simple-bus"; + compatible = "samsung,exynos4212-fimc-is"; reg = <0x12000000 0x260000>; - interrupts = <0 90 0>, <0 95 0>; + interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>; power-domains = <&pd_isp>; clocks = <&clock CLK_FIMC_LITE0>, <&clock CLK_FIMC_LITE1>, <&clock CLK_PPMUISPX>, @@ -200,7 +201,7 @@ mshc_0: mmc@12550000 { compatible = "samsung,exynos4412-dw-mshc"; reg = <0x12550000 0x1000>; - interrupts = <0 77 0>; + interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>; #address-cells = <1>; #size-cells = <0>; fifo-depth = <0x80>; @@ -461,11 +462,26 @@ }; &combiner { - interrupts = <0 0 0>, <0 1 0>, <0 2 0>, <0 3 0>, - <0 4 0>, <0 5 0>, <0 6 0>, <0 7 0>, - <0 8 0>, <0 9 0>, <0 10 0>, <0 11 0>, - <0 12 0>, <0 13 0>, <0 14 0>, <0 15 0>, - <0 107 0>, <0 108 0>, <0 48 0>, <0 42 0>; + interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>; }; &exynos_usbphy { @@ -529,18 +545,18 @@ &pinctrl_0 { compatible = "samsung,exynos4x12-pinctrl"; reg = <0x11400000 0x1000>; - interrupts = <0 47 0>; + interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>; }; &pinctrl_1 { compatible = "samsung,exynos4x12-pinctrl"; reg = <0x11000000 0x1000>; - interrupts = <0 46 0>; + interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>; wakup_eint: wakeup-interrupt-controller { compatible = "samsung,exynos4210-wakeup-eint"; interrupt-parent = <&gic>; - interrupts = <0 32 0>; + interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>; }; }; @@ -554,7 +570,7 @@ &pinctrl_3 { compatible = "samsung,exynos4x12-pinctrl"; reg = <0x106E0000 0x1000>; - interrupts = <0 72 0>; + interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>; }; &pmu_system_controller { diff --git a/arch/arm/boot/dts/exynos5.dtsi b/arch/arm/boot/dts/exynos5.dtsi index 8f06609879f5..7fd870ee5093 100644 --- a/arch/arm/boot/dts/exynos5.dtsi +++ b/arch/arm/boot/dts/exynos5.dtsi @@ -13,6 +13,8 @@ * published by the Free Software Foundation. */ +#include <dt-bindings/interrupt-controller/arm-gic.h> +#include <dt-bindings/interrupt-controller/irq.h> #include "exynos-syscon-restart.dtsi" / { @@ -53,14 +55,38 @@ interrupt-controller; samsung,combiner-nr = <32>; reg = <0x10440000 0x1000>; - interrupts = <0 0 0>, <0 1 0>, <0 2 0>, <0 3 0>, - <0 4 0>, <0 5 0>, <0 6 0>, <0 7 0>, - <0 8 0>, <0 9 0>, <0 10 0>, <0 11 0>, - <0 12 0>, <0 13 0>, <0 14 0>, <0 15 0>, - <0 16 0>, <0 17 0>, <0 18 0>, <0 19 0>, - <0 20 0>, <0 21 0>, <0 22 0>, <0 23 0>, - <0 24 0>, <0 25 0>, <0 26 0>, <0 27 0>, - <0 28 0>, <0 29 0>, <0 30 0>, <0 31 0>; + interrupts = <0 0 IRQ_TYPE_LEVEL_HIGH>, + <0 1 IRQ_TYPE_LEVEL_HIGH>, + <0 2 IRQ_TYPE_LEVEL_HIGH>, + <0 3 IRQ_TYPE_LEVEL_HIGH>, + <0 4 IRQ_TYPE_LEVEL_HIGH>, + <0 5 IRQ_TYPE_LEVEL_HIGH>, + <0 6 IRQ_TYPE_LEVEL_HIGH>, + <0 7 IRQ_TYPE_LEVEL_HIGH>, + <0 8 IRQ_TYPE_LEVEL_HIGH>, + <0 9 IRQ_TYPE_LEVEL_HIGH>, + <0 10 IRQ_TYPE_LEVEL_HIGH>, + <0 11 IRQ_TYPE_LEVEL_HIGH>, + <0 12 IRQ_TYPE_LEVEL_HIGH>, + <0 13 IRQ_TYPE_LEVEL_HIGH>, + <0 14 IRQ_TYPE_LEVEL_HIGH>, + <0 15 IRQ_TYPE_LEVEL_HIGH>, + <0 16 IRQ_TYPE_LEVEL_HIGH>, + <0 17 IRQ_TYPE_LEVEL_HIGH>, + <0 18 IRQ_TYPE_LEVEL_HIGH>, + <0 19 IRQ_TYPE_LEVEL_HIGH>, + <0 20 IRQ_TYPE_LEVEL_HIGH>, + <0 21 IRQ_TYPE_LEVEL_HIGH>, + <0 22 IRQ_TYPE_LEVEL_HIGH>, + <0 23 IRQ_TYPE_LEVEL_HIGH>, + <0 24 IRQ_TYPE_LEVEL_HIGH>, + <0 25 IRQ_TYPE_LEVEL_HIGH>, + <0 26 IRQ_TYPE_LEVEL_HIGH>, + <0 27 IRQ_TYPE_LEVEL_HIGH>, + <0 28 IRQ_TYPE_LEVEL_HIGH>, + <0 29 IRQ_TYPE_LEVEL_HIGH>, + <0 30 IRQ_TYPE_LEVEL_HIGH>, + <0 31 IRQ_TYPE_LEVEL_HIGH>; }; gic: interrupt-controller@10481000 { @@ -71,7 +97,8 @@ <0x10482000 0x1000>, <0x10484000 0x2000>, <0x10486000 0x2000>; - interrupts = <1 9 0xf04>; + interrupts = <GIC_PPI 9 + (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; }; sysreg_system_controller: syscon@10050000 { @@ -82,31 +109,31 @@ serial_0: serial@12C00000 { compatible = "samsung,exynos4210-uart"; reg = <0x12C00000 0x100>; - interrupts = <0 51 0>; + interrupts = <0 51 IRQ_TYPE_LEVEL_HIGH>; }; serial_1: serial@12C10000 { compatible = "samsung,exynos4210-uart"; reg = <0x12C10000 0x100>; - interrupts = <0 52 0>; + interrupts = <0 52 IRQ_TYPE_LEVEL_HIGH>; }; serial_2: serial@12C20000 { compatible = "samsung,exynos4210-uart"; reg = <0x12C20000 0x100>; - interrupts = <0 53 0>; + interrupts = <0 53 IRQ_TYPE_LEVEL_HIGH>; }; serial_3: serial@12C30000 { compatible = "samsung,exynos4210-uart"; reg = <0x12C30000 0x100>; - interrupts = <0 54 0>; + interrupts = <0 54 IRQ_TYPE_LEVEL_HIGH>; }; i2c_0: i2c@12C60000 { compatible = "samsung,s3c2440-i2c"; reg = <0x12C60000 0x100>; - interrupts = <0 56 0>; + interrupts = <0 56 IRQ_TYPE_LEVEL_HIGH>; #address-cells = <1>; #size-cells = <0>; samsung,sysreg-phandle = <&sysreg_system_controller>; @@ -116,7 +143,7 @@ i2c_1: i2c@12C70000 { compatible = "samsung,s3c2440-i2c"; reg = <0x12C70000 0x100>; - interrupts = <0 57 0>; + interrupts = <0 57 IRQ_TYPE_LEVEL_HIGH>; #address-cells = <1>; #size-cells = <0>; samsung,sysreg-phandle = <&sysreg_system_controller>; @@ -126,7 +153,7 @@ i2c_2: i2c@12C80000 { compatible = "samsung,s3c2440-i2c"; reg = <0x12C80000 0x100>; - interrupts = <0 58 0>; + interrupts = <0 58 IRQ_TYPE_LEVEL_HIGH>; #address-cells = <1>; #size-cells = <0>; samsung,sysreg-phandle = <&sysreg_system_controller>; @@ -136,7 +163,7 @@ i2c_3: i2c@12C90000 { compatible = "samsung,s3c2440-i2c"; reg = <0x12C90000 0x100>; - interrupts = <0 59 0>; + interrupts = <0 59 IRQ_TYPE_LEVEL_HIGH>; #address-cells = <1>; #size-cells = <0>; samsung,sysreg-phandle = <&sysreg_system_controller>; @@ -153,7 +180,8 @@ rtc: rtc@101E0000 { compatible = "samsung,s3c6410-rtc"; reg = <0x101E0000 0x100>; - interrupts = <0 43 0>, <0 44 0>; + interrupts = <0 43 IRQ_TYPE_LEVEL_HIGH>, + <0 44 IRQ_TYPE_LEVEL_HIGH>; status = "disabled"; }; diff --git a/arch/arm/boot/dts/exynos5250-snow-common.dtsi b/arch/arm/boot/dts/exynos5250-snow-common.dtsi index d5d51916bb74..8f3a80430748 100644 --- a/arch/arm/boot/dts/exynos5250-snow-common.dtsi +++ b/arch/arm/boot/dts/exynos5250-snow-common.dtsi @@ -523,6 +523,7 @@ status = "okay"; }; +/* eMMC flash */ &mmc_0 { status = "okay"; num-slots = <1>; @@ -536,6 +537,7 @@ cap-mmc-highspeed; }; +/* uSD card */ &mmc_2 { status = "okay"; num-slots = <1>; @@ -553,6 +555,8 @@ /* * On Snow we've got SIP WiFi and so can keep drive strengths low to * reduce EMI. + * + * WiFi SDIO module */ &mmc_3 { status = "okay"; diff --git a/arch/arm/boot/dts/exynos5250.dtsi b/arch/arm/boot/dts/exynos5250.dtsi index f7357d99b47c..b6d7444d8585 100644 --- a/arch/arm/boot/dts/exynos5250.dtsi +++ b/arch/arm/boot/dts/exynos5250.dtsi @@ -181,8 +181,8 @@ <0x1 0 &combiner 23 4>, <0x2 0 &combiner 25 2>, <0x3 0 &combiner 25 3>, - <0x4 0 &gic 0 120 0>, - <0x5 0 &gic 0 121 0>; + <0x4 0 &gic 0 120 IRQ_TYPE_LEVEL_HIGH>, + <0x5 0 &gic 0 121 IRQ_TYPE_LEVEL_HIGH>; }; }; @@ -195,31 +195,31 @@ pinctrl_0: pinctrl@11400000 { compatible = "samsung,exynos5250-pinctrl"; reg = <0x11400000 0x1000>; - interrupts = <0 46 0>; + interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>; wakup_eint: wakeup-interrupt-controller { compatible = "samsung,exynos4210-wakeup-eint"; interrupt-parent = <&gic>; - interrupts = <0 32 0>; + interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>; }; }; pinctrl_1: pinctrl@13400000 { compatible = "samsung,exynos5250-pinctrl"; reg = <0x13400000 0x1000>; - interrupts = <0 45 0>; + interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>; }; pinctrl_2: pinctrl@10d10000 { compatible = "samsung,exynos5250-pinctrl"; reg = <0x10d10000 0x1000>; - interrupts = <0 50 0>; + interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>; }; pinctrl_3: pinctrl@03860000 { compatible = "samsung,exynos5250-pinctrl"; reg = <0x03860000 0x1000>; - interrupts = <0 47 0>; + interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>; }; pmu_system_controller: system-controller@10040000 { @@ -236,7 +236,7 @@ watchdog@101D0000 { compatible = "samsung,exynos5250-wdt"; reg = <0x101D0000 0x100>; - interrupts = <0 42 0>; + interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>; clocks = <&clock CLK_WDT>; clock-names = "watchdog"; samsung,syscon-phandle = <&pmu_system_controller>; @@ -245,7 +245,7 @@ g2d@10850000 { compatible = "samsung,exynos5250-g2d"; reg = <0x10850000 0x1000>; - interrupts = <0 91 0>; + interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>; clocks = <&clock CLK_G2D>; clock-names = "fimg2d"; iommus = <&sysmmu_g2d>; @@ -254,7 +254,7 @@ mfc: codec@11000000 { compatible = "samsung,mfc-v6"; reg = <0x11000000 0x10000>; - interrupts = <0 96 0>; + interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>; power-domains = <&pd_mfc>; clocks = <&clock CLK_MFC>; clock-names = "mfc"; @@ -265,7 +265,7 @@ rotator: rotator@11C00000 { compatible = "samsung,exynos5250-rotator"; reg = <0x11C00000 0x64>; - interrupts = <0 84 0>; + interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>; clocks = <&clock CLK_ROTATOR>; clock-names = "rotator"; iommus = <&sysmmu_rotator>; @@ -274,7 +274,7 @@ tmu: tmu@10060000 { compatible = "samsung,exynos5250-tmu"; reg = <0x10060000 0x100>; - interrupts = <0 65 0>; + interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>; clocks = <&clock CLK_TMU>; clock-names = "tmu_apbif"; #include "exynos4412-tmu-sensor-conf.dtsi" @@ -284,7 +284,7 @@ compatible = "snps,dwc-ahci"; samsung,sata-freq = <66>; reg = <0x122F0000 0x1ff>; - interrupts = <0 115 0>; + interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>; clocks = <&clock CLK_SATA>, <&clock CLK_SCLK_SATA>; clock-names = "sata", "sclk_sata"; phys = <&sata_phy>; @@ -306,7 +306,7 @@ i2c_4: i2c@12CA0000 { compatible = "samsung,s3c2440-i2c"; reg = <0x12CA0000 0x100>; - interrupts = <0 60 0>; + interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>; #address-cells = <1>; #size-cells = <0>; clocks = <&clock CLK_I2C4>; @@ -319,7 +319,7 @@ i2c_5: i2c@12CB0000 { compatible = "samsung,s3c2440-i2c"; reg = <0x12CB0000 0x100>; - interrupts = <0 61 0>; + interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>; #address-cells = <1>; #size-cells = <0>; clocks = <&clock CLK_I2C5>; @@ -332,7 +332,7 @@ i2c_6: i2c@12CC0000 { compatible = "samsung,s3c2440-i2c"; reg = <0x12CC0000 0x100>; - interrupts = <0 62 0>; + interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>; #address-cells = <1>; #size-cells = <0>; clocks = <&clock CLK_I2C6>; @@ -345,7 +345,7 @@ i2c_7: i2c@12CD0000 { compatible = "samsung,s3c2440-i2c"; reg = <0x12CD0000 0x100>; - interrupts = <0 63 0>; + interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>; #address-cells = <1>; #size-cells = <0>; clocks = <&clock CLK_I2C7>; @@ -358,7 +358,7 @@ i2c_8: i2c@12CE0000 { compatible = "samsung,s3c2440-hdmiphy-i2c"; reg = <0x12CE0000 0x1000>; - interrupts = <0 64 0>; + interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>; #address-cells = <1>; #size-cells = <0>; clocks = <&clock CLK_I2C_HDMI>; @@ -380,7 +380,7 @@ compatible = "samsung,exynos4210-spi"; status = "disabled"; reg = <0x12d20000 0x100>; - interrupts = <0 66 0>; + interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>; dmas = <&pdma0 5 &pdma0 4>; dma-names = "tx", "rx"; @@ -396,7 +396,7 @@ compatible = "samsung,exynos4210-spi"; status = "disabled"; reg = <0x12d30000 0x100>; - interrupts = <0 67 0>; + interrupts = <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>; dmas = <&pdma1 5 &pdma1 4>; dma-names = "tx", "rx"; @@ -412,7 +412,7 @@ compatible = "samsung,exynos4210-spi"; status = "disabled"; reg = <0x12d40000 0x100>; - interrupts = <0 68 0>; + interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>; dmas = <&pdma0 7 &pdma0 6>; dma-names = "tx", "rx"; @@ -426,7 +426,7 @@ mmc_0: mmc@12200000 { compatible = "samsung,exynos5250-dw-mshc"; - interrupts = <0 75 0>; + interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>; #address-cells = <1>; #size-cells = <0>; reg = <0x12200000 0x1000>; @@ -438,7 +438,7 @@ mmc_1: mmc@12210000 { compatible = "samsung,exynos5250-dw-mshc"; - interrupts = <0 76 0>; + interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>; #address-cells = <1>; #size-cells = <0>; reg = <0x12210000 0x1000>; @@ -450,7 +450,7 @@ mmc_2: mmc@12220000 { compatible = "samsung,exynos5250-dw-mshc"; - interrupts = <0 77 0>; + interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>; #address-cells = <1>; #size-cells = <0>; reg = <0x12220000 0x1000>; @@ -463,7 +463,7 @@ mmc_3: mmc@12230000 { compatible = "samsung,exynos5250-dw-mshc"; reg = <0x12230000 0x1000>; - interrupts = <0 78 0>; + interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>; #address-cells = <1>; #size-cells = <0>; clocks = <&clock CLK_SDMMC3>, <&clock CLK_SCLK_MMC3>; @@ -526,7 +526,7 @@ usbdrd_dwc3: dwc3@12000000 { compatible = "synopsys,dwc3"; reg = <0x12000000 0x10000>; - interrupts = <0 72 0>; + interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>; phys = <&usbdrd_phy 0>, <&usbdrd_phy 1>; phy-names = "usb2-phy", "usb3-phy"; }; @@ -544,7 +544,7 @@ ehci: usb@12110000 { compatible = "samsung,exynos4210-ehci"; reg = <0x12110000 0x100>; - interrupts = <0 71 0>; + interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>; clocks = <&clock CLK_USB2>; clock-names = "usbhost"; @@ -559,7 +559,7 @@ ohci: usb@12120000 { compatible = "samsung,exynos4210-ohci"; reg = <0x12120000 0x100>; - interrupts = <0 71 0>; + interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>; clocks = <&clock CLK_USB2>; clock-names = "usbhost"; @@ -591,7 +591,7 @@ pdma0: pdma@121A0000 { compatible = "arm,pl330", "arm,primecell"; reg = <0x121A0000 0x1000>; - interrupts = <0 34 0>; + interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>; clocks = <&clock CLK_PDMA0>; clock-names = "apb_pclk"; #dma-cells = <1>; @@ -602,7 +602,7 @@ pdma1: pdma@121B0000 { compatible = "arm,pl330", "arm,primecell"; reg = <0x121B0000 0x1000>; - interrupts = <0 35 0>; + interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>; clocks = <&clock CLK_PDMA1>; clock-names = "apb_pclk"; #dma-cells = <1>; @@ -613,7 +613,7 @@ mdma0: mdma@10800000 { compatible = "arm,pl330", "arm,primecell"; reg = <0x10800000 0x1000>; - interrupts = <0 33 0>; + interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>; clocks = <&clock CLK_MDMA0>; clock-names = "apb_pclk"; #dma-cells = <1>; @@ -624,7 +624,7 @@ mdma1: mdma@11C10000 { compatible = "arm,pl330", "arm,primecell"; reg = <0x11C10000 0x1000>; - interrupts = <0 124 0>; + interrupts = <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>; clocks = <&clock CLK_MDMA1>; clock-names = "apb_pclk"; #dma-cells = <1>; @@ -636,7 +636,7 @@ gsc_0: gsc@13e00000 { compatible = "samsung,exynos5-gsc"; reg = <0x13e00000 0x1000>; - interrupts = <0 85 0>; + interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>; power-domains = <&pd_gsc>; clocks = <&clock CLK_GSCL0>; clock-names = "gscl"; @@ -646,7 +646,7 @@ gsc_1: gsc@13e10000 { compatible = "samsung,exynos5-gsc"; reg = <0x13e10000 0x1000>; - interrupts = <0 86 0>; + interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>; power-domains = <&pd_gsc>; clocks = <&clock CLK_GSCL1>; clock-names = "gscl"; @@ -656,7 +656,7 @@ gsc_2: gsc@13e20000 { compatible = "samsung,exynos5-gsc"; reg = <0x13e20000 0x1000>; - interrupts = <0 87 0>; + interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>; power-domains = <&pd_gsc>; clocks = <&clock CLK_GSCL2>; clock-names = "gscl"; @@ -666,7 +666,7 @@ gsc_3: gsc@13e30000 { compatible = "samsung,exynos5-gsc"; reg = <0x13e30000 0x1000>; - interrupts = <0 88 0>; + interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>; power-domains = <&pd_gsc>; clocks = <&clock CLK_GSCL3>; clock-names = "gscl"; @@ -677,7 +677,7 @@ compatible = "samsung,exynos4212-hdmi"; reg = <0x14530000 0x70000>; power-domains = <&pd_disp1>; - interrupts = <0 95 0>; + interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>; clocks = <&clock CLK_HDMI>, <&clock CLK_SCLK_HDMI>, <&clock CLK_SCLK_PIXEL>, <&clock CLK_SCLK_HDMIPHY>, <&clock CLK_MOUT_HDMI>; @@ -690,7 +690,7 @@ compatible = "samsung,exynos5250-mixer"; reg = <0x14450000 0x10000>; power-domains = <&pd_disp1>; - interrupts = <0 94 0>; + interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>; clocks = <&clock CLK_MIXER>, <&clock CLK_HDMI>, <&clock CLK_SCLK_HDMI>; clock-names = "mixer", "hdmi", "sclk_hdmi"; @@ -706,7 +706,7 @@ adc: adc@12D10000 { compatible = "samsung,exynos-adc-v1"; reg = <0x12D10000 0x100>; - interrupts = <0 106 0>; + interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>; clocks = <&clock CLK_ADC>; clock-names = "adc"; #io-channel-cells = <1>; @@ -718,7 +718,7 @@ sss@10830000 { compatible = "samsung,exynos4210-secss"; reg = <0x10830000 0x300>; - interrupts = <0 112 0>; + interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>; clocks = <&clock CLK_SSS>; clock-names = "secss"; }; diff --git a/arch/arm/boot/dts/exynos5260.dtsi b/arch/arm/boot/dts/exynos5260.dtsi index a86a4898d077..5818718618b1 100644 --- a/arch/arm/boot/dts/exynos5260.dtsi +++ b/arch/arm/boot/dts/exynos5260.dtsi @@ -10,6 +10,8 @@ */ #include <dt-bindings/clock/exynos5260-clk.h> +#include <dt-bindings/interrupt-controller/arm-gic.h> +#include <dt-bindings/interrupt-controller/irq.h> / { compatible = "samsung,exynos5260", "samsung,exynos5"; @@ -168,7 +170,8 @@ <0x10482000 0x1000>, <0x10484000 0x2000>, <0x10486000 0x2000>; - interrupts = <1 9 0xf04>; + interrupts = <GIC_PPI 9 + (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; }; chipid: chipid@10000000 { @@ -181,10 +184,18 @@ reg = <0x100B0000 0x1000>; clocks = <&fin_pll>, <&clock_peri PERI_CLK_MCT>; clock-names = "fin_pll", "mct"; - interrupts = <0 104 0>, <0 105 0>, <0 106 0>, - <0 107 0>, <0 122 0>, <0 123 0>, - <0 124 0>, <0 125 0>, <0 126 0>, - <0 127 0>, <0 128 0>, <0 129 0>; + interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 129 IRQ_TYPE_LEVEL_HIGH>; }; cci: cci@10F00000 { @@ -210,25 +221,25 @@ pinctrl_0: pinctrl@11600000 { compatible = "samsung,exynos5260-pinctrl"; reg = <0x11600000 0x1000>; - interrupts = <0 79 0>; + interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>; wakeup-interrupt-controller { compatible = "samsung,exynos4210-wakeup-eint"; interrupt-parent = <&gic>; - interrupts = <0 32 0>; + interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>; }; }; pinctrl_1: pinctrl@12290000 { compatible = "samsung,exynos5260-pinctrl"; reg = <0x12290000 0x1000>; - interrupts = <0 157 0>; + interrupts = <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>; }; pinctrl_2: pinctrl@128B0000 { compatible = "samsung,exynos5260-pinctrl"; reg = <0x128B0000 0x1000>; - interrupts = <0 243 0>; + interrupts = <GIC_SPI 243 IRQ_TYPE_LEVEL_HIGH>; }; pmu_system_controller: system-controller@10D50000 { @@ -239,7 +250,7 @@ uart0: serial@12C00000 { compatible = "samsung,exynos4210-uart"; reg = <0x12C00000 0x100>; - interrupts = <0 146 0>; + interrupts = <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>; clocks = <&clock_peri PERI_CLK_UART0>, <&clock_peri PERI_SCLK_UART0>; clock-names = "uart", "clk_uart_baud0"; status = "disabled"; @@ -248,7 +259,7 @@ uart1: serial@12C10000 { compatible = "samsung,exynos4210-uart"; reg = <0x12C10000 0x100>; - interrupts = <0 147 0>; + interrupts = <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>; clocks = <&clock_peri PERI_CLK_UART1>, <&clock_peri PERI_SCLK_UART1>; clock-names = "uart", "clk_uart_baud0"; status = "disabled"; @@ -257,7 +268,7 @@ uart2: serial@12C20000 { compatible = "samsung,exynos4210-uart"; reg = <0x12C20000 0x100>; - interrupts = <0 148 0>; + interrupts = <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>; clocks = <&clock_peri PERI_CLK_UART2>, <&clock_peri PERI_SCLK_UART2>; clock-names = "uart", "clk_uart_baud0"; status = "disabled"; @@ -266,7 +277,7 @@ uart3: serial@12860000 { compatible = "samsung,exynos4210-uart"; reg = <0x12860000 0x100>; - interrupts = <0 145 0>; + interrupts = <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>; clocks = <&clock_aud AUD_CLK_AUD_UART>, <&clock_aud AUD_SCLK_AUD_UART>; clock-names = "uart", "clk_uart_baud0"; status = "disabled"; @@ -275,7 +286,7 @@ mmc_0: mmc@12140000 { compatible = "samsung,exynos5250-dw-mshc"; reg = <0x12140000 0x2000>; - interrupts = <0 156 0>; + interrupts = <GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH>; #address-cells = <1>; #size-cells = <0>; clocks = <&clock_fsys FSYS_CLK_MMC0>, <&clock_top TOP_SCLK_MMC0>; @@ -287,7 +298,7 @@ mmc_1: mmc@12150000 { compatible = "samsung,exynos5250-dw-mshc"; reg = <0x12150000 0x2000>; - interrupts = <0 158 0>; + interrupts = <GIC_SPI 158 IRQ_TYPE_LEVEL_HIGH>; #address-cells = <1>; #size-cells = <0>; clocks = <&clock_fsys FSYS_CLK_MMC1>, <&clock_top TOP_SCLK_MMC1>; @@ -299,7 +310,7 @@ mmc_2: mmc@12160000 { compatible = "samsung,exynos5250-dw-mshc"; reg = <0x12160000 0x2000>; - interrupts = <0 159 0>; + interrupts = <GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH>; #address-cells = <1>; #size-cells = <0>; clocks = <&clock_fsys FSYS_CLK_MMC2>, <&clock_top TOP_SCLK_MMC2>; diff --git a/arch/arm/boot/dts/exynos5410-odroidxu.dts b/arch/arm/boot/dts/exynos5410-odroidxu.dts index 3c271cb4b2be..c4de1353e5df 100644 --- a/arch/arm/boot/dts/exynos5410-odroidxu.dts +++ b/arch/arm/boot/dts/exynos5410-odroidxu.dts @@ -15,6 +15,7 @@ #include <dt-bindings/clock/maxim,max77802.h> #include <dt-bindings/gpio/gpio.h> #include <dt-bindings/interrupt-controller/irq.h> +#include <dt-bindings/sound/samsung-i2s.h> #include "exynos54xx-odroidxu-leds.dtsi" / { @@ -57,6 +58,61 @@ compatible = "samsung,secure-firmware"; reg = <0x02073000 0x1000>; }; + + sound: sound { + compatible = "simple-audio-card"; + + simple-audio-card,name = "Odroid-XU"; + simple-audio-card,widgets = + "Headphone", "Headphone Jack", + "Speakers", "Speakers"; + simple-audio-card,routing = + "Headphone Jack", "HPL", + "Headphone Jack", "HPR", + "Headphone Jack", "MICBIAS", + "IN1", "Headphone Jack", + "Speakers", "SPKL", + "Speakers", "SPKR"; + + simple-audio-card,format = "i2s"; + simple-audio-card,bitclock-master = <&link0_codec>; + simple-audio-card,frame-master = <&link0_codec>; + + simple-audio-card,cpu { + sound-dai = <&audi2s0 0>; + system-clock-frequency = <19200000>; + }; + + link0_codec: simple-audio-card,codec { + sound-dai = <&max98090>; + clocks = <&audi2s0 CLK_I2S_CDCLK>; + }; + }; +}; + +&audi2s0 { + status = "okay"; +}; + +&clock { + clocks = <&fin_pll>; + assigned-clocks = <&clock CLK_FOUT_EPLL>; + assigned-clock-rates = <192000000>; +}; + +&clock_audss { + assigned-clocks = <&clock_audss EXYNOS_MOUT_AUDSS>, + <&clock_audss EXYNOS_MOUT_I2S>, + <&clock_audss EXYNOS_DOUT_SRP>, + <&clock_audss EXYNOS_DOUT_AUD_BUS>; + + assigned-clock-parents = <&clock CLK_FOUT_EPLL>, + <&clock_audss EXYNOS_MOUT_AUDSS>; + + assigned-clock-rates = <0>, + <0>, + <96000000>, + <19200000>; }; &cpu0_thermal { @@ -440,6 +496,19 @@ }; }; +&i2c_1 { + status = "okay"; + max98090: max98090@10 { + compatible = "maxim,max98090"; + reg = <0x10>; + interrupt-parent = <&gpj3>; + interrupts = <0 IRQ_TYPE_NONE>; + clocks = <&audi2s0 CLK_I2S_CDCLK>; + clock-names = "mclk"; + #sound-dai-cells = <0>; + }; +}; + &mmc_0 { status = "okay"; mmc-pwrseq = <&emmc_pwrseq>; diff --git a/arch/arm/boot/dts/exynos5410-pinctrl.dtsi b/arch/arm/boot/dts/exynos5410-pinctrl.dtsi index a083d23fdee3..ff46a1c27182 100644 --- a/arch/arm/boot/dts/exynos5410-pinctrl.dtsi +++ b/arch/arm/boot/dts/exynos5410-pinctrl.dtsi @@ -615,4 +615,13 @@ interrupt-controller; #interrupt-cells = <2>; }; + + audi2s0_bus: audi2s0-bus { + samsung,pins = "gpz-0", "gpz-1", "gpz-2", "gpz-3", + "gpz-4"; + samsung,pin-function = <2>; + samsung,pin-pud = <0>; + samsung,pin-drv = <0>; + }; + }; diff --git a/arch/arm/boot/dts/exynos5410.dtsi b/arch/arm/boot/dts/exynos5410.dtsi index 137f48464f8b..bb90bbdbe2d9 100644 --- a/arch/arm/boot/dts/exynos5410.dtsi +++ b/arch/arm/boot/dts/exynos5410.dtsi @@ -16,6 +16,7 @@ #include "exynos54xx.dtsi" #include "exynos-syscon-restart.dtsi" #include <dt-bindings/clock/exynos5410.h> +#include <dt-bindings/clock/exynos-audss-clk.h> #include <dt-bindings/interrupt-controller/arm-gic.h> / { @@ -82,10 +83,18 @@ #clock-cells = <1>; }; + clock_audss: audss-clock-controller@3810000 { + compatible = "samsung,exynos5410-audss-clock"; + reg = <0x03810000 0x0C>; + #clock-cells = <1>; + clocks = <&fin_pll>, <&clock CLK_FOUT_EPLL>; + clock-names = "pll_ref", "pll_in"; + }; + tmu_cpu0: tmu@10060000 { compatible = "samsung,exynos5420-tmu"; reg = <0x10060000 0x100>; - interrupts = <GIC_SPI 65 0>; + interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>; clocks = <&clock CLK_TMU>; clock-names = "tmu_apbif"; #include "exynos4412-tmu-sensor-conf.dtsi" @@ -94,7 +103,7 @@ tmu_cpu1: tmu@10064000 { compatible = "samsung,exynos5420-tmu"; reg = <0x10064000 0x100>; - interrupts = <GIC_SPI 183 0>; + interrupts = <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>; clocks = <&clock CLK_TMU>; clock-names = "tmu_apbif"; #include "exynos4412-tmu-sensor-conf.dtsi" @@ -103,7 +112,7 @@ tmu_cpu2: tmu@10068000 { compatible = "samsung,exynos5420-tmu"; reg = <0x10068000 0x100>; - interrupts = <GIC_SPI 184 0>; + interrupts = <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>; clocks = <&clock CLK_TMU>; clock-names = "tmu_apbif"; #include "exynos4412-tmu-sensor-conf.dtsi" @@ -112,7 +121,7 @@ tmu_cpu3: tmu@1006c000 { compatible = "samsung,exynos5420-tmu"; reg = <0x1006c000 0x100>; - interrupts = <GIC_SPI 185 0>; + interrupts = <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>; clocks = <&clock CLK_TMU>; clock-names = "tmu_apbif"; #include "exynos4412-tmu-sensor-conf.dtsi" @@ -121,7 +130,7 @@ mmc_0: mmc@12200000 { compatible = "samsung,exynos5250-dw-mshc"; reg = <0x12200000 0x1000>; - interrupts = <0 75 0>; + interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>; #address-cells = <1>; #size-cells = <0>; clocks = <&clock CLK_MMC0>, <&clock CLK_SCLK_MMC0>; @@ -133,7 +142,7 @@ mmc_1: mmc@12210000 { compatible = "samsung,exynos5250-dw-mshc"; reg = <0x12210000 0x1000>; - interrupts = <0 76 0>; + interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>; #address-cells = <1>; #size-cells = <0>; clocks = <&clock CLK_MMC1>, <&clock CLK_SCLK_MMC1>; @@ -145,7 +154,7 @@ mmc_2: mmc@12220000 { compatible = "samsung,exynos5250-dw-mshc"; reg = <0x12220000 0x1000>; - interrupts = <0 77 0>; + interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>; #address-cells = <1>; #size-cells = <0>; clocks = <&clock CLK_MMC2>, <&clock CLK_SCLK_MMC2>; @@ -157,31 +166,81 @@ pinctrl_0: pinctrl@13400000 { compatible = "samsung,exynos5410-pinctrl"; reg = <0x13400000 0x1000>; - interrupts = <0 45 0>; + interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>; wakeup-interrupt-controller { compatible = "samsung,exynos4210-wakeup-eint"; interrupt-parent = <&gic>; - interrupts = <0 32 0>; + interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>; }; }; pinctrl_1: pinctrl@14000000 { compatible = "samsung,exynos5410-pinctrl"; reg = <0x14000000 0x1000>; - interrupts = <0 46 0>; + interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>; }; pinctrl_2: pinctrl@10d10000 { compatible = "samsung,exynos5410-pinctrl"; reg = <0x10d10000 0x1000>; - interrupts = <0 50 0>; + interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>; }; pinctrl_3: pinctrl@03860000 { compatible = "samsung,exynos5410-pinctrl"; reg = <0x03860000 0x1000>; - interrupts = <0 47 0>; + interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>; + }; + + amba { + #address-cells = <1>; + #size-cells = <1>; + compatible = "simple-bus"; + interrupt-parent = <&gic>; + ranges; + + pdma0: pdma@12680000 { + compatible = "arm,pl330", "arm,primecell"; + reg = <0x121A0000 0x1000>; + interrupts = <GIC_SPI 34 IRQ_TYPE_NONE>; + clocks = <&clock CLK_PDMA0>; + clock-names = "apb_pclk"; + #dma-cells = <1>; + #dma-channels = <8>; + #dma-requests = <32>; + }; + + pdma1: pdma@12690000 { + compatible = "arm,pl330", "arm,primecell"; + reg = <0x121B0000 0x1000>; + interrupts = <GIC_SPI 35 IRQ_TYPE_NONE>; + clocks = <&clock CLK_PDMA1>; + clock-names = "apb_pclk"; + #dma-cells = <1>; + #dma-channels = <8>; + #dma-requests = <32>; + }; + }; + + audi2s0: i2s@03830000 { + compatible = "samsung,exynos5420-i2s"; + reg = <0x03830000 0x100>; + dmas = <&pdma0 10 + &pdma0 9 + &pdma0 8>; + dma-names = "tx", "rx", "tx-sec"; + clocks = <&clock_audss EXYNOS_I2S_BUS>, + <&clock_audss EXYNOS_I2S_BUS>, + <&clock_audss EXYNOS_SCLK_I2S>; + clock-names = "iis", "i2s_opclk0", "i2s_opclk1"; + #clock-cells = <1>; + clock-output-names = "i2s_cdclk0"; + #sound-dai-cells = <1>; + samsung,idma-addr = <0x03000000>; + pinctrl-names = "default"; + pinctrl-0 = <&audi2s0_bus>; + status = "disabled"; }; }; @@ -329,7 +388,7 @@ }; &usbdrd_dwc3_1 { - interrupts = <GIC_SPI 200 0>; + interrupts = <GIC_SPI 200 IRQ_TYPE_LEVEL_HIGH>; }; &usbdrd_phy1 { diff --git a/arch/arm/boot/dts/exynos5420-peach-pit.dts b/arch/arm/boot/dts/exynos5420-peach-pit.dts index ec4a00f1ce01..1f964ec35c5e 100644 --- a/arch/arm/boot/dts/exynos5420-peach-pit.dts +++ b/arch/arm/boot/dts/exynos5420-peach-pit.dts @@ -697,6 +697,7 @@ status = "okay"; }; +/* eMMC flash */ &mmc_0 { status = "okay"; num-slots = <1>; @@ -714,6 +715,7 @@ bus-width = <8>; }; +/* WiFi SDIO module */ &mmc_1 { status = "okay"; num-slots = <1>; @@ -733,6 +735,7 @@ vqmmc-supply = <&buck10_reg>; }; +/* uSD card */ &mmc_2 { status = "okay"; num-slots = <1>; diff --git a/arch/arm/boot/dts/exynos5420.dtsi b/arch/arm/boot/dts/exynos5420.dtsi index 00c4cfa54839..906a1a42a7ea 100644 --- a/arch/arm/boot/dts/exynos5420.dtsi +++ b/arch/arm/boot/dts/exynos5420.dtsi @@ -193,7 +193,7 @@ mfc: codec@11000000 { compatible = "samsung,mfc-v7"; reg = <0x11000000 0x10000>; - interrupts = <0 96 0>; + interrupts = <0 96 IRQ_TYPE_LEVEL_HIGH>; clocks = <&clock CLK_MFC>; clock-names = "mfc"; power-domains = <&mfc_pd>; @@ -203,7 +203,7 @@ mmc_0: mmc@12200000 { compatible = "samsung,exynos5420-dw-mshc-smu"; - interrupts = <0 75 0>; + interrupts = <0 75 IRQ_TYPE_LEVEL_HIGH>; #address-cells = <1>; #size-cells = <0>; reg = <0x12200000 0x2000>; @@ -215,7 +215,7 @@ mmc_1: mmc@12210000 { compatible = "samsung,exynos5420-dw-mshc-smu"; - interrupts = <0 76 0>; + interrupts = <0 76 IRQ_TYPE_LEVEL_HIGH>; #address-cells = <1>; #size-cells = <0>; reg = <0x12210000 0x2000>; @@ -227,7 +227,7 @@ mmc_2: mmc@12220000 { compatible = "samsung,exynos5420-dw-mshc"; - interrupts = <0 77 0>; + interrupts = <0 77 IRQ_TYPE_LEVEL_HIGH>; #address-cells = <1>; #size-cells = <0>; reg = <0x12220000 0x1000>; @@ -320,37 +320,37 @@ pinctrl_0: pinctrl@13400000 { compatible = "samsung,exynos5420-pinctrl"; reg = <0x13400000 0x1000>; - interrupts = <0 45 0>; + interrupts = <0 45 IRQ_TYPE_LEVEL_HIGH>; wakeup-interrupt-controller { compatible = "samsung,exynos4210-wakeup-eint"; interrupt-parent = <&gic>; - interrupts = <0 32 0>; + interrupts = <0 32 IRQ_TYPE_LEVEL_HIGH>; }; }; pinctrl_1: pinctrl@13410000 { compatible = "samsung,exynos5420-pinctrl"; reg = <0x13410000 0x1000>; - interrupts = <0 78 0>; + interrupts = <0 78 IRQ_TYPE_LEVEL_HIGH>; }; pinctrl_2: pinctrl@14000000 { compatible = "samsung,exynos5420-pinctrl"; reg = <0x14000000 0x1000>; - interrupts = <0 46 0>; + interrupts = <0 46 IRQ_TYPE_LEVEL_HIGH>; }; pinctrl_3: pinctrl@14010000 { compatible = "samsung,exynos5420-pinctrl"; reg = <0x14010000 0x1000>; - interrupts = <0 50 0>; + interrupts = <0 50 IRQ_TYPE_LEVEL_HIGH>; }; pinctrl_4: pinctrl@03860000 { compatible = "samsung,exynos5420-pinctrl"; reg = <0x03860000 0x1000>; - interrupts = <0 47 0>; + interrupts = <0 47 IRQ_TYPE_LEVEL_HIGH>; }; amba { @@ -363,7 +363,7 @@ adma: adma@03880000 { compatible = "arm,pl330", "arm,primecell"; reg = <0x03880000 0x1000>; - interrupts = <0 110 0>; + interrupts = <0 110 IRQ_TYPE_LEVEL_HIGH>; clocks = <&clock_audss EXYNOS_ADMA>; clock-names = "apb_pclk"; #dma-cells = <1>; @@ -374,7 +374,7 @@ pdma0: pdma@121A0000 { compatible = "arm,pl330", "arm,primecell"; reg = <0x121A0000 0x1000>; - interrupts = <0 34 0>; + interrupts = <0 34 IRQ_TYPE_LEVEL_HIGH>; clocks = <&clock CLK_PDMA0>; clock-names = "apb_pclk"; #dma-cells = <1>; @@ -385,7 +385,7 @@ pdma1: pdma@121B0000 { compatible = "arm,pl330", "arm,primecell"; reg = <0x121B0000 0x1000>; - interrupts = <0 35 0>; + interrupts = <0 35 IRQ_TYPE_LEVEL_HIGH>; clocks = <&clock CLK_PDMA1>; clock-names = "apb_pclk"; #dma-cells = <1>; @@ -396,7 +396,7 @@ mdma0: mdma@10800000 { compatible = "arm,pl330", "arm,primecell"; reg = <0x10800000 0x1000>; - interrupts = <0 33 0>; + interrupts = <0 33 IRQ_TYPE_LEVEL_HIGH>; clocks = <&clock CLK_MDMA0>; clock-names = "apb_pclk"; #dma-cells = <1>; @@ -407,7 +407,7 @@ mdma1: mdma@11C10000 { compatible = "arm,pl330", "arm,primecell"; reg = <0x11C10000 0x1000>; - interrupts = <0 124 0>; + interrupts = <0 124 IRQ_TYPE_LEVEL_HIGH>; clocks = <&clock CLK_MDMA1>; clock-names = "apb_pclk"; #dma-cells = <1>; @@ -479,7 +479,7 @@ spi_0: spi@12d20000 { compatible = "samsung,exynos4210-spi"; reg = <0x12d20000 0x100>; - interrupts = <0 68 0>; + interrupts = <0 68 IRQ_TYPE_LEVEL_HIGH>; dmas = <&pdma0 5 &pdma0 4>; dma-names = "tx", "rx"; @@ -495,7 +495,7 @@ spi_1: spi@12d30000 { compatible = "samsung,exynos4210-spi"; reg = <0x12d30000 0x100>; - interrupts = <0 69 0>; + interrupts = <0 69 IRQ_TYPE_LEVEL_HIGH>; dmas = <&pdma1 5 &pdma1 4>; dma-names = "tx", "rx"; @@ -511,7 +511,7 @@ spi_2: spi@12d40000 { compatible = "samsung,exynos4210-spi"; reg = <0x12d40000 0x100>; - interrupts = <0 70 0>; + interrupts = <0 70 IRQ_TYPE_LEVEL_HIGH>; dmas = <&pdma0 7 &pdma0 6>; dma-names = "tx", "rx"; @@ -539,7 +539,7 @@ dsi@14500000 { compatible = "samsung,exynos5410-mipi-dsi"; reg = <0x14500000 0x10000>; - interrupts = <0 82 0>; + interrupts = <0 82 IRQ_TYPE_LEVEL_HIGH>; phys = <&mipi_phy 1>; phy-names = "dsim"; clocks = <&clock CLK_DSIM1>, <&clock CLK_SCLK_MIPI1>; @@ -552,7 +552,7 @@ adc: adc@12D10000 { compatible = "samsung,exynos-adc-v2"; reg = <0x12D10000 0x100>; - interrupts = <0 106 0>; + interrupts = <0 106 IRQ_TYPE_LEVEL_HIGH>; clocks = <&clock CLK_TSADC>; clock-names = "adc"; #io-channel-cells = <1>; @@ -564,7 +564,7 @@ hsi2c_8: i2c@12E00000 { compatible = "samsung,exynos5250-hsi2c"; reg = <0x12E00000 0x1000>; - interrupts = <0 87 0>; + interrupts = <0 87 IRQ_TYPE_LEVEL_HIGH>; #address-cells = <1>; #size-cells = <0>; pinctrl-names = "default"; @@ -577,7 +577,7 @@ hsi2c_9: i2c@12E10000 { compatible = "samsung,exynos5250-hsi2c"; reg = <0x12E10000 0x1000>; - interrupts = <0 88 0>; + interrupts = <0 88 IRQ_TYPE_LEVEL_HIGH>; #address-cells = <1>; #size-cells = <0>; pinctrl-names = "default"; @@ -590,7 +590,7 @@ hsi2c_10: i2c@12E20000 { compatible = "samsung,exynos5250-hsi2c"; reg = <0x12E20000 0x1000>; - interrupts = <0 203 0>; + interrupts = <0 203 IRQ_TYPE_LEVEL_HIGH>; #address-cells = <1>; #size-cells = <0>; pinctrl-names = "default"; @@ -603,7 +603,7 @@ hdmi: hdmi@14530000 { compatible = "samsung,exynos5420-hdmi"; reg = <0x14530000 0x70000>; - interrupts = <0 95 0>; + interrupts = <0 95 IRQ_TYPE_LEVEL_HIGH>; clocks = <&clock CLK_HDMI>, <&clock CLK_SCLK_HDMI>, <&clock CLK_DOUT_PIXEL>, <&clock CLK_SCLK_HDMIPHY>, <&clock CLK_MOUT_HDMI>; @@ -622,7 +622,7 @@ mixer: mixer@14450000 { compatible = "samsung,exynos5420-mixer"; reg = <0x14450000 0x10000>; - interrupts = <0 94 0>; + interrupts = <0 94 IRQ_TYPE_LEVEL_HIGH>; clocks = <&clock CLK_MIXER>, <&clock CLK_HDMI>, <&clock CLK_SCLK_HDMI>; clock-names = "mixer", "hdmi", "sclk_hdmi"; @@ -633,7 +633,7 @@ rotator: rotator@11C00000 { compatible = "samsung,exynos5250-rotator"; reg = <0x11C00000 0x64>; - interrupts = <0 84 0>; + interrupts = <0 84 IRQ_TYPE_LEVEL_HIGH>; clocks = <&clock CLK_ROTATOR>; clock-names = "rotator"; iommus = <&sysmmu_rotator>; @@ -642,7 +642,7 @@ gsc_0: video-scaler@13e00000 { compatible = "samsung,exynos5-gsc"; reg = <0x13e00000 0x1000>; - interrupts = <0 85 0>; + interrupts = <0 85 IRQ_TYPE_LEVEL_HIGH>; clocks = <&clock CLK_GSCL0>; clock-names = "gscl"; power-domains = <&gsc_pd>; @@ -652,7 +652,7 @@ gsc_1: video-scaler@13e10000 { compatible = "samsung,exynos5-gsc"; reg = <0x13e10000 0x1000>; - interrupts = <0 86 0>; + interrupts = <0 86 IRQ_TYPE_LEVEL_HIGH>; clocks = <&clock CLK_GSCL1>; clock-names = "gscl"; power-domains = <&gsc_pd>; @@ -662,7 +662,7 @@ jpeg_0: jpeg@11F50000 { compatible = "samsung,exynos5420-jpeg"; reg = <0x11F50000 0x1000>; - interrupts = <0 89 0>; + interrupts = <0 89 IRQ_TYPE_LEVEL_HIGH>; clock-names = "jpeg"; clocks = <&clock CLK_JPEG>; iommus = <&sysmmu_jpeg0>; @@ -671,7 +671,7 @@ jpeg_1: jpeg@11F60000 { compatible = "samsung,exynos5420-jpeg"; reg = <0x11F60000 0x1000>; - interrupts = <0 168 0>; + interrupts = <0 168 IRQ_TYPE_LEVEL_HIGH>; clock-names = "jpeg"; clocks = <&clock CLK_JPEG2>; iommus = <&sysmmu_jpeg1>; @@ -691,7 +691,7 @@ tmu_cpu0: tmu@10060000 { compatible = "samsung,exynos5420-tmu"; reg = <0x10060000 0x100>; - interrupts = <0 65 0>; + interrupts = <0 65 IRQ_TYPE_LEVEL_HIGH>; clocks = <&clock CLK_TMU>; clock-names = "tmu_apbif"; #include "exynos4412-tmu-sensor-conf.dtsi" @@ -700,7 +700,7 @@ tmu_cpu1: tmu@10064000 { compatible = "samsung,exynos5420-tmu"; reg = <0x10064000 0x100>; - interrupts = <0 183 0>; + interrupts = <0 183 IRQ_TYPE_LEVEL_HIGH>; clocks = <&clock CLK_TMU>; clock-names = "tmu_apbif"; #include "exynos4412-tmu-sensor-conf.dtsi" @@ -709,7 +709,7 @@ tmu_cpu2: tmu@10068000 { compatible = "samsung,exynos5420-tmu-ext-triminfo"; reg = <0x10068000 0x100>, <0x1006c000 0x4>; - interrupts = <0 184 0>; + interrupts = <0 184 IRQ_TYPE_LEVEL_HIGH>; clocks = <&clock CLK_TMU>, <&clock CLK_TMU>; clock-names = "tmu_apbif", "tmu_triminfo_apbif"; #include "exynos4412-tmu-sensor-conf.dtsi" @@ -718,7 +718,7 @@ tmu_cpu3: tmu@1006c000 { compatible = "samsung,exynos5420-tmu-ext-triminfo"; reg = <0x1006c000 0x100>, <0x100a0000 0x4>; - interrupts = <0 185 0>; + interrupts = <0 185 IRQ_TYPE_LEVEL_HIGH>; clocks = <&clock CLK_TMU>, <&clock CLK_TMU_GPU>; clock-names = "tmu_apbif", "tmu_triminfo_apbif"; #include "exynos4412-tmu-sensor-conf.dtsi" @@ -727,7 +727,7 @@ tmu_gpu: tmu@100a0000 { compatible = "samsung,exynos5420-tmu-ext-triminfo"; reg = <0x100a0000 0x100>, <0x10068000 0x4>; - interrupts = <0 215 0>; + interrupts = <0 215 IRQ_TYPE_LEVEL_HIGH>; clocks = <&clock CLK_TMU_GPU>, <&clock CLK_TMU>; clock-names = "tmu_apbif", "tmu_triminfo_apbif"; #include "exynos4412-tmu-sensor-conf.dtsi" @@ -799,7 +799,7 @@ sysmmu_scaler1r: sysmmu@0x12890000 { compatible = "samsung,exynos-sysmmu"; reg = <0x12890000 0x1000>; - interrupts = <0 186 0>; + interrupts = <0 186 IRQ_TYPE_LEVEL_HIGH>; clock-names = "sysmmu", "master"; clocks = <&clock CLK_SMMU_MSCL1>, <&clock CLK_MSCL1>; #iommu-cells = <0>; @@ -808,7 +808,7 @@ sysmmu_scaler2r: sysmmu@0x128A0000 { compatible = "samsung,exynos-sysmmu"; reg = <0x128A0000 0x1000>; - interrupts = <0 188 0>; + interrupts = <0 188 IRQ_TYPE_LEVEL_HIGH>; clock-names = "sysmmu", "master"; clocks = <&clock CLK_SMMU_MSCL2>, <&clock CLK_MSCL2>; #iommu-cells = <0>; @@ -867,7 +867,7 @@ sysmmu_jpeg1: sysmmu@0x11F20000 { compatible = "samsung,exynos-sysmmu"; reg = <0x11F20000 0x1000>; - interrupts = <0 169 0>; + interrupts = <0 169 IRQ_TYPE_LEVEL_HIGH>; clock-names = "sysmmu", "master"; clocks = <&clock CLK_SMMU_JPEG2>, <&clock CLK_JPEG2>; #iommu-cells = <0>; @@ -1445,7 +1445,7 @@ }; &usbdrd_dwc3_1 { - interrupts = <GIC_SPI 73 0>; + interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>; }; &usbdrd_phy1 { diff --git a/arch/arm/boot/dts/exynos5440.dtsi b/arch/arm/boot/dts/exynos5440.dtsi index e6bffd13cedd..97c9f0e38526 100644 --- a/arch/arm/boot/dts/exynos5440.dtsi +++ b/arch/arm/boot/dts/exynos5440.dtsi @@ -10,6 +10,8 @@ */ #include <dt-bindings/clock/exynos5440.h> +#include <dt-bindings/interrupt-controller/arm-gic.h> +#include <dt-bindings/interrupt-controller/irq.h> / { compatible = "samsung,exynos5440", "samsung,exynos5"; @@ -41,7 +43,8 @@ <0x2E2000 0x1000>, <0x2E4000 0x2000>, <0x2E6000 0x2000>; - interrupts = <1 9 0xf04>; + interrupts = <GIC_PPI 9 + (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; }; cpus { @@ -72,26 +75,26 @@ arm-pmu { compatible = "arm,cortex-a15-pmu", "arm,cortex-a9-pmu"; - interrupts = <0 52 4>, - <0 53 4>, - <0 54 4>, - <0 55 4>; + interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>; }; timer { compatible = "arm,cortex-a15-timer", "arm,armv7-timer"; - interrupts = <1 13 0xf08>, - <1 14 0xf08>, - <1 11 0xf08>, - <1 10 0xf08>; + interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, + <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, + <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, + <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>; clock-frequency = <50000000>; }; cpufreq@160000 { compatible = "samsung,exynos5440-cpufreq"; reg = <0x160000 0x1000>; - interrupts = <0 57 0>; + interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>; operating-points = < /* KHz uV */ 1500000 1100000 @@ -108,7 +111,7 @@ serial_0: serial@B0000 { compatible = "samsung,exynos4210-uart"; reg = <0xB0000 0x1000>; - interrupts = <0 2 0>; + interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>; clocks = <&clock CLK_B_125>, <&clock CLK_B_125>; clock-names = "uart", "clk_uart_baud0"; }; @@ -116,7 +119,7 @@ serial_1: serial@C0000 { compatible = "samsung,exynos4210-uart"; reg = <0xC0000 0x1000>; - interrupts = <0 3 0>; + interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>; clocks = <&clock CLK_B_125>, <&clock CLK_B_125>; clock-names = "uart", "clk_uart_baud0"; }; @@ -124,7 +127,7 @@ spi_0: spi@D0000 { compatible = "samsung,exynos5440-spi"; reg = <0xD0000 0x100>; - interrupts = <0 4 0>; + interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>; #address-cells = <1>; #size-cells = <0>; samsung,spi-src-clk = <0>; @@ -136,8 +139,14 @@ pin_ctrl: pinctrl@E0000 { compatible = "samsung,exynos5440-pinctrl"; reg = <0xE0000 0x1000>; - interrupts = <0 37 0>, <0 38 0>, <0 39 0>, <0 40 0>, - <0 41 0>, <0 42 0>, <0 43 0>, <0 44 0>; + interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>; interrupt-controller; #interrupt-cells = <2>; #gpio-cells = <2>; @@ -162,7 +171,7 @@ i2c@F0000 { compatible = "samsung,exynos5440-i2c"; reg = <0xF0000 0x1000>; - interrupts = <0 5 0>; + interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>; #address-cells = <1>; #size-cells = <0>; clocks = <&clock CLK_B_125>; @@ -172,7 +181,7 @@ i2c@100000 { compatible = "samsung,exynos5440-i2c"; reg = <0x100000 0x1000>; - interrupts = <0 6 0>; + interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>; #address-cells = <1>; #size-cells = <0>; clocks = <&clock CLK_B_125>; @@ -182,7 +191,7 @@ watchdog@110000 { compatible = "samsung,s3c2410-wdt"; reg = <0x110000 0x1000>; - interrupts = <0 1 0>; + interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>; clocks = <&clock CLK_B_125>; clock-names = "watchdog"; }; @@ -191,7 +200,7 @@ compatible = "snps,dwmac-3.70a"; reg = <0x00230000 0x8000>; interrupt-parent = <&gic>; - interrupts = <0 31 4>; + interrupts = <GIC_SPI 31 4>; interrupt-names = "macirq"; phy-mode = "sgmii"; clocks = <&clock CLK_GMAC0>; @@ -209,7 +218,8 @@ rtc@130000 { compatible = "samsung,s3c6410-rtc"; reg = <0x130000 0x1000>; - interrupts = <0 17 0>, <0 16 0>; + interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>; clocks = <&clock CLK_B_125>; clock-names = "rtc"; }; @@ -217,7 +227,7 @@ tmuctrl_0: tmuctrl@160118 { compatible = "samsung,exynos5440-tmu"; reg = <0x160118 0x230>, <0x160368 0x10>; - interrupts = <0 58 0>; + interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>; clocks = <&clock CLK_B_125>; clock-names = "tmu_apbif"; #include "exynos5440-tmu-sensor-conf.dtsi" @@ -226,7 +236,7 @@ tmuctrl_1: tmuctrl@16011C { compatible = "samsung,exynos5440-tmu"; reg = <0x16011C 0x230>, <0x160368 0x10>; - interrupts = <0 58 0>; + interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>; clocks = <&clock CLK_B_125>; clock-names = "tmu_apbif"; #include "exynos5440-tmu-sensor-conf.dtsi" @@ -235,7 +245,7 @@ tmuctrl_2: tmuctrl@160120 { compatible = "samsung,exynos5440-tmu"; reg = <0x160120 0x230>, <0x160368 0x10>; - interrupts = <0 58 0>; + interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>; clocks = <&clock CLK_B_125>; clock-names = "tmu_apbif"; #include "exynos5440-tmu-sensor-conf.dtsi" @@ -259,7 +269,7 @@ sata@210000 { compatible = "snps,exynos5440-ahci"; reg = <0x210000 0x10000>; - interrupts = <0 30 0>; + interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>; clocks = <&clock CLK_SATA>; clock-names = "sata"; }; @@ -267,7 +277,7 @@ ohci@220000 { compatible = "samsung,exynos5440-ohci"; reg = <0x220000 0x1000>; - interrupts = <0 29 0>; + interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>; clocks = <&clock CLK_USB>; clock-names = "usbhost"; }; @@ -275,7 +285,7 @@ ehci@221000 { compatible = "samsung,exynos5440-ehci"; reg = <0x221000 0x1000>; - interrupts = <0 29 0>; + interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>; clocks = <&clock CLK_USB>; clock-names = "usbhost"; }; @@ -285,7 +295,9 @@ reg = <0x290000 0x1000 0x270000 0x1000 0x271000 0x40>; - interrupts = <0 20 0>, <0 21 0>, <0 22 0>; + interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>; clocks = <&clock CLK_PR0_250_O>, <&clock CLK_PB0_250_O>; clock-names = "pcie", "pcie_bus"; #address-cells = <3>; @@ -306,7 +318,9 @@ reg = <0x2a0000 0x1000 0x272000 0x1000 0x271040 0x40>; - interrupts = <0 23 0>, <0 24 0>, <0 25 0>; + interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>; clocks = <&clock CLK_PR1_250_O>, <&clock CLK_PB0_250_O>; clock-names = "pcie", "pcie_bus"; #address-cells = <3>; diff --git a/arch/arm/boot/dts/exynos54xx.dtsi b/arch/arm/boot/dts/exynos54xx.dtsi index 9d31cdce1959..0389e8a10d0b 100644 --- a/arch/arm/boot/dts/exynos54xx.dtsi +++ b/arch/arm/boot/dts/exynos54xx.dtsi @@ -62,34 +62,34 @@ <1 &combiner 23 4>, <2 &combiner 25 2>, <3 &combiner 25 3>, - <4 &gic 0 120 0>, - <5 &gic 0 121 0>, - <6 &gic 0 122 0>, - <7 &gic 0 123 0>, - <8 &gic 0 128 0>, - <9 &gic 0 129 0>, - <10 &gic 0 130 0>, - <11 &gic 0 131 0>; + <4 &gic 0 120 IRQ_TYPE_LEVEL_HIGH>, + <5 &gic 0 121 IRQ_TYPE_LEVEL_HIGH>, + <6 &gic 0 122 IRQ_TYPE_LEVEL_HIGH>, + <7 &gic 0 123 IRQ_TYPE_LEVEL_HIGH>, + <8 &gic 0 128 IRQ_TYPE_LEVEL_HIGH>, + <9 &gic 0 129 IRQ_TYPE_LEVEL_HIGH>, + <10 &gic 0 130 IRQ_TYPE_LEVEL_HIGH>, + <11 &gic 0 131 IRQ_TYPE_LEVEL_HIGH>; }; }; watchdog: watchdog@101d0000 { compatible = "samsung,exynos5420-wdt"; reg = <0x101d0000 0x100>; - interrupts = <0 42 0>; + interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>; }; sss: sss@10830000 { compatible = "samsung,exynos4210-secss"; reg = <0x10830000 0x300>; - interrupts = <0 112 0>; + interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>; }; /* i2c_0-3 are defined in exynos5.dtsi */ hsi2c_4: i2c@12ca0000 { compatible = "samsung,exynos5250-hsi2c"; reg = <0x12ca0000 0x1000>; - interrupts = <0 60 0>; + interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>; #address-cells = <1>; #size-cells = <0>; status = "disabled"; @@ -98,7 +98,7 @@ hsi2c_5: i2c@12cb0000 { compatible = "samsung,exynos5250-hsi2c"; reg = <0x12cb0000 0x1000>; - interrupts = <0 61 0>; + interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>; #address-cells = <1>; #size-cells = <0>; status = "disabled"; @@ -107,7 +107,7 @@ hsi2c_6: i2c@12cc0000 { compatible = "samsung,exynos5250-hsi2c"; reg = <0x12cc0000 0x1000>; - interrupts = <0 62 0>; + interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>; #address-cells = <1>; #size-cells = <0>; status = "disabled"; @@ -116,7 +116,7 @@ hsi2c_7: i2c@12cd0000 { compatible = "samsung,exynos5250-hsi2c"; reg = <0x12cd0000 0x1000>; - interrupts = <0 63 0>; + interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>; #address-cells = <1>; #size-cells = <0>; status = "disabled"; @@ -131,7 +131,7 @@ usbdrd_dwc3_0: dwc3@12000000 { compatible = "snps,dwc3"; reg = <0x12000000 0x10000>; - interrupts = <0 72 0>; + interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>; phys = <&usbdrd_phy0 0>, <&usbdrd_phy0 1>; phy-names = "usb2-phy", "usb3-phy"; }; @@ -166,7 +166,7 @@ usbhost2: usb@12110000 { compatible = "samsung,exynos4210-ehci"; reg = <0x12110000 0x100>; - interrupts = <0 71 0>; + interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>; #address-cells = <1>; #size-cells = <0>; @@ -179,7 +179,7 @@ usbhost1: usb@12120000 { compatible = "samsung,exynos4210-ohci"; reg = <0x12120000 0x100>; - interrupts = <0 71 0>; + interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>; #address-cells = <1>; #size-cells = <0>; diff --git a/arch/arm/boot/dts/exynos5800-peach-pi.dts b/arch/arm/boot/dts/exynos5800-peach-pi.dts index 01f466816fea..f9ff7f07ae0c 100644 --- a/arch/arm/boot/dts/exynos5800-peach-pi.dts +++ b/arch/arm/boot/dts/exynos5800-peach-pi.dts @@ -665,6 +665,7 @@ status = "okay"; }; +/* eMMC flash */ &mmc_0 { status = "okay"; num-slots = <1>; @@ -683,6 +684,7 @@ bus-width = <8>; }; +/* WiFi SDIO module */ &mmc_1 { status = "okay"; num-slots = <1>; @@ -702,6 +704,7 @@ vqmmc-supply = <&buck10_reg>; }; +/* uSD card */ &mmc_2 { status = "okay"; num-slots = <1>; diff --git a/arch/arm/boot/dts/hi3620.dtsi b/arch/arm/boot/dts/hi3620.dtsi index c85d07e6db61..541d70094544 100644 --- a/arch/arm/boot/dts/hi3620.dtsi +++ b/arch/arm/boot/dts/hi3620.dtsi @@ -11,10 +11,12 @@ * publishhed by the Free Software Foundation. */ -#include "skeleton.dtsi" #include <dt-bindings/clock/hi3620-clock.h> / { + #address-cells = <1>; + #size-cells = <1>; + aliases { serial0 = &uart0; serial1 = &uart1; @@ -537,6 +539,7 @@ reg = <0x803000 0x188>; #address-cells = <1>; #size-cells = <1>; + #pinctrl-cells = <1>; #gpio-range-cells = <3>; ranges; @@ -558,6 +561,7 @@ reg = <0x803800 0x2dc>; #address-cells = <1>; #size-cells = <1>; + #pinctrl-cells = <1>; ranges; pinctrl-single,register-width = <32>; diff --git a/arch/arm/boot/dts/hip01.dtsi b/arch/arm/boot/dts/hip01.dtsi index 4e9562f806a2..9d5fd5cfefa6 100644 --- a/arch/arm/boot/dts/hip01.dtsi +++ b/arch/arm/boot/dts/hip01.dtsi @@ -11,8 +11,6 @@ * published by the Free Software Foundation. */ -#include "skeleton.dtsi" - / { interrupt-parent = <&gic>; #address-cells = <1>; diff --git a/arch/arm/boot/dts/hisi-x5hd2.dtsi b/arch/arm/boot/dts/hisi-x5hd2.dtsi index fdcc23d203e5..506fdc10706d 100644 --- a/arch/arm/boot/dts/hisi-x5hd2.dtsi +++ b/arch/arm/boot/dts/hisi-x5hd2.dtsi @@ -7,10 +7,12 @@ * publishhed by the Free Software Foundation. */ -#include "skeleton.dtsi" #include <dt-bindings/clock/hix5hd2-clock.h> / { + #address-cells = <1>; + #size-cells = <1>; + aliases { serial0 = &uart0; }; diff --git a/arch/arm/boot/dts/imx1.dtsi b/arch/arm/boot/dts/imx1.dtsi index 22f5d1db5b31..b792eee3899b 100644 --- a/arch/arm/boot/dts/imx1.dtsi +++ b/arch/arm/boot/dts/imx1.dtsi @@ -9,7 +9,6 @@ * http://www.gnu.org/copyleft/gpl.html */ -#include "skeleton.dtsi" #include "imx1-pinfunc.h" #include <dt-bindings/clock/imx1-clock.h> @@ -17,6 +16,9 @@ #include <dt-bindings/interrupt-controller/irq.h> / { + #address-cells = <1>; + #size-cells = <1>; + aliases { gpio0 = &gpio1; gpio1 = &gpio2; diff --git a/arch/arm/boot/dts/imx23.dtsi b/arch/arm/boot/dts/imx23.dtsi index 440ee9a4a158..ac2a9da62b6c 100644 --- a/arch/arm/boot/dts/imx23.dtsi +++ b/arch/arm/boot/dts/imx23.dtsi @@ -9,10 +9,12 @@ * http://www.gnu.org/copyleft/gpl.html */ -#include "skeleton.dtsi" #include "imx23-pinfunc.h" / { + #address-cells = <1>; + #size-cells = <1>; + interrupt-parent = <&icoll>; aliases { @@ -464,7 +466,7 @@ reg = <0x80038000 0x2000>; status = "disabled"; }; - }; + }; apbx@80040000 { compatible = "simple-bus"; diff --git a/arch/arm/boot/dts/imx25.dtsi b/arch/arm/boot/dts/imx25.dtsi index af6af8741fe5..831d09a28155 100644 --- a/arch/arm/boot/dts/imx25.dtsi +++ b/arch/arm/boot/dts/imx25.dtsi @@ -9,10 +9,12 @@ * http://www.gnu.org/copyleft/gpl.html */ -#include "skeleton.dtsi" #include "imx25-pinfunc.h" / { + #address-cells = <1>; + #size-cells = <1>; + aliases { ethernet0 = &fec; gpio0 = &gpio1; diff --git a/arch/arm/boot/dts/imx27.dtsi b/arch/arm/boot/dts/imx27.dtsi index f818ea483aeb..9d8b5969ee3b 100644 --- a/arch/arm/boot/dts/imx27.dtsi +++ b/arch/arm/boot/dts/imx27.dtsi @@ -9,7 +9,6 @@ * http://www.gnu.org/copyleft/gpl.html */ -#include "skeleton.dtsi" #include "imx27-pinfunc.h" #include <dt-bindings/clock/imx27-clock.h> @@ -18,6 +17,9 @@ #include <dt-bindings/interrupt-controller/irq.h> / { + #address-cells = <1>; + #size-cells = <1>; + aliases { ethernet0 = &fec; gpio0 = &gpio1; diff --git a/arch/arm/boot/dts/imx28-m28.dtsi b/arch/arm/boot/dts/imx28-m28.dtsi index 214bb1506b53..a69856e41ba4 100644 --- a/arch/arm/boot/dts/imx28-m28.dtsi +++ b/arch/arm/boot/dts/imx28-m28.dtsi @@ -12,8 +12,8 @@ #include "imx28.dtsi" / { - model = "DENX M28"; - compatible = "denx,m28", "fsl,imx28"; + model = "Aries/DENX M28"; + compatible = "aries,m28", "denx,m28", "fsl,imx28"; memory { reg = <0x40000000 0x08000000>; diff --git a/arch/arm/boot/dts/imx28-m28evk.dts b/arch/arm/boot/dts/imx28-m28evk.dts index 8d04e57039bc..dbfb8aab505f 100644 --- a/arch/arm/boot/dts/imx28-m28evk.dts +++ b/arch/arm/boot/dts/imx28-m28evk.dts @@ -13,8 +13,8 @@ #include "imx28-m28.dtsi" / { - model = "DENX M28EVK"; - compatible = "denx,m28evk", "fsl,imx28"; + model = "Aries/DENX M28EVK"; + compatible = "aries,m28evk", "denx,m28evk", "fsl,imx28"; apb@80000000 { apbh@80000000 { diff --git a/arch/arm/boot/dts/imx28.dtsi b/arch/arm/boot/dts/imx28.dtsi index 0ad893bf5f43..3aabf65a6a52 100644 --- a/arch/arm/boot/dts/imx28.dtsi +++ b/arch/arm/boot/dts/imx28.dtsi @@ -10,10 +10,12 @@ */ #include <dt-bindings/gpio/gpio.h> -#include "skeleton.dtsi" #include "imx28-pinfunc.h" / { + #address-cells = <1>; + #size-cells = <1>; + interrupt-parent = <&icoll>; aliases { diff --git a/arch/arm/boot/dts/imx31.dtsi b/arch/arm/boot/dts/imx31.dtsi index 1ce7ae94e7ad..c534c1fd185a 100644 --- a/arch/arm/boot/dts/imx31.dtsi +++ b/arch/arm/boot/dts/imx31.dtsi @@ -9,9 +9,10 @@ * http://www.gnu.org/copyleft/gpl.html */ -#include "skeleton.dtsi" - / { + #address-cells = <1>; + #size-cells = <1>; + aliases { serial0 = &uart1; serial1 = &uart2; diff --git a/arch/arm/boot/dts/imx35.dtsi b/arch/arm/boot/dts/imx35.dtsi index f812d586c5ce..9f40e6229189 100644 --- a/arch/arm/boot/dts/imx35.dtsi +++ b/arch/arm/boot/dts/imx35.dtsi @@ -8,10 +8,12 @@ * Free Software Foundation. */ -#include "skeleton.dtsi" #include "imx35-pinfunc.h" / { + #address-cells = <1>; + #size-cells = <1>; + aliases { ethernet0 = &fec; gpio0 = &gpio1; diff --git a/arch/arm/boot/dts/imx50.dtsi b/arch/arm/boot/dts/imx50.dtsi index 8fe8beeb68a4..fe0221e4cbf7 100644 --- a/arch/arm/boot/dts/imx50.dtsi +++ b/arch/arm/boot/dts/imx50.dtsi @@ -11,11 +11,13 @@ * http://www.gnu.org/copyleft/gpl.html */ -#include "skeleton.dtsi" #include "imx50-pinfunc.h" #include <dt-bindings/clock/imx5-clock.h> / { + #address-cells = <1>; + #size-cells = <1>; + aliases { ethernet0 = &fec; gpio0 = &gpio1; @@ -103,8 +105,8 @@ reg = <0x50004000 0x4000>; interrupts = <1>; clocks = <&clks IMX5_CLK_ESDHC1_IPG_GATE>, - <&clks IMX5_CLK_DUMMY>, - <&clks IMX5_CLK_ESDHC1_PER_GATE>; + <&clks IMX5_CLK_DUMMY>, + <&clks IMX5_CLK_ESDHC1_PER_GATE>; clock-names = "ipg", "ahb", "per"; bus-width = <4>; status = "disabled"; @@ -115,8 +117,8 @@ reg = <0x50008000 0x4000>; interrupts = <2>; clocks = <&clks IMX5_CLK_ESDHC2_IPG_GATE>, - <&clks IMX5_CLK_DUMMY>, - <&clks IMX5_CLK_ESDHC2_PER_GATE>; + <&clks IMX5_CLK_DUMMY>, + <&clks IMX5_CLK_ESDHC2_PER_GATE>; clock-names = "ipg", "ahb", "per"; bus-width = <4>; status = "disabled"; @@ -127,7 +129,7 @@ reg = <0x5000c000 0x4000>; interrupts = <33>; clocks = <&clks IMX5_CLK_UART3_IPG_GATE>, - <&clks IMX5_CLK_UART3_PER_GATE>; + <&clks IMX5_CLK_UART3_PER_GATE>; clock-names = "ipg", "per"; status = "disabled"; }; @@ -139,7 +141,7 @@ reg = <0x50010000 0x4000>; interrupts = <36>; clocks = <&clks IMX5_CLK_ECSPI1_IPG_GATE>, - <&clks IMX5_CLK_ECSPI1_PER_GATE>; + <&clks IMX5_CLK_ECSPI1_PER_GATE>; clock-names = "ipg", "per"; status = "disabled"; }; @@ -164,8 +166,8 @@ reg = <0x50020000 0x4000>; interrupts = <3>; clocks = <&clks IMX5_CLK_ESDHC3_IPG_GATE>, - <&clks IMX5_CLK_DUMMY>, - <&clks IMX5_CLK_ESDHC3_PER_GATE>; + <&clks IMX5_CLK_DUMMY>, + <&clks IMX5_CLK_ESDHC3_PER_GATE>; clock-names = "ipg", "ahb", "per"; bus-width = <4>; status = "disabled"; @@ -176,8 +178,8 @@ reg = <0x50024000 0x4000>; interrupts = <4>; clocks = <&clks IMX5_CLK_ESDHC4_IPG_GATE>, - <&clks IMX5_CLK_DUMMY>, - <&clks IMX5_CLK_ESDHC4_PER_GATE>; + <&clks IMX5_CLK_DUMMY>, + <&clks IMX5_CLK_ESDHC4_PER_GATE>; clock-names = "ipg", "ahb", "per"; bus-width = <4>; status = "disabled"; @@ -279,7 +281,7 @@ reg = <0x53fa0000 0x4000>; interrupts = <39>; clocks = <&clks IMX5_CLK_GPT_IPG_GATE>, - <&clks IMX5_CLK_GPT_HF_GATE>; + <&clks IMX5_CLK_GPT_HF_GATE>; clock-names = "ipg", "per"; }; @@ -298,7 +300,7 @@ compatible = "fsl,imx50-pwm", "fsl,imx27-pwm"; reg = <0x53fb4000 0x4000>; clocks = <&clks IMX5_CLK_PWM1_IPG_GATE>, - <&clks IMX5_CLK_PWM1_HF_GATE>; + <&clks IMX5_CLK_PWM1_HF_GATE>; clock-names = "ipg", "per"; interrupts = <61>; }; @@ -308,7 +310,7 @@ compatible = "fsl,imx50-pwm", "fsl,imx27-pwm"; reg = <0x53fb8000 0x4000>; clocks = <&clks IMX5_CLK_PWM2_IPG_GATE>, - <&clks IMX5_CLK_PWM2_HF_GATE>; + <&clks IMX5_CLK_PWM2_HF_GATE>; clock-names = "ipg", "per"; interrupts = <94>; }; @@ -318,7 +320,7 @@ reg = <0x53fbc000 0x4000>; interrupts = <31>; clocks = <&clks IMX5_CLK_UART1_IPG_GATE>, - <&clks IMX5_CLK_UART1_PER_GATE>; + <&clks IMX5_CLK_UART1_PER_GATE>; clock-names = "ipg", "per"; status = "disabled"; }; @@ -328,7 +330,7 @@ reg = <0x53fc0000 0x4000>; interrupts = <32>; clocks = <&clks IMX5_CLK_UART2_IPG_GATE>, - <&clks IMX5_CLK_UART2_PER_GATE>; + <&clks IMX5_CLK_UART2_PER_GATE>; clock-names = "ipg", "per"; status = "disabled"; }; @@ -383,7 +385,7 @@ reg = <0x53ff0000 0x4000>; interrupts = <13>; clocks = <&clks IMX5_CLK_UART4_IPG_GATE>, - <&clks IMX5_CLK_UART4_PER_GATE>; + <&clks IMX5_CLK_UART4_PER_GATE>; clock-names = "ipg", "per"; status = "disabled"; }; @@ -401,7 +403,7 @@ reg = <0x63f90000 0x4000>; interrupts = <86>; clocks = <&clks IMX5_CLK_UART5_IPG_GATE>, - <&clks IMX5_CLK_UART5_PER_GATE>; + <&clks IMX5_CLK_UART5_PER_GATE>; clock-names = "ipg", "per"; status = "disabled"; }; @@ -420,7 +422,7 @@ reg = <0x63fac000 0x4000>; interrupts = <37>; clocks = <&clks IMX5_CLK_ECSPI2_IPG_GATE>, - <&clks IMX5_CLK_ECSPI2_PER_GATE>; + <&clks IMX5_CLK_ECSPI2_PER_GATE>; clock-names = "ipg", "per"; status = "disabled"; }; @@ -430,7 +432,7 @@ reg = <0x63fb0000 0x4000>; interrupts = <6>; clocks = <&clks IMX5_CLK_SDMA_GATE>, - <&clks IMX5_CLK_SDMA_GATE>; + <&clks IMX5_CLK_SDMA_GATE>; clock-names = "ipg", "ahb"; fsl,sdma-ram-script-name = "imx/sdma/sdma-imx50.bin"; }; @@ -442,7 +444,7 @@ reg = <0x63fc0000 0x4000>; interrupts = <38>; clocks = <&clks IMX5_CLK_CSPI_IPG_GATE>, - <&clks IMX5_CLK_CSPI_IPG_GATE>; + <&clks IMX5_CLK_CSPI_IPG_GATE>; clock-names = "ipg", "per"; status = "disabled"; }; @@ -492,8 +494,8 @@ reg = <0x63fec000 0x4000>; interrupts = <87>; clocks = <&clks IMX5_CLK_FEC_GATE>, - <&clks IMX5_CLK_FEC_GATE>, - <&clks IMX5_CLK_FEC_GATE>; + <&clks IMX5_CLK_FEC_GATE>, + <&clks IMX5_CLK_FEC_GATE>; clock-names = "ipg", "ahb", "ptp"; status = "disabled"; }; diff --git a/arch/arm/boot/dts/imx51.dtsi b/arch/arm/boot/dts/imx51.dtsi index f46fe9bf0bcb..33526cade735 100644 --- a/arch/arm/boot/dts/imx51.dtsi +++ b/arch/arm/boot/dts/imx51.dtsi @@ -10,7 +10,6 @@ * http://www.gnu.org/copyleft/gpl.html */ -#include "skeleton.dtsi" #include "imx51-pinfunc.h" #include <dt-bindings/clock/imx5-clock.h> #include <dt-bindings/gpio/gpio.h> @@ -18,6 +17,9 @@ #include <dt-bindings/interrupt-controller/irq.h> / { + #address-cells = <1>; + #size-cells = <1>; + aliases { ethernet0 = &fec; gpio0 = &gpio1; @@ -130,8 +132,8 @@ reg = <0x40000000 0x20000000>; interrupts = <11 10>; clocks = <&clks IMX5_CLK_IPU_GATE>, - <&clks IMX5_CLK_IPU_DI0_GATE>, - <&clks IMX5_CLK_IPU_DI1_GATE>; + <&clks IMX5_CLK_IPU_DI0_GATE>, + <&clks IMX5_CLK_IPU_DI1_GATE>; clock-names = "bus", "di0", "di1"; resets = <&src 2>; @@ -169,8 +171,8 @@ reg = <0x70004000 0x4000>; interrupts = <1>; clocks = <&clks IMX5_CLK_ESDHC1_IPG_GATE>, - <&clks IMX5_CLK_DUMMY>, - <&clks IMX5_CLK_ESDHC1_PER_GATE>; + <&clks IMX5_CLK_DUMMY>, + <&clks IMX5_CLK_ESDHC1_PER_GATE>; clock-names = "ipg", "ahb", "per"; status = "disabled"; }; @@ -180,8 +182,8 @@ reg = <0x70008000 0x4000>; interrupts = <2>; clocks = <&clks IMX5_CLK_ESDHC2_IPG_GATE>, - <&clks IMX5_CLK_DUMMY>, - <&clks IMX5_CLK_ESDHC2_PER_GATE>; + <&clks IMX5_CLK_DUMMY>, + <&clks IMX5_CLK_ESDHC2_PER_GATE>; clock-names = "ipg", "ahb", "per"; bus-width = <4>; status = "disabled"; @@ -192,7 +194,7 @@ reg = <0x7000c000 0x4000>; interrupts = <33>; clocks = <&clks IMX5_CLK_UART3_IPG_GATE>, - <&clks IMX5_CLK_UART3_PER_GATE>; + <&clks IMX5_CLK_UART3_PER_GATE>; clock-names = "ipg", "per"; status = "disabled"; }; @@ -204,7 +206,7 @@ reg = <0x70010000 0x4000>; interrupts = <36>; clocks = <&clks IMX5_CLK_ECSPI1_IPG_GATE>, - <&clks IMX5_CLK_ECSPI1_PER_GATE>; + <&clks IMX5_CLK_ECSPI1_PER_GATE>; clock-names = "ipg", "per"; status = "disabled"; }; @@ -229,8 +231,8 @@ reg = <0x70020000 0x4000>; interrupts = <3>; clocks = <&clks IMX5_CLK_ESDHC3_IPG_GATE>, - <&clks IMX5_CLK_DUMMY>, - <&clks IMX5_CLK_ESDHC3_PER_GATE>; + <&clks IMX5_CLK_DUMMY>, + <&clks IMX5_CLK_ESDHC3_PER_GATE>; clock-names = "ipg", "ahb", "per"; bus-width = <4>; status = "disabled"; @@ -241,8 +243,8 @@ reg = <0x70024000 0x4000>; interrupts = <4>; clocks = <&clks IMX5_CLK_ESDHC4_IPG_GATE>, - <&clks IMX5_CLK_DUMMY>, - <&clks IMX5_CLK_ESDHC4_PER_GATE>; + <&clks IMX5_CLK_DUMMY>, + <&clks IMX5_CLK_ESDHC4_PER_GATE>; clock-names = "ipg", "ahb", "per"; bus-width = <4>; status = "disabled"; @@ -364,7 +366,7 @@ reg = <0x73fa0000 0x4000>; interrupts = <39>; clocks = <&clks IMX5_CLK_GPT_IPG_GATE>, - <&clks IMX5_CLK_GPT_HF_GATE>; + <&clks IMX5_CLK_GPT_HF_GATE>; clock-names = "ipg", "per"; }; @@ -378,7 +380,7 @@ compatible = "fsl,imx51-pwm", "fsl,imx27-pwm"; reg = <0x73fb4000 0x4000>; clocks = <&clks IMX5_CLK_PWM1_IPG_GATE>, - <&clks IMX5_CLK_PWM1_HF_GATE>; + <&clks IMX5_CLK_PWM1_HF_GATE>; clock-names = "ipg", "per"; interrupts = <61>; }; @@ -388,7 +390,7 @@ compatible = "fsl,imx51-pwm", "fsl,imx27-pwm"; reg = <0x73fb8000 0x4000>; clocks = <&clks IMX5_CLK_PWM2_IPG_GATE>, - <&clks IMX5_CLK_PWM2_HF_GATE>; + <&clks IMX5_CLK_PWM2_HF_GATE>; clock-names = "ipg", "per"; interrupts = <94>; }; @@ -398,7 +400,7 @@ reg = <0x73fbc000 0x4000>; interrupts = <31>; clocks = <&clks IMX5_CLK_UART1_IPG_GATE>, - <&clks IMX5_CLK_UART1_PER_GATE>; + <&clks IMX5_CLK_UART1_PER_GATE>; clock-names = "ipg", "per"; status = "disabled"; }; @@ -408,7 +410,7 @@ reg = <0x73fc0000 0x4000>; interrupts = <32>; clocks = <&clks IMX5_CLK_UART2_IPG_GATE>, - <&clks IMX5_CLK_UART2_PER_GATE>; + <&clks IMX5_CLK_UART2_PER_GATE>; clock-names = "ipg", "per"; status = "disabled"; }; @@ -456,7 +458,7 @@ reg = <0x83fac000 0x4000>; interrupts = <37>; clocks = <&clks IMX5_CLK_ECSPI2_IPG_GATE>, - <&clks IMX5_CLK_ECSPI2_PER_GATE>; + <&clks IMX5_CLK_ECSPI2_PER_GATE>; clock-names = "ipg", "per"; status = "disabled"; }; @@ -466,7 +468,7 @@ reg = <0x83fb0000 0x4000>; interrupts = <6>; clocks = <&clks IMX5_CLK_SDMA_GATE>, - <&clks IMX5_CLK_SDMA_GATE>; + <&clks IMX5_CLK_SDMA_GATE>; clock-names = "ipg", "ahb"; #dma-cells = <3>; fsl,sdma-ram-script-name = "imx/sdma/sdma-imx51.bin"; @@ -479,7 +481,7 @@ reg = <0x83fc0000 0x4000>; interrupts = <38>; clocks = <&clks IMX5_CLK_CSPI_IPG_GATE>, - <&clks IMX5_CLK_CSPI_IPG_GATE>; + <&clks IMX5_CLK_CSPI_IPG_GATE>; clock-names = "ipg", "per"; status = "disabled"; }; @@ -582,8 +584,8 @@ reg = <0x83fec000 0x4000>; interrupts = <87>; clocks = <&clks IMX5_CLK_FEC_GATE>, - <&clks IMX5_CLK_FEC_GATE>, - <&clks IMX5_CLK_FEC_GATE>; + <&clks IMX5_CLK_FEC_GATE>, + <&clks IMX5_CLK_FEC_GATE>; clock-names = "ipg", "ahb", "ptp"; status = "disabled"; }; diff --git a/arch/arm/boot/dts/imx53-m53.dtsi b/arch/arm/boot/dts/imx53-m53.dtsi index d259f57bfd98..ec390aa562c3 100644 --- a/arch/arm/boot/dts/imx53-m53.dtsi +++ b/arch/arm/boot/dts/imx53-m53.dtsi @@ -12,8 +12,8 @@ #include "imx53.dtsi" / { - model = "DENX M53"; - compatible = "denx,imx53-m53", "fsl,imx53"; + model = "Aries/DENX M53"; + compatible = "aries,imx53-m53", "denx,imx53-m53", "fsl,imx53"; memory { reg = <0x70000000 0x20000000>, diff --git a/arch/arm/boot/dts/imx53-m53evk.dts b/arch/arm/boot/dts/imx53-m53evk.dts index dcee1e0f968f..4347a321c782 100644 --- a/arch/arm/boot/dts/imx53-m53evk.dts +++ b/arch/arm/boot/dts/imx53-m53evk.dts @@ -13,8 +13,8 @@ #include "imx53-m53.dtsi" / { - model = "DENX M53EVK"; - compatible = "denx,imx53-m53evk", "fsl,imx53"; + model = "Aries/DENX M53EVK"; + compatible = "aries,imx53-m53evk", "denx,imx53-m53evk", "fsl,imx53"; display1: display@di1 { compatible = "fsl,imx-parallel-display"; diff --git a/arch/arm/boot/dts/imx53.dtsi b/arch/arm/boot/dts/imx53.dtsi index 0777b41cdfe8..ca51dc03e327 100644 --- a/arch/arm/boot/dts/imx53.dtsi +++ b/arch/arm/boot/dts/imx53.dtsi @@ -10,7 +10,6 @@ * http://www.gnu.org/copyleft/gpl.html */ -#include "skeleton.dtsi" #include "imx53-pinfunc.h" #include <dt-bindings/clock/imx5-clock.h> #include <dt-bindings/gpio/gpio.h> @@ -18,6 +17,9 @@ #include <dt-bindings/interrupt-controller/irq.h> / { + #address-cells = <1>; + #size-cells = <1>; + aliases { ethernet0 = &fec; gpio0 = &gpio1; @@ -131,8 +133,8 @@ reg = <0x18000000 0x08000000>; interrupts = <11 10>; clocks = <&clks IMX5_CLK_IPU_GATE>, - <&clks IMX5_CLK_IPU_DI0_GATE>, - <&clks IMX5_CLK_IPU_DI1_GATE>; + <&clks IMX5_CLK_IPU_DI0_GATE>, + <&clks IMX5_CLK_IPU_DI1_GATE>; clock-names = "bus", "di0", "di1"; resets = <&src 2>; @@ -199,8 +201,8 @@ reg = <0x50004000 0x4000>; interrupts = <1>; clocks = <&clks IMX5_CLK_ESDHC1_IPG_GATE>, - <&clks IMX5_CLK_DUMMY>, - <&clks IMX5_CLK_ESDHC1_PER_GATE>; + <&clks IMX5_CLK_DUMMY>, + <&clks IMX5_CLK_ESDHC1_PER_GATE>; clock-names = "ipg", "ahb", "per"; bus-width = <4>; status = "disabled"; @@ -211,8 +213,8 @@ reg = <0x50008000 0x4000>; interrupts = <2>; clocks = <&clks IMX5_CLK_ESDHC2_IPG_GATE>, - <&clks IMX5_CLK_DUMMY>, - <&clks IMX5_CLK_ESDHC2_PER_GATE>; + <&clks IMX5_CLK_DUMMY>, + <&clks IMX5_CLK_ESDHC2_PER_GATE>; clock-names = "ipg", "ahb", "per"; bus-width = <4>; status = "disabled"; @@ -223,7 +225,7 @@ reg = <0x5000c000 0x4000>; interrupts = <33>; clocks = <&clks IMX5_CLK_UART3_IPG_GATE>, - <&clks IMX5_CLK_UART3_PER_GATE>; + <&clks IMX5_CLK_UART3_PER_GATE>; clock-names = "ipg", "per"; dmas = <&sdma 42 4 0>, <&sdma 43 4 0>; dma-names = "rx", "tx"; @@ -237,7 +239,7 @@ reg = <0x50010000 0x4000>; interrupts = <36>; clocks = <&clks IMX5_CLK_ECSPI1_IPG_GATE>, - <&clks IMX5_CLK_ECSPI1_PER_GATE>; + <&clks IMX5_CLK_ECSPI1_PER_GATE>; clock-names = "ipg", "per"; status = "disabled"; }; @@ -264,8 +266,8 @@ reg = <0x50020000 0x4000>; interrupts = <3>; clocks = <&clks IMX5_CLK_ESDHC3_IPG_GATE>, - <&clks IMX5_CLK_DUMMY>, - <&clks IMX5_CLK_ESDHC3_PER_GATE>; + <&clks IMX5_CLK_DUMMY>, + <&clks IMX5_CLK_ESDHC3_PER_GATE>; clock-names = "ipg", "ahb", "per"; bus-width = <4>; status = "disabled"; @@ -276,8 +278,8 @@ reg = <0x50024000 0x4000>; interrupts = <4>; clocks = <&clks IMX5_CLK_ESDHC4_IPG_GATE>, - <&clks IMX5_CLK_DUMMY>, - <&clks IMX5_CLK_ESDHC4_PER_GATE>; + <&clks IMX5_CLK_DUMMY>, + <&clks IMX5_CLK_ESDHC4_PER_GATE>; clock-names = "ipg", "ahb", "per"; bus-width = <4>; status = "disabled"; @@ -419,7 +421,7 @@ reg = <0x53fa0000 0x4000>; interrupts = <39>; clocks = <&clks IMX5_CLK_GPT_IPG_GATE>, - <&clks IMX5_CLK_GPT_HF_GATE>; + <&clks IMX5_CLK_GPT_HF_GATE>; clock-names = "ipg", "per"; }; @@ -440,11 +442,11 @@ reg = <0x53fa8008 0x4>; gpr = <&gpr>; clocks = <&clks IMX5_CLK_LDB_DI0_SEL>, - <&clks IMX5_CLK_LDB_DI1_SEL>, - <&clks IMX5_CLK_IPU_DI0_SEL>, - <&clks IMX5_CLK_IPU_DI1_SEL>, - <&clks IMX5_CLK_LDB_DI0_GATE>, - <&clks IMX5_CLK_LDB_DI1_GATE>; + <&clks IMX5_CLK_LDB_DI1_SEL>, + <&clks IMX5_CLK_IPU_DI0_SEL>, + <&clks IMX5_CLK_IPU_DI1_SEL>, + <&clks IMX5_CLK_LDB_DI0_GATE>, + <&clks IMX5_CLK_LDB_DI1_GATE>; clock-names = "di0_pll", "di1_pll", "di0_sel", "di1_sel", "di0", "di1"; @@ -486,7 +488,7 @@ compatible = "fsl,imx53-pwm", "fsl,imx27-pwm"; reg = <0x53fb4000 0x4000>; clocks = <&clks IMX5_CLK_PWM1_IPG_GATE>, - <&clks IMX5_CLK_PWM1_HF_GATE>; + <&clks IMX5_CLK_PWM1_HF_GATE>; clock-names = "ipg", "per"; interrupts = <61>; }; @@ -496,7 +498,7 @@ compatible = "fsl,imx53-pwm", "fsl,imx27-pwm"; reg = <0x53fb8000 0x4000>; clocks = <&clks IMX5_CLK_PWM2_IPG_GATE>, - <&clks IMX5_CLK_PWM2_HF_GATE>; + <&clks IMX5_CLK_PWM2_HF_GATE>; clock-names = "ipg", "per"; interrupts = <94>; }; @@ -506,7 +508,7 @@ reg = <0x53fbc000 0x4000>; interrupts = <31>; clocks = <&clks IMX5_CLK_UART1_IPG_GATE>, - <&clks IMX5_CLK_UART1_PER_GATE>; + <&clks IMX5_CLK_UART1_PER_GATE>; clock-names = "ipg", "per"; dmas = <&sdma 18 4 0>, <&sdma 19 4 0>; dma-names = "rx", "tx"; @@ -518,7 +520,7 @@ reg = <0x53fc0000 0x4000>; interrupts = <32>; clocks = <&clks IMX5_CLK_UART2_IPG_GATE>, - <&clks IMX5_CLK_UART2_PER_GATE>; + <&clks IMX5_CLK_UART2_PER_GATE>; clock-names = "ipg", "per"; dmas = <&sdma 12 4 0>, <&sdma 13 4 0>; dma-names = "rx", "tx"; @@ -530,7 +532,7 @@ reg = <0x53fc8000 0x4000>; interrupts = <82>; clocks = <&clks IMX5_CLK_CAN1_IPG_GATE>, - <&clks IMX5_CLK_CAN1_SERIAL_GATE>; + <&clks IMX5_CLK_CAN1_SERIAL_GATE>; clock-names = "ipg", "per"; status = "disabled"; }; @@ -540,7 +542,7 @@ reg = <0x53fcc000 0x4000>; interrupts = <83>; clocks = <&clks IMX5_CLK_CAN2_IPG_GATE>, - <&clks IMX5_CLK_CAN2_SERIAL_GATE>; + <&clks IMX5_CLK_CAN2_SERIAL_GATE>; clock-names = "ipg", "per"; status = "disabled"; }; @@ -603,7 +605,7 @@ reg = <0x53ff0000 0x4000>; interrupts = <13>; clocks = <&clks IMX5_CLK_UART4_IPG_GATE>, - <&clks IMX5_CLK_UART4_PER_GATE>; + <&clks IMX5_CLK_UART4_PER_GATE>; clock-names = "ipg", "per"; dmas = <&sdma 2 4 0>, <&sdma 3 4 0>; dma-names = "rx", "tx"; @@ -635,7 +637,7 @@ reg = <0x63f90000 0x4000>; interrupts = <86>; clocks = <&clks IMX5_CLK_UART5_IPG_GATE>, - <&clks IMX5_CLK_UART5_PER_GATE>; + <&clks IMX5_CLK_UART5_PER_GATE>; clock-names = "ipg", "per"; dmas = <&sdma 16 4 0>, <&sdma 17 4 0>; dma-names = "rx", "tx"; @@ -656,7 +658,7 @@ reg = <0x63fac000 0x4000>; interrupts = <37>; clocks = <&clks IMX5_CLK_ECSPI2_IPG_GATE>, - <&clks IMX5_CLK_ECSPI2_PER_GATE>; + <&clks IMX5_CLK_ECSPI2_PER_GATE>; clock-names = "ipg", "per"; status = "disabled"; }; @@ -666,7 +668,7 @@ reg = <0x63fb0000 0x4000>; interrupts = <6>; clocks = <&clks IMX5_CLK_SDMA_GATE>, - <&clks IMX5_CLK_SDMA_GATE>; + <&clks IMX5_CLK_SDMA_GATE>; clock-names = "ipg", "ahb"; #dma-cells = <3>; fsl,sdma-ram-script-name = "imx/sdma/sdma-imx53.bin"; @@ -679,7 +681,7 @@ reg = <0x63fc0000 0x4000>; interrupts = <38>; clocks = <&clks IMX5_CLK_CSPI_IPG_GATE>, - <&clks IMX5_CLK_CSPI_IPG_GATE>; + <&clks IMX5_CLK_CSPI_IPG_GATE>; clock-names = "ipg", "per"; status = "disabled"; }; @@ -755,8 +757,8 @@ reg = <0x63fec000 0x4000>; interrupts = <87>; clocks = <&clks IMX5_CLK_FEC_GATE>, - <&clks IMX5_CLK_FEC_GATE>, - <&clks IMX5_CLK_FEC_GATE>; + <&clks IMX5_CLK_FEC_GATE>, + <&clks IMX5_CLK_FEC_GATE>; clock-names = "ipg", "ahb", "ptp"; status = "disabled"; }; @@ -766,7 +768,7 @@ reg = <0x63ff0000 0x1000>; interrupts = <92>; clocks = <&clks IMX5_CLK_TVE_GATE>, - <&clks IMX5_CLK_IPU_DI1_SEL>; + <&clks IMX5_CLK_IPU_DI1_SEL>; clock-names = "tve", "di_sel"; status = "disabled"; @@ -782,7 +784,7 @@ reg = <0x63ff4000 0x1000>; interrupts = <9>; clocks = <&clks IMX5_CLK_VPU_REFERENCE_GATE>, - <&clks IMX5_CLK_VPU_GATE>; + <&clks IMX5_CLK_VPU_GATE>; clock-names = "per", "ahb"; resets = <&src 1>; iram = <&ocram>; @@ -793,7 +795,7 @@ reg = <0x63ff8000 0x4000>; interrupts = <19 20>; clocks = <&clks IMX5_CLK_SAHARA_IPG_GATE>, - <&clks IMX5_CLK_SAHARA_IPG_GATE>; + <&clks IMX5_CLK_SAHARA_IPG_GATE>; clock-names = "ipg", "ahb"; }; }; diff --git a/arch/arm/boot/dts/imx6dl-colibri-eval-v3.dts b/arch/arm/boot/dts/imx6dl-colibri-eval-v3.dts new file mode 100644 index 000000000000..e0c21727866d --- /dev/null +++ b/arch/arm/boot/dts/imx6dl-colibri-eval-v3.dts @@ -0,0 +1,253 @@ +/* + * Copyright 2014-2016 Toradex AG + * Copyright 2012 Freescale Semiconductor, Inc. + * Copyright 2011 Linaro Ltd. + * + * This file is dual-licensed: you can use it either under the terms + * of the GPL or the X11 license, at your option. Note that this dual + * licensing only applies to this file, and not this project as a + * whole. + * + * a) This file is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * version 2 as published by the Free Software Foundation. + * + * This file is distributed in the hope that it will be useful + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * Or, alternatively + * + * b) Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use + * copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following + * conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED , WITHOUT WARRANTY OF ANY KIND + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + */ + +/dts-v1/; + +#include <dt-bindings/input/input.h> +#include <dt-bindings/interrupt-controller/irq.h> +#include "imx6dl.dtsi" +#include "imx6qdl-colibri.dtsi" + +/ { + model = "Toradex Colibri iMX6DL/S on Colibri Evaluation Board V3"; + compatible = "toradex,colibri_imx6dl-eval-v3", "toradex,colibri_imx6dl", + "fsl,imx6dl"; + + aliases { + i2c0 = &i2c2; + i2c1 = &i2c3; + }; + + aliases { + rtc0 = &rtc_i2c; + rtc1 = &snvs_rtc; + }; + + clocks { + /* Fixed crystal dedicated to mcp251x */ + clk16m: clk@1 { + compatible = "fixed-clock"; + reg = <1>; + #clock-cells = <0>; + clock-frequency = <16000000>; + clock-output-names = "clk16m"; + }; + }; + + gpio-keys { + compatible = "gpio-keys"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_gpio_keys>; + + wakeup { + label = "Wake-Up"; + gpios = <&gpio2 22 GPIO_ACTIVE_HIGH>; /* SODIMM 45 */ + linux,code = <KEY_WAKEUP>; + debounce-interval = <10>; + wakeup-source; + }; + }; + + lcd_display: display@di0 { + compatible = "fsl,imx-parallel-display"; + #address-cells = <1>; + #size-cells = <0>; + interface-pix-fmt = "bgr666"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_ipu1_lcdif>; + status = "okay"; + + port@0 { + reg = <0>; + + lcd_display_in: endpoint { + remote-endpoint = <&ipu1_di0_disp0>; + }; + }; + + port@1 { + reg = <1>; + + lcd_display_out: endpoint { + remote-endpoint = <&lcd_panel_in>; + }; + }; + }; + + panel: panel { + /* + * edt,et057090dhu: EDT 5.7" LCD TFT + * edt,et070080dh6: EDT 7.0" LCD TFT + */ + compatible = "edt,et057090dhu"; + backlight = <&backlight>; + + port { + lcd_panel_in: endpoint { + remote-endpoint = <&lcd_display_out>; + }; + }; + }; +}; + +&backlight { + brightness-levels = <0 127 191 223 239 247 251 255>; + default-brightness-level = <1>; + status = "okay"; +}; + +/* Colibri SSP */ +&ecspi4 { + status = "okay"; + + mcp251x0: mcp251x@1 { + compatible = "microchip,mcp2515"; + reg = <0>; + clocks = <&clk16m>; + interrupt-parent = <&gpio3>; + interrupts = <27 0x2>; + spi-max-frequency = <10000000>; + status = "okay"; + }; +}; + +&hdmi { + status = "okay"; +}; + +/* + * Colibri I2C: I2C3_SDA/SCL on SODIMM 194/196 (e.g. RTC on carrier board) + */ +&i2c3 { + status = "okay"; + + /* M41T0M6 real time clock on carrier board */ + rtc_i2c: rtc@68 { + compatible = "st,m41t00"; + reg = <0x68>; + }; +}; + +&ipu1_di0_disp0 { + remote-endpoint = <&lcd_display_in>; +}; + +&pwm1 { + status = "okay"; +}; + +&pwm2 { + status = "okay"; +}; + +&pwm3 { + status = "okay"; +}; + +&pwm4 { + status = "okay"; +}; + +®_usb_host_vbus { + status = "okay"; +}; + +&uart1 { + status = "okay"; +}; + +&uart2 { + status = "okay"; +}; + +&uart3 { + status = "okay"; +}; + +&usbh1 { + vbus-supply = <®_usb_host_vbus>; + status = "okay"; +}; + +&usbotg { + status = "okay"; +}; + +/* Colibri MMC */ +&usdhc1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_mmc_cd>; + cd-gpios = <&gpio2 5 GPIO_ACTIVE_LOW>; /* MMCD */ + status = "okay"; +}; + +&weim { + status = "okay"; + + /* weim memory map: 32MB on CS0, 32MB on CS1, 32MB on CS2 */ + ranges = <0 0 0x08000000 0x02000000 + 1 0 0x0a000000 0x02000000 + 2 0 0x0c000000 0x02000000>; + + /* SRAM on Colibri nEXT_CS0 */ + sram@0,0 { + compatible = "cypress,cy7c1019dv33-10zsxi, mtd-ram"; + reg = <0 0 0x00010000>; + #address-cells = <1>; + #size-cells = <1>; + bank-width = <2>; + fsl,weim-cs-timing = <0x00010081 0x00000000 0x04000000 + 0x00000000 0x04000040 0x00000000>; + }; + + /* SRAM on Colibri nEXT_CS1 */ + sram@1,0 { + compatible = "cypress,cy7c1019dv33-10zsxi, mtd-ram"; + reg = <1 0 0x00010000>; + #address-cells = <1>; + #size-cells = <1>; + bank-width = <2>; + fsl,weim-cs-timing = <0x00010081 0x00000000 0x04000000 + 0x00000000 0x04000040 0x00000000>; + }; +}; diff --git a/arch/arm/boot/dts/imx6dl-icore.dts b/arch/arm/boot/dts/imx6dl-icore.dts new file mode 100644 index 000000000000..aec332c14af1 --- /dev/null +++ b/arch/arm/boot/dts/imx6dl-icore.dts @@ -0,0 +1,59 @@ +/* + * Copyright (C) 2016 Amarula Solutions B.V. + * Copyright (C) 2016 Engicam S.r.l. + * + * This file is dual-licensed: you can use it either under the terms + * of the GPL or the X11 license, at your option. Note that this dual + * licensing only applies to this file, and not this project as a + * whole. + * + * a) This file is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * version 2 as published by the Free Software Foundation. + * + * This file is distributed in the hope that it will be useful + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * Or, alternatively + * + * b) Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use + * copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following + * conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED , WITHOUT WARRANTY OF ANY KIND + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + */ + +/dts-v1/; + +#include "imx6dl.dtsi" +#include "imx6qdl-icore.dtsi" + +/ { + model = "Engicam i.CoreM6 DualLite/Solo Starter Kit"; + compatible = "engicam,imx6-icore", "fsl,imx6dl"; +}; + +&can1 { + status = "okay"; +}; + +&can2 { + status = "okay"; +}; diff --git a/arch/arm/boot/dts/imx6dl-riotboard.dts b/arch/arm/boot/dts/imx6dl-riotboard.dts index 75d73437adf7..2cb72824e800 100644 --- a/arch/arm/boot/dts/imx6dl-riotboard.dts +++ b/arch/arm/boot/dts/imx6dl-riotboard.dts @@ -390,7 +390,7 @@ MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b030 /* AR8035 pin strapping: MODE#3: pull up */ MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x130b0 /* AR8035 pin strapping: MODE#0: pull down */ MX6QDL_PAD_GPIO_16__ENET_REF_CLK 0x4001b0a8 /* GPIO16 -> AR8035 25MHz */ - MX6QDL_PAD_EIM_D31__GPIO3_IO31 0x130b0 /* RGMII_nRST */ + MX6QDL_PAD_EIM_D31__GPIO3_IO31 0x130b0 /* RGMII_nRST */ MX6QDL_PAD_ENET_TX_EN__GPIO1_IO28 0x180b0 /* AR8035 interrupt */ MX6QDL_PAD_GPIO_6__ENET_IRQ 0x000b1 >; diff --git a/arch/arm/boot/dts/imx6dl-tx6dl-comtft.dts b/arch/arm/boot/dts/imx6dl-tx6dl-comtft.dts index 063fe7510da5..aac42ac465b6 100644 --- a/arch/arm/boot/dts/imx6dl-tx6dl-comtft.dts +++ b/arch/arm/boot/dts/imx6dl-tx6dl-comtft.dts @@ -105,7 +105,7 @@ pixelclk-active = <1>; }; }; - }; + }; }; &can1 { diff --git a/arch/arm/boot/dts/imx6dl-tx6u-801x.dts b/arch/arm/boot/dts/imx6dl-tx6u-801x.dts index b7a72840b7f0..d1f1298ec55a 100644 --- a/arch/arm/boot/dts/imx6dl-tx6u-801x.dts +++ b/arch/arm/boot/dts/imx6dl-tx6u-801x.dts @@ -199,7 +199,7 @@ pixelclk-active = <0>; }; }; - }; + }; }; &ipu1_di0_disp0 { diff --git a/arch/arm/boot/dts/imx6q-apalis-ixora.dts b/arch/arm/boot/dts/imx6q-apalis-ixora.dts index 207b85b91ada..0ea75f7b6039 100644 --- a/arch/arm/boot/dts/imx6q-apalis-ixora.dts +++ b/arch/arm/boot/dts/imx6q-apalis-ixora.dts @@ -147,28 +147,6 @@ gpios = <&gpio2 2 GPIO_ACTIVE_HIGH>; }; }; - - pwmleds { - compatible = "pwm-leds"; - - ledpwm1 { - label = "PWM1"; - pwms = <&pwm1 0 50000>; - max-brightness = <255>; - }; - - ledpwm2 { - label = "PWM2"; - pwms = <&pwm2 0 50000>; - max-brightness = <255>; - }; - - ledpwm3 { - label = "PWM3"; - pwms = <&pwm3 0 50000>; - max-brightness = <255>; - }; - }; }; &backlight { diff --git a/arch/arm/boot/dts/imx6q-b650v3.dts b/arch/arm/boot/dts/imx6q-b650v3.dts index d85388725426..1dcaee23ed9c 100644 --- a/arch/arm/boot/dts/imx6q-b650v3.dts +++ b/arch/arm/boot/dts/imx6q-b650v3.dts @@ -98,3 +98,9 @@ line-name = "PCA9539-P05"; }; }; + +&usbphy1 { + fsl,tx-cal-45-dn-ohms = <55>; + fsl,tx-cal-45-dp-ohms = <55>; + fsl,tx-d-cal = <100>; +}; diff --git a/arch/arm/boot/dts/imx6q-evi.dts b/arch/arm/boot/dts/imx6q-evi.dts index 6de21ff47c3a..7c7c1a855ece 100644 --- a/arch/arm/boot/dts/imx6q-evi.dts +++ b/arch/arm/boot/dts/imx6q-evi.dts @@ -232,10 +232,7 @@ }; &weim { - #address-cells = <2>; - #size-cells = <1>; ranges = <0 0 0x08000000 0x08000000>; - fsl,weim-cs-gpr = <&gpr>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_weimfpga &pinctrl_weimcs>; status = "okay"; diff --git a/arch/arm/boot/dts/imx6q-icore.dts b/arch/arm/boot/dts/imx6q-icore.dts new file mode 100644 index 000000000000..025f54350c28 --- /dev/null +++ b/arch/arm/boot/dts/imx6q-icore.dts @@ -0,0 +1,59 @@ +/* + * Copyright (C) 2016 Amarula Solutions B.V. + * Copyright (C) 2016 Engicam S.r.l. + * + * This file is dual-licensed: you can use it either under the terms + * of the GPL or the X11 license, at your option. Note that this dual + * licensing only applies to this file, and not this project as a + * whole. + * + * a) This file is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * version 2 as published by the Free Software Foundation. + * + * This file is distributed in the hope that it will be useful + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * Or, alternatively + * + * b) Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use + * copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following + * conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED , WITHOUT WARRANTY OF ANY KIND + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + */ + +/dts-v1/; + +#include "imx6q.dtsi" +#include "imx6qdl-icore.dtsi" + +/ { + model = "Engicam i.CoreM6 Quad/Dual Starter Kit"; + compatible = "engicam,imx6-icore", "fsl,imx6q"; +}; + +&can1 { + status = "okay"; +}; + +&can2 { + status = "okay"; +}; diff --git a/arch/arm/boot/dts/imx6q-nitrogen6_som2.dts b/arch/arm/boot/dts/imx6q-nitrogen6_som2.dts new file mode 100644 index 000000000000..cf4feefe02c5 --- /dev/null +++ b/arch/arm/boot/dts/imx6q-nitrogen6_som2.dts @@ -0,0 +1,53 @@ +/* + * Copyright 2016 Boundary Devices, Inc. + * + * This file is dual-licensed: you can use it either under the terms + * of the GPL or the X11 license, at your option. Note that this dual + * licensing only applies to this file, and not this project as a + * whole. + * + * a) This file is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * version 2 as published by the Free Software Foundation. + * + * This file is distributed in the hope that it will be useful + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * Or, alternatively + * + * b) Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use + * copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following + * conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED , WITHOUT WARRANTY OF ANY KIND + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + */ +/dts-v1/; + +#include "imx6q.dtsi" +#include "imx6qdl-nitrogen6_som2.dtsi" + +/ { + model = "Boundary Devices i.MX6 Quad Nitrogen6_SOM2 Board"; + compatible = "boundary,imx6q-nitrogen6_som2", "fsl,imx6q"; +}; + +&sata { + status = "okay"; +}; diff --git a/arch/arm/boot/dts/imx6q-novena.dts b/arch/arm/boot/dts/imx6q-novena.dts index 1723e89e3acc..758bca96786f 100644 --- a/arch/arm/boot/dts/imx6q-novena.dts +++ b/arch/arm/boot/dts/imx6q-novena.dts @@ -451,6 +451,10 @@ status = "okay"; }; +&pwm1 { + status = "okay"; +}; + &sata { target-supply = <®_sata>; fsl,transmit-level-mV = <1025>; diff --git a/arch/arm/boot/dts/imx6q-phytec-pbab01.dts b/arch/arm/boot/dts/imx6q-phytec-pbab01.dts index c139ac0ebe15..1f4771304da8 100644 --- a/arch/arm/boot/dts/imx6q-phytec-pbab01.dts +++ b/arch/arm/boot/dts/imx6q-phytec-pbab01.dts @@ -23,5 +23,5 @@ }; &sata { - status = "okay"; + status = "okay"; }; diff --git a/arch/arm/boot/dts/imx6q-tx6q-1010-comtft.dts b/arch/arm/boot/dts/imx6q-tx6q-1010-comtft.dts index 65e95ae7509a..71746edc2ee9 100644 --- a/arch/arm/boot/dts/imx6q-tx6q-1010-comtft.dts +++ b/arch/arm/boot/dts/imx6q-tx6q-1010-comtft.dts @@ -105,7 +105,7 @@ pixelclk-active = <1>; }; }; - }; + }; }; &can1 { diff --git a/arch/arm/boot/dts/imx6q-tx6q-1010.dts b/arch/arm/boot/dts/imx6q-tx6q-1010.dts index 20cd0e7b3e21..f9cd21a41a79 100644 --- a/arch/arm/boot/dts/imx6q-tx6q-1010.dts +++ b/arch/arm/boot/dts/imx6q-tx6q-1010.dts @@ -199,7 +199,7 @@ pixelclk-active = <0>; }; }; - }; + }; }; &ipu1_di0_disp0 { diff --git a/arch/arm/boot/dts/imx6q-tx6q-1020-comtft.dts b/arch/arm/boot/dts/imx6q-tx6q-1020-comtft.dts index 9ed243b704ff..959ff3fb7304 100644 --- a/arch/arm/boot/dts/imx6q-tx6q-1020-comtft.dts +++ b/arch/arm/boot/dts/imx6q-tx6q-1020-comtft.dts @@ -105,7 +105,7 @@ pixelclk-active = <1>; }; }; - }; + }; }; &can1 { diff --git a/arch/arm/boot/dts/imx6q-tx6q-1020.dts b/arch/arm/boot/dts/imx6q-tx6q-1020.dts index 347b531d3763..b49133d25d80 100644 --- a/arch/arm/boot/dts/imx6q-tx6q-1020.dts +++ b/arch/arm/boot/dts/imx6q-tx6q-1020.dts @@ -199,7 +199,7 @@ pixelclk-active = <0>; }; }; - }; + }; }; &ds1339 { diff --git a/arch/arm/boot/dts/imx6q-utilite-pro.dts b/arch/arm/boot/dts/imx6q-utilite-pro.dts index 61990630a748..22009947cebc 100644 --- a/arch/arm/boot/dts/imx6q-utilite-pro.dts +++ b/arch/arm/boot/dts/imx6q-utilite-pro.dts @@ -68,7 +68,41 @@ label = "Power Button"; gpios = <&gpio1 29 GPIO_ACTIVE_LOW>; linux,code = <KEY_POWER>; - gpio-key,wakeup; + wakeup-source; + }; + }; + + i2cmux { + compatible = "i2c-mux-gpio"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c1mux>; + #address-cells = <1>; + #size-cells = <0>; + + mux-gpios = <&gpio1 2 GPIO_ACTIVE_HIGH>; + i2c-parent = <&i2c1>; + + i2c@0 { + reg = <0>; + #address-cells = <1>; + #size-cells = <0>; + + eeprom@50 { + compatible = "at24,24c02"; + reg = <0x50>; + pagesize = <16>; + }; + + em3027: rtc@56 { + compatible = "emmicro,em3027"; + reg = <0x56>; + }; + }; + + i2c_dvi_ddc: i2c@1 { + reg = <1>; + #address-cells = <1>; + #size-cells = <0>; }; }; }; @@ -82,17 +116,6 @@ pinctrl-names = "default"; pinctrl-0 = <&pinctrl_i2c1>; status = "okay"; - - eeprom@50 { - compatible = "at24,24c02"; - reg = <0x50>; - pagesize = <16>; - }; - - em3027: rtc@56 { - compatible = "emmicro,em3027"; - reg = <0x56>; - }; }; &i2c2 { @@ -115,6 +138,12 @@ >; }; + pinctrl_i2c1mux: i2c1muxgrp { + fsl,pins = < + MX6QDL_PAD_GPIO_2__GPIO1_IO02 0x1b0b0 + >; + }; + pinctrl_i2c2: i2c2grp { fsl,pins = < MX6QDL_PAD_KEY_COL3__I2C2_SCL 0x4001b8b1 diff --git a/arch/arm/boot/dts/imx6qdl-apalis.dtsi b/arch/arm/boot/dts/imx6qdl-apalis.dtsi index 99e323b57261..8c8a049eb3d0 100644 --- a/arch/arm/boot/dts/imx6qdl-apalis.dtsi +++ b/arch/arm/boot/dts/imx6qdl-apalis.dtsi @@ -49,7 +49,10 @@ backlight: backlight { compatible = "pwm-backlight"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_gpio_bl_on>; pwms = <&pwm4 0 5000000>; + enable-gpios = <&gpio3 13 GPIO_ACTIVE_HIGH>; status = "disabled"; }; @@ -620,6 +623,12 @@ >; }; + pinctrl_gpio_bl_on: gpioblon { + fsl,pins = < + MX6QDL_PAD_EIM_DA13__GPIO3_IO13 0x1b0b0 + >; + }; + pinctrl_gpio_keys: gpio1io04grp { fsl,pins = < /* Power button */ diff --git a/arch/arm/boot/dts/imx6qdl-apf6dev.dtsi b/arch/arm/boot/dts/imx6qdl-apf6dev.dtsi index edbce222c782..5e7792d6bf58 100644 --- a/arch/arm/boot/dts/imx6qdl-apf6dev.dtsi +++ b/arch/arm/boot/dts/imx6qdl-apf6dev.dtsi @@ -347,13 +347,13 @@ fsl,pins = < MX6QDL_PAD_DI0_PIN4__GPIO4_IO20 0x100b1 MX6QDL_PAD_DISP0_DAT18__GPIO5_IO12 0x100b1 - MX6QDL_PAD_DISP0_DAT19__GPIO5_IO13 0x100b1 - MX6QDL_PAD_DISP0_DAT20__GPIO5_IO14 0x100b1 - MX6QDL_PAD_DISP0_DAT21__GPIO5_IO15 0x100b1 - MX6QDL_PAD_DISP0_DAT22__GPIO5_IO16 0x100b1 - MX6QDL_PAD_DISP0_DAT23__GPIO5_IO17 0x100b1 - MX6QDL_PAD_CSI0_PIXCLK__GPIO5_IO18 0x100b1 - MX6QDL_PAD_CSI0_VSYNC__GPIO5_IO21 0x100b1 + MX6QDL_PAD_DISP0_DAT19__GPIO5_IO13 0x100b1 + MX6QDL_PAD_DISP0_DAT20__GPIO5_IO14 0x100b1 + MX6QDL_PAD_DISP0_DAT21__GPIO5_IO15 0x100b1 + MX6QDL_PAD_DISP0_DAT22__GPIO5_IO16 0x100b1 + MX6QDL_PAD_DISP0_DAT23__GPIO5_IO17 0x100b1 + MX6QDL_PAD_CSI0_PIXCLK__GPIO5_IO18 0x100b1 + MX6QDL_PAD_CSI0_VSYNC__GPIO5_IO21 0x100b1 >; }; diff --git a/arch/arm/boot/dts/imx6qdl-colibri.dtsi b/arch/arm/boot/dts/imx6qdl-colibri.dtsi new file mode 100644 index 000000000000..e6faa653f91a --- /dev/null +++ b/arch/arm/boot/dts/imx6qdl-colibri.dtsi @@ -0,0 +1,890 @@ +/* + * Copyright 2014-2016 Toradex AG + * Copyright 2012 Freescale Semiconductor, Inc. + * Copyright 2011 Linaro Ltd. + * + * This file is dual-licensed: you can use it either under the terms + * of the GPL or the X11 license, at your option. Note that this dual + * licensing only applies to this file, and not this project as a + * whole. + * + * a) This file is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * version 2 as published by the Free Software Foundation. + * + * This file is distributed in the hope that it will be useful + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * Or, alternatively + * + * b) Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use + * copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following + * conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED , WITHOUT WARRANTY OF ANY KIND + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + */ + +#include <dt-bindings/gpio/gpio.h> + +/ { + model = "Toradex Colibri iMX6DL/S Module"; + compatible = "toradex,colibri_imx6dl", "fsl,imx6dl"; + + backlight: backlight { + compatible = "pwm-backlight"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_gpio_bl_on>; + pwms = <&pwm3 0 5000000>; + enable-gpios = <&gpio3 26 GPIO_ACTIVE_HIGH>; /* Colibri BL_ON */ + status = "disabled"; + }; + + reg_1p8v: regulator-1p8v { + compatible = "regulator-fixed"; + regulator-name = "1P8V"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + }; + + reg_2p5v: regulator-2p5v { + compatible = "regulator-fixed"; + regulator-name = "2P5V"; + regulator-min-microvolt = <2500000>; + regulator-max-microvolt = <2500000>; + regulator-always-on; + }; + + reg_3p3v: regulator-3p3v { + compatible = "regulator-fixed"; + regulator-name = "3P3V"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + reg_usb_host_vbus: regulator-usb-host-vbus { + compatible = "regulator-fixed"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_regulator_usbh_pwr>; + regulator-name = "usb_host_vbus"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + gpio = <&gpio3 31 GPIO_ACTIVE_HIGH>; /* USBH_PEN */ + status = "disabled"; + }; + + sound { + compatible = "fsl,imx-audio-sgtl5000"; + model = "imx6dl-colibri-sgtl5000"; + ssi-controller = <&ssi1>; + audio-codec = <&codec>; + audio-routing = + "Headphone Jack", "HP_OUT", + "LINE_IN", "Line In Jack", + "MIC_IN", "Mic Jack", + "Mic Jack", "Mic Bias"; + mux-int-port = <1>; + mux-ext-port = <5>; + }; + + /* Optional S/PDIF in on SODIMM 88 and out on SODIMM 90, 137 or 168 */ + sound_spdif: sound-spdif { + compatible = "fsl,imx-audio-spdif"; + model = "imx-spdif"; + spdif-controller = <&spdif>; + spdif-in; + spdif-out; + status = "disabled"; + }; +}; + +&audmux { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_audmux &pinctrl_mic_gnd>; + status = "okay"; +}; + +/* Optional on SODIMM 55/63 */ +&can1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_flexcan1>; + status = "disabled"; +}; + +/* Optional on SODIMM 178/188 */ +&can2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_flexcan2>; + status = "disabled"; +}; + +/* Colibri SSP */ +&ecspi4 { + fsl,spi-num-chipselects = <1>; + cs-gpios = <&gpio5 2 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_ecspi4>; + status = "disabled"; +}; + +&fec { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_enet>; + phy-mode = "rmii"; + status = "okay"; +}; + +&hdmi { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_hdmi_ddc>; + status = "disabled"; +}; + +/* + * PWR_I2C: power I2C to audio codec, PMIC, temperature sensor and + * touch screen controller + */ +&i2c2 { + clock-frequency = <100000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c2>; + status = "okay"; + + pmic: pfuze100@08 { + compatible = "fsl,pfuze100"; + reg = <0x08>; + + regulators { + sw1a_reg: sw1ab { + regulator-min-microvolt = <300000>; + regulator-max-microvolt = <1875000>; + regulator-boot-on; + regulator-always-on; + regulator-ramp-delay = <6250>; + }; + + sw1c_reg: sw1c { + regulator-min-microvolt = <300000>; + regulator-max-microvolt = <1875000>; + regulator-boot-on; + regulator-always-on; + regulator-ramp-delay = <6250>; + }; + + sw3a_reg: sw3a { + regulator-min-microvolt = <400000>; + regulator-max-microvolt = <1975000>; + regulator-boot-on; + regulator-always-on; + }; + + swbst_reg: swbst { + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5150000>; + regulator-boot-on; + regulator-always-on; + }; + + snvs_reg: vsnvs { + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <3000000>; + regulator-boot-on; + regulator-always-on; + }; + + vref_reg: vrefddr { + regulator-boot-on; + regulator-always-on; + }; + + /* vgen1: unused */ + + vgen2_reg: vgen2 { + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <1550000>; + regulator-boot-on; + regulator-always-on; + }; + + /* vgen3: unused */ + + vgen4_reg: vgen4 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + regulator-boot-on; + regulator-always-on; + }; + + vgen5_reg: vgen5 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + regulator-boot-on; + regulator-always-on; + }; + + vgen6_reg: vgen6 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + regulator-boot-on; + regulator-always-on; + }; + }; + }; + + codec: sgtl5000@0a { + compatible = "fsl,sgtl5000"; + reg = <0x0a>; + clocks = <&clks IMX6QDL_CLK_CKO>; + VDDA-supply = <®_2p5v>; + VDDIO-supply = <®_3p3v>; + }; + + /* STMPE811 touch screen controller */ + stmpe811@41 { + compatible = "st,stmpe811"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_touch_int>; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x41>; + interrupts = <20 IRQ_TYPE_LEVEL_LOW>; + interrupt-parent = <&gpio6>; + interrupt-controller; + id = <0>; + blocks = <0x5>; + irq-trigger = <0x1>; + + stmpe_touchscreen { + compatible = "st,stmpe-ts"; + reg = <0>; + /* 3.25 MHz ADC clock speed */ + st,adc-freq = <1>; + /* 8 sample average control */ + st,ave-ctrl = <3>; + /* 7 length fractional part in z */ + st,fraction-z = <7>; + /* + * 50 mA typical 80 mA max touchscreen drivers + * current limit value + */ + st,i-drive = <1>; + /* 12-bit ADC */ + st,mod-12b = <1>; + /* internal ADC reference */ + st,ref-sel = <0>; + /* ADC converstion time: 80 clocks */ + st,sample-time = <4>; + /* 1 ms panel driver settling time */ + st,settling = <3>; + /* 5 ms touch detect interrupt delay */ + st,touch-det-delay = <5>; + }; + }; +}; + +/* + * I2C3_SDA/SCL on SODIMM 194/196 (e.g. RTC on carrier board) + */ +&i2c3 { + clock-frequency = <100000>; + pinctrl-names = "default", "recovery"; + pinctrl-0 = <&pinctrl_i2c3>; + pinctrl-1 = <&pinctrl_i2c3_recovery>; + scl-gpios = <&gpio1 3 GPIO_ACTIVE_HIGH>; + sda-gpios = <&gpio1 6 GPIO_ACTIVE_HIGH>; + status = "disabled"; +}; + +/* Colibri PWM<B> */ +&pwm1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pwm1>; + status = "disabled"; +}; + +/* Colibri PWM<D> */ +&pwm2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pwm2>; + status = "disabled"; +}; + +/* Colibri PWM<A> */ +&pwm3 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pwm3>; + status = "disabled"; +}; + +/* Colibri PWM<C> */ +&pwm4 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pwm4>; + status = "disabled"; +}; + +/* Optional S/PDIF out on SODIMM 137 */ +&spdif { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_spdif>; + status = "disabled"; +}; + +&ssi1 { + status = "okay"; +}; + +/* Colibri UART_A */ +&uart1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart1_dte &pinctrl_uart1_ctrl>; + fsl,dte-mode; + uart-has-rtscts; + status = "disabled"; +}; + +/* Colibri UART_B */ +&uart2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart2_dte>; + fsl,dte-mode; + uart-has-rtscts; + status = "disabled"; +}; + +/* Colibri UART_C */ +&uart3 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart3_dte>; + fsl,dte-mode; + status = "disabled"; +}; + +&usbotg { + pinctrl-names = "default"; + disable-over-current; + dr_mode = "peripheral"; + status = "disabled"; +}; + +/* Colibri MMC */ +&usdhc1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usdhc1>; + vqmmc-supply = <®_3p3v>; + bus-width = <4>; + voltage-ranges = <3300 3300>; + status = "disabled"; +}; + +/* eMMC */ +&usdhc3 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usdhc3>; + vqmmc-supply = <®_3p3v>; + bus-width = <8>; + voltage-ranges = <3300 3300>; + non-removable; + status = "okay"; +}; + +&weim { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_weim_sram &pinctrl_weim_cs0 + &pinctrl_weim_cs1 &pinctrl_weim_cs2 + &pinctrl_weim_rdnwr &pinctrl_weim_npwe>; + #address-cells = <2>; + #size-cells = <1>; + status = "disabled"; +}; + +&iomuxc { + pinctrl_audmux: audmuxgrp { + fsl,pins = < + MX6QDL_PAD_KEY_COL0__AUD5_TXC 0x130b0 + MX6QDL_PAD_KEY_ROW0__AUD5_TXD 0x130b0 + MX6QDL_PAD_KEY_COL1__AUD5_TXFS 0x130b0 + MX6QDL_PAD_KEY_ROW1__AUD5_RXD 0x130b0 + /* SGTL5000 sys_mclk */ + MX6QDL_PAD_GPIO_0__CCM_CLKO1 0x000b0 + >; + }; + + pinctrl_cam_mclk: cammclkgrp { + fsl,pins = < + /* Parallel Camera CAM sys_mclk */ + MX6QDL_PAD_NANDF_CS2__CCM_CLKO2 0x00b0 + >; + }; + + pinctrl_ecspi4: ecspi4grp { + fsl,pins = < + MX6QDL_PAD_EIM_D22__ECSPI4_MISO 0x100b1 + MX6QDL_PAD_EIM_D28__ECSPI4_MOSI 0x100b1 + MX6QDL_PAD_EIM_D21__ECSPI4_SCLK 0x100b1 + /* SPI CS */ + MX6QDL_PAD_EIM_A25__GPIO5_IO02 0x000b1 + >; + }; + + pinctrl_enet: enetgrp { + fsl,pins = < + MX6QDL_PAD_ENET_MDC__ENET_MDC 0x1b0b0 + MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x1b0b0 + MX6QDL_PAD_ENET_RXD0__ENET_RX_DATA0 0x1b0b0 + MX6QDL_PAD_ENET_RXD1__ENET_RX_DATA1 0x1b0b0 + MX6QDL_PAD_ENET_RX_ER__ENET_RX_ER 0x1b0b0 + MX6QDL_PAD_ENET_TX_EN__ENET_TX_EN 0x1b0b0 + MX6QDL_PAD_ENET_TXD0__ENET_TX_DATA0 0x1b0b0 + MX6QDL_PAD_ENET_TXD1__ENET_TX_DATA1 0x1b0b0 + MX6QDL_PAD_ENET_CRS_DV__ENET_RX_EN 0x1b0b0 + MX6QDL_PAD_GPIO_16__ENET_REF_CLK ((1<<30) | 0x1b0b0) + >; + }; + + pinctrl_flexcan1: flexcan1grp { + fsl,pins = < + MX6QDL_PAD_GPIO_7__FLEXCAN1_TX 0x1b0b0 + MX6QDL_PAD_GPIO_8__FLEXCAN1_RX 0x1b0b0 + >; + }; + + pinctrl_flexcan2: flexcan2grp { + fsl,pins = < + MX6QDL_PAD_KEY_COL4__FLEXCAN2_TX 0x1b0b0 + MX6QDL_PAD_KEY_ROW4__FLEXCAN2_RX 0x1b0b0 + >; + }; + + pinctrl_gpio_bl_on: gpioblon { + fsl,pins = < + MX6QDL_PAD_EIM_D26__GPIO3_IO26 0x1b0b0 + >; + }; + + pinctrl_gpio_keys: gpiokeys { + fsl,pins = < + /* Power button */ + MX6QDL_PAD_EIM_A16__GPIO2_IO22 0x1b0b0 + >; + }; + + pinctrl_hdmi_ddc: hdmiddcgrp { + fsl,pins = < + MX6QDL_PAD_KEY_COL3__HDMI_TX_DDC_SCL 0x4001b8b1 + MX6QDL_PAD_KEY_ROW3__HDMI_TX_DDC_SDA 0x4001b8b1 + >; + }; + + pinctrl_i2c2: i2c2grp { + fsl,pins = < + MX6QDL_PAD_EIM_EB2__I2C2_SCL 0x4001b8b1 + MX6QDL_PAD_EIM_D16__I2C2_SDA 0x4001b8b1 + >; + }; + + pinctrl_i2c3: i2c3grp { + fsl,pins = < + MX6QDL_PAD_GPIO_3__I2C3_SCL 0x4001b8b1 + MX6QDL_PAD_GPIO_6__I2C3_SDA 0x4001b8b1 + >; + }; + + pinctrl_i2c3_recovery: i2c3recoverygrp { + fsl,pins = < + MX6QDL_PAD_GPIO_3__GPIO1_IO03 0x4001b8b1 + MX6QDL_PAD_GPIO_6__GPIO1_IO06 0x4001b8b1 + >; + }; + + pinctrl_ipu1_csi0: ipu1csi0grp { /* Parallel Camera */ + fsl,pins = < + MX6QDL_PAD_EIM_A17__IPU1_CSI1_DATA12 0xb0b1 + MX6QDL_PAD_EIM_A18__IPU1_CSI1_DATA13 0xb0b1 + MX6QDL_PAD_EIM_A19__IPU1_CSI1_DATA14 0xb0b1 + MX6QDL_PAD_EIM_A20__IPU1_CSI1_DATA15 0xb0b1 + MX6QDL_PAD_EIM_A21__IPU1_CSI1_DATA16 0xb0b1 + MX6QDL_PAD_EIM_A22__IPU1_CSI1_DATA17 0xb0b1 + MX6QDL_PAD_EIM_A23__IPU1_CSI1_DATA18 0xb0b1 + MX6QDL_PAD_EIM_A24__IPU1_CSI1_DATA19 0xb0b1 + MX6QDL_PAD_EIM_D17__IPU1_CSI1_PIXCLK 0xb0b1 + MX6QDL_PAD_EIM_EB3__IPU1_CSI1_HSYNC 0xb0b1 + MX6QDL_PAD_EIM_D29__IPU1_CSI1_VSYNC 0xb0b1 + /* Disable PWM pins on camera interface */ + MX6QDL_PAD_SD4_DAT1__GPIO2_IO09 0x40 + MX6QDL_PAD_GPIO_1__GPIO1_IO01 0x40 + >; + }; + + pinctrl_ipu1_lcdif: ipu1lcdifgrp { + fsl,pins = < + MX6QDL_PAD_DI0_DISP_CLK__IPU1_DI0_DISP_CLK 0xa1 + MX6QDL_PAD_DI0_PIN15__IPU1_DI0_PIN15 0xa1 + MX6QDL_PAD_DI0_PIN2__IPU1_DI0_PIN02 0xa1 + MX6QDL_PAD_DI0_PIN3__IPU1_DI0_PIN03 0xa1 + MX6QDL_PAD_DISP0_DAT0__IPU1_DISP0_DATA00 0xa1 + MX6QDL_PAD_DISP0_DAT1__IPU1_DISP0_DATA01 0xa1 + MX6QDL_PAD_DISP0_DAT2__IPU1_DISP0_DATA02 0xa1 + MX6QDL_PAD_DISP0_DAT3__IPU1_DISP0_DATA03 0xa1 + MX6QDL_PAD_DISP0_DAT4__IPU1_DISP0_DATA04 0xa1 + MX6QDL_PAD_DISP0_DAT5__IPU1_DISP0_DATA05 0xa1 + MX6QDL_PAD_DISP0_DAT6__IPU1_DISP0_DATA06 0xa1 + MX6QDL_PAD_DISP0_DAT7__IPU1_DISP0_DATA07 0xa1 + MX6QDL_PAD_DISP0_DAT8__IPU1_DISP0_DATA08 0xa1 + MX6QDL_PAD_DISP0_DAT9__IPU1_DISP0_DATA09 0xa1 + MX6QDL_PAD_DISP0_DAT10__IPU1_DISP0_DATA10 0xa1 + MX6QDL_PAD_DISP0_DAT11__IPU1_DISP0_DATA11 0xa1 + MX6QDL_PAD_DISP0_DAT12__IPU1_DISP0_DATA12 0xa1 + MX6QDL_PAD_DISP0_DAT13__IPU1_DISP0_DATA13 0xa1 + MX6QDL_PAD_DISP0_DAT14__IPU1_DISP0_DATA14 0xa1 + MX6QDL_PAD_DISP0_DAT15__IPU1_DISP0_DATA15 0xa1 + MX6QDL_PAD_DISP0_DAT16__IPU1_DISP0_DATA16 0xa1 + MX6QDL_PAD_DISP0_DAT17__IPU1_DISP0_DATA17 0xa1 + >; + }; + + pinctrl_mic_gnd: gpiomicgnd { + fsl,pins = < + /* Controls Mic GND, PU or '1' pull Mic GND to GND */ + MX6QDL_PAD_RGMII_TD1__GPIO6_IO21 0x1b0b0 + >; + }; + + pinctrl_mmc_cd: gpiommccd { + fsl,pins = < + MX6QDL_PAD_NANDF_D5__GPIO2_IO05 0x80000000 + >; + }; + + pinctrl_pwm1: pwm1grp { + fsl,pins = < + MX6QDL_PAD_GPIO_9__PWM1_OUT 0x1b0b1 + >; + }; + + pinctrl_pwm2: pwm2grp { + fsl,pins = < + MX6QDL_PAD_GPIO_1__PWM2_OUT 0x1b0b1 + MX6QDL_PAD_EIM_A21__GPIO2_IO17 0x00040 + >; + }; + + pinctrl_pwm3: pwm3grp { + fsl,pins = < + MX6QDL_PAD_SD4_DAT1__PWM3_OUT 0x1b0b1 + MX6QDL_PAD_EIM_A22__GPIO2_IO16 0x00040 + >; + }; + + pinctrl_pwm4: pwm4grp { + fsl,pins = < + MX6QDL_PAD_SD4_DAT2__PWM4_OUT 0x1b0b1 + >; + }; + + pinctrl_regulator_usbh_pwr: gpioregusbhpwrgrp { + fsl,pins = < + /* USBH_EN */ + MX6QDL_PAD_EIM_D31__GPIO3_IO31 0x0f058 + >; + }; + + pinctrl_spdif: spdifgrp { + fsl,pins = < + MX6QDL_PAD_GPIO_17__SPDIF_OUT 0x1b0b0 + >; + }; + + pinctrl_touch_int: gpiotouchintgrp { + fsl,pins = < + /* STMPE811 interrupt */ + MX6QDL_PAD_RGMII_TD0__GPIO6_IO20 0x1b0b0 + >; + }; + + pinctrl_uart1_dce: uart1dcegrp { + fsl,pins = < + MX6QDL_PAD_CSI0_DAT10__UART1_TX_DATA 0x1b0b1 + MX6QDL_PAD_CSI0_DAT11__UART1_RX_DATA 0x1b0b1 + >; + }; + + /* DTE mode */ + pinctrl_uart1_dte: uart1dtegrp { + fsl,pins = < + MX6QDL_PAD_CSI0_DAT10__UART1_RX_DATA 0x1b0b1 + MX6QDL_PAD_CSI0_DAT11__UART1_TX_DATA 0x1b0b1 + MX6QDL_PAD_EIM_D19__UART1_RTS_B 0x1b0b1 + MX6QDL_PAD_EIM_D20__UART1_CTS_B 0x1b0b1 + >; + }; + + /* Additional DTR, DSR, DCD */ + pinctrl_uart1_ctrl: uart1ctrlgrp { + fsl,pins = < + MX6QDL_PAD_EIM_D23__UART1_DCD_B 0x1b0b0 + MX6QDL_PAD_EIM_D24__UART1_DTR_B 0x1b0b0 + MX6QDL_PAD_EIM_D25__UART1_DSR_B 0x1b0b0 + >; + }; + + pinctrl_uart2_dte: uart2dtegrp { + fsl,pins = < + MX6QDL_PAD_SD4_DAT4__UART2_TX_DATA 0x1b0b1 + MX6QDL_PAD_SD4_DAT7__UART2_RX_DATA 0x1b0b1 + MX6QDL_PAD_SD4_DAT6__UART2_RTS_B 0x1b0b1 + MX6QDL_PAD_SD4_DAT5__UART2_CTS_B 0x1b0b1 + >; + }; + + pinctrl_uart3_dte: uart3dtegrp { + fsl,pins = < + MX6QDL_PAD_SD4_CLK__UART3_TX_DATA 0x1b0b1 + MX6QDL_PAD_SD4_CMD__UART3_RX_DATA 0x1b0b1 + >; + }; + + pinctrl_usbc_det: usbcdetgrp { + fsl,pins = < + /* USBC_DET */ + MX6QDL_PAD_GPIO_17__GPIO7_IO12 0x1b0b0 + /* USBC_DET_EN */ + MX6QDL_PAD_RGMII_TX_CTL__GPIO6_IO26 0x0f058 + /* USBC_DET_OVERWRITE */ + MX6QDL_PAD_RGMII_RXC__GPIO6_IO30 0x0f058 + >; + }; + + pinctrl_usdhc1: usdhc1grp { + fsl,pins = < + MX6QDL_PAD_SD1_CMD__SD1_CMD 0x17071 + MX6QDL_PAD_SD1_CLK__SD1_CLK 0x10071 + MX6QDL_PAD_SD1_DAT0__SD1_DATA0 0x17071 + MX6QDL_PAD_SD1_DAT1__SD1_DATA1 0x17071 + MX6QDL_PAD_SD1_DAT2__SD1_DATA2 0x17071 + MX6QDL_PAD_SD1_DAT3__SD1_DATA3 0x17071 + >; + }; + + pinctrl_usdhc3: usdhc3grp { + fsl,pins = < + MX6QDL_PAD_SD3_CMD__SD3_CMD 0x17059 + MX6QDL_PAD_SD3_CLK__SD3_CLK 0x10059 + MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x17059 + MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x17059 + MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x17059 + MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x17059 + MX6QDL_PAD_SD3_DAT4__SD3_DATA4 0x17059 + MX6QDL_PAD_SD3_DAT5__SD3_DATA5 0x17059 + MX6QDL_PAD_SD3_DAT6__SD3_DATA6 0x17059 + MX6QDL_PAD_SD3_DAT7__SD3_DATA7 0x17059 + /* eMMC reset */ + MX6QDL_PAD_SD3_RST__SD3_RESET 0x17059 + >; + }; + + pinctrl_usdhc3_100mhz: usdhc3100mhzgrp { + fsl,pins = < + MX6QDL_PAD_SD3_CMD__SD3_CMD 0x170b9 + MX6QDL_PAD_SD3_CLK__SD3_CLK 0x100b9 + MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x170b9 + MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x170b9 + MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x170b9 + MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x170b9 + MX6QDL_PAD_SD3_DAT4__SD3_DATA4 0x170b9 + MX6QDL_PAD_SD3_DAT5__SD3_DATA5 0x170b9 + MX6QDL_PAD_SD3_DAT6__SD3_DATA6 0x170b9 + MX6QDL_PAD_SD3_DAT7__SD3_DATA7 0x170b9 + /* eMMC reset */ + MX6QDL_PAD_SD3_RST__SD3_RESET 0x170b9 + >; + }; + + pinctrl_usdhc3_200mhz: usdhc3200mhzgrp { + fsl,pins = < + MX6QDL_PAD_SD3_CMD__SD3_CMD 0x170f9 + MX6QDL_PAD_SD3_CLK__SD3_CLK 0x100f9 + MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x170f9 + MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x170f9 + MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x170f9 + MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x170f9 + MX6QDL_PAD_SD3_DAT4__SD3_DATA4 0x170f9 + MX6QDL_PAD_SD3_DAT5__SD3_DATA5 0x170f9 + MX6QDL_PAD_SD3_DAT6__SD3_DATA6 0x170f9 + MX6QDL_PAD_SD3_DAT7__SD3_DATA7 0x170f9 + /* eMMC reset */ + MX6QDL_PAD_SD3_RST__SD3_RESET 0x170f9 + >; + }; + + pinctrl_weim_cs0: weimcs0grp { + fsl,pins = < + /* nEXT_CS0 */ + MX6QDL_PAD_EIM_CS0__EIM_CS0_B 0xb0b1 + >; + }; + + pinctrl_weim_cs1: weimcs1grp { + fsl,pins = < + /* nEXT_CS1 */ + MX6QDL_PAD_EIM_CS1__EIM_CS1_B 0xb0b1 + >; + }; + + pinctrl_weim_cs2: weimcs2grp { + fsl,pins = < + /* nEXT_CS2 */ + MX6QDL_PAD_SD2_DAT1__EIM_CS2_B 0xb0b1 + >; + }; + + pinctrl_weim_sram: weimsramgrp { + fsl,pins = < + MX6QDL_PAD_EIM_OE__EIM_OE_B 0xb0b1 + MX6QDL_PAD_EIM_RW__EIM_RW 0xb0b1 + /* Data */ + MX6QDL_PAD_CSI0_DATA_EN__EIM_DATA00 0x1b0b0 + MX6QDL_PAD_CSI0_VSYNC__EIM_DATA01 0x1b0b0 + MX6QDL_PAD_CSI0_DAT4__EIM_DATA02 0x1b0b0 + MX6QDL_PAD_CSI0_DAT5__EIM_DATA03 0x1b0b0 + MX6QDL_PAD_CSI0_DAT6__EIM_DATA04 0x1b0b0 + MX6QDL_PAD_CSI0_DAT7__EIM_DATA05 0x1b0b0 + MX6QDL_PAD_CSI0_DAT8__EIM_DATA06 0x1b0b0 + MX6QDL_PAD_CSI0_DAT9__EIM_DATA07 0x1b0b0 + MX6QDL_PAD_CSI0_DAT12__EIM_DATA08 0x1b0b0 + MX6QDL_PAD_CSI0_DAT13__EIM_DATA09 0x1b0b0 + MX6QDL_PAD_CSI0_DAT14__EIM_DATA10 0x1b0b0 + MX6QDL_PAD_CSI0_DAT15__EIM_DATA11 0x1b0b0 + MX6QDL_PAD_CSI0_DAT16__EIM_DATA12 0x1b0b0 + MX6QDL_PAD_CSI0_DAT17__EIM_DATA13 0x1b0b0 + MX6QDL_PAD_CSI0_DAT18__EIM_DATA14 0x1b0b0 + MX6QDL_PAD_CSI0_DAT19__EIM_DATA15 0x1b0b0 + /* Address */ + MX6QDL_PAD_EIM_DA15__EIM_AD15 0xb0b1 + MX6QDL_PAD_EIM_DA14__EIM_AD14 0xb0b1 + MX6QDL_PAD_EIM_DA13__EIM_AD13 0xb0b1 + MX6QDL_PAD_EIM_DA12__EIM_AD12 0xb0b1 + MX6QDL_PAD_EIM_DA11__EIM_AD11 0xb0b1 + MX6QDL_PAD_EIM_DA10__EIM_AD10 0xb0b1 + MX6QDL_PAD_EIM_DA9__EIM_AD09 0xb0b1 + MX6QDL_PAD_EIM_DA8__EIM_AD08 0xb0b1 + MX6QDL_PAD_EIM_DA7__EIM_AD07 0xb0b1 + MX6QDL_PAD_EIM_DA6__EIM_AD06 0xb0b1 + MX6QDL_PAD_EIM_DA5__EIM_AD05 0xb0b1 + MX6QDL_PAD_EIM_DA4__EIM_AD04 0xb0b1 + MX6QDL_PAD_EIM_DA3__EIM_AD03 0xb0b1 + MX6QDL_PAD_EIM_DA2__EIM_AD02 0xb0b1 + MX6QDL_PAD_EIM_DA1__EIM_AD01 0xb0b1 + MX6QDL_PAD_EIM_DA0__EIM_AD00 0xb0b1 + >; + }; + + pinctrl_weim_rdnwr: weimrdnwr { + fsl,pins = < + MX6QDL_PAD_SD2_CLK__GPIO1_IO10 0x0040 + MX6QDL_PAD_RGMII_TD3__GPIO6_IO23 0x130b0 + >; + }; + + pinctrl_weim_npwe: weimnpwe { + fsl,pins = < + MX6QDL_PAD_SD2_DAT3__GPIO1_IO12 0x0040 + MX6QDL_PAD_RGMII_TD2__GPIO6_IO22 0x130b0 + >; + }; + + /* ADDRESS[16:18] [25] used as GPIO */ + pinctrl_weim_gpio_1: weimgpio-1 { + fsl,pins = < + MX6QDL_PAD_KEY_ROW4__GPIO4_IO15 0x1b0b0 + MX6QDL_PAD_KEY_ROW2__GPIO4_IO11 0x1b0b0 + MX6QDL_PAD_KEY_COL2__GPIO4_IO10 0x1b0b0 + MX6QDL_PAD_DISP0_DAT23__GPIO5_IO17 0x1b0b0 + MX6QDL_PAD_DISP0_DAT22__GPIO5_IO16 0x1b0b0 + MX6QDL_PAD_DISP0_DAT21__GPIO5_IO15 0x1b0b0 + MX6QDL_PAD_DISP0_DAT20__GPIO5_IO14 0x1b0b0 + MX6QDL_PAD_DISP0_DAT19__GPIO5_IO13 0x1b0b0 + MX6QDL_PAD_DISP0_DAT18__GPIO5_IO12 0x1b0b0 + MX6QDL_PAD_NANDF_D1__GPIO2_IO01 0x1b0b0 + >; + }; + + /* ADDRESS[19:24] used as GPIO */ + pinctrl_weim_gpio_2: weimgpio-2 { + fsl,pins = < + MX6QDL_PAD_KEY_ROW2__GPIO4_IO11 0x1b0b0 + MX6QDL_PAD_KEY_COL2__GPIO4_IO10 0x1b0b0 + MX6QDL_PAD_DISP0_DAT23__GPIO5_IO17 0x1b0b0 + MX6QDL_PAD_DISP0_DAT22__GPIO5_IO16 0x1b0b0 + MX6QDL_PAD_DISP0_DAT21__GPIO5_IO15 0x1b0b0 + MX6QDL_PAD_DISP0_DAT20__GPIO5_IO14 0x1b0b0 + MX6QDL_PAD_DISP0_DAT19__GPIO5_IO13 0x1b0b0 + MX6QDL_PAD_DISP0_DAT18__GPIO5_IO12 0x1b0b0 + MX6QDL_PAD_NANDF_D1__GPIO2_IO01 0x1b0b0 + >; + }; + + /* DATA[16:31] used as GPIO */ + pinctrl_weim_gpio_3: weimgpio-3 { + fsl,pins = < + MX6QDL_PAD_EIM_LBA__GPIO2_IO27 0x1b0b0 + MX6QDL_PAD_EIM_BCLK__GPIO6_IO31 0x1b0b0 + MX6QDL_PAD_NANDF_CS3__GPIO6_IO16 0x1b0b0 + MX6QDL_PAD_NANDF_CS1__GPIO6_IO14 0x1b0b0 + MX6QDL_PAD_NANDF_RB0__GPIO6_IO10 0x1b0b0 + MX6QDL_PAD_NANDF_ALE__GPIO6_IO08 0x1b0b0 + MX6QDL_PAD_NANDF_WP_B__GPIO6_IO09 0x1b0b0 + MX6QDL_PAD_NANDF_CS0__GPIO6_IO11 0x1b0b0 + MX6QDL_PAD_NANDF_CLE__GPIO6_IO07 0x1b0b0 + MX6QDL_PAD_GPIO_19__GPIO4_IO05 0x1b0b0 + MX6QDL_PAD_CSI0_MCLK__GPIO5_IO19 0x1b0b0 + MX6QDL_PAD_CSI0_PIXCLK__GPIO5_IO18 0x1b0b0 + MX6QDL_PAD_GPIO_4__GPIO1_IO04 0x1b0b0 + MX6QDL_PAD_GPIO_5__GPIO1_IO05 0x1b0b0 + MX6QDL_PAD_GPIO_2__GPIO1_IO02 0x1b0b0 + >; + }; + + /* DQM[0:3] used as GPIO */ + pinctrl_weim_gpio_4: weimgpio-4 { + fsl,pins = < + MX6QDL_PAD_EIM_EB0__GPIO2_IO28 0x1b0b0 + MX6QDL_PAD_EIM_EB1__GPIO2_IO29 0x1b0b0 + MX6QDL_PAD_SD2_DAT2__GPIO1_IO13 0x1b0b0 + MX6QDL_PAD_NANDF_D0__GPIO2_IO00 0x1b0b0 + >; + }; + + /* RDY used as GPIO */ + pinctrl_weim_gpio_5: weimgpio-5 { + fsl,pins = < + MX6QDL_PAD_EIM_WAIT__GPIO5_IO00 0x1b0b0 + >; + }; + + /* ADDRESS[16] DATA[30] used as GPIO */ + pinctrl_weim_gpio_6: weimgpio-6 { + fsl,pins = < + MX6QDL_PAD_KEY_ROW4__GPIO4_IO15 0x1b0b0 + MX6QDL_PAD_KEY_COL4__GPIO4_IO14 0x1b0b0 + >; + }; +}; diff --git a/arch/arm/boot/dts/imx6qdl-gw52xx.dtsi b/arch/arm/boot/dts/imx6qdl-gw52xx.dtsi index a7100f99123e..54aca3a07ce4 100644 --- a/arch/arm/boot/dts/imx6qdl-gw52xx.dtsi +++ b/arch/arm/boot/dts/imx6qdl-gw52xx.dtsi @@ -153,9 +153,9 @@ &clks { assigned-clocks = <&clks IMX6QDL_CLK_LDB_DI0_SEL>, - <&clks IMX6QDL_CLK_LDB_DI1_SEL>; + <&clks IMX6QDL_CLK_LDB_DI1_SEL>; assigned-clock-parents = <&clks IMX6QDL_CLK_PLL3_USB_OTG>, - <&clks IMX6QDL_CLK_PLL3_USB_OTG>; + <&clks IMX6QDL_CLK_PLL3_USB_OTG>; }; &ecspi3 { diff --git a/arch/arm/boot/dts/imx6qdl-gw53xx.dtsi b/arch/arm/boot/dts/imx6qdl-gw53xx.dtsi index 8953eba0573d..88e5cb3b6be9 100644 --- a/arch/arm/boot/dts/imx6qdl-gw53xx.dtsi +++ b/arch/arm/boot/dts/imx6qdl-gw53xx.dtsi @@ -154,9 +154,9 @@ &clks { assigned-clocks = <&clks IMX6QDL_CLK_LDB_DI0_SEL>, - <&clks IMX6QDL_CLK_LDB_DI1_SEL>; + <&clks IMX6QDL_CLK_LDB_DI1_SEL>; assigned-clock-parents = <&clks IMX6QDL_CLK_PLL3_USB_OTG>, - <&clks IMX6QDL_CLK_PLL3_USB_OTG>; + <&clks IMX6QDL_CLK_PLL3_USB_OTG>; }; &fec { diff --git a/arch/arm/boot/dts/imx6qdl-gw54xx.dtsi b/arch/arm/boot/dts/imx6qdl-gw54xx.dtsi index 6ac41c7ed32e..1753ab720b0b 100644 --- a/arch/arm/boot/dts/imx6qdl-gw54xx.dtsi +++ b/arch/arm/boot/dts/imx6qdl-gw54xx.dtsi @@ -144,9 +144,9 @@ &clks { assigned-clocks = <&clks IMX6QDL_CLK_LDB_DI0_SEL>, - <&clks IMX6QDL_CLK_LDB_DI1_SEL>; + <&clks IMX6QDL_CLK_LDB_DI1_SEL>; assigned-clock-parents = <&clks IMX6QDL_CLK_PLL3_USB_OTG>, - <&clks IMX6QDL_CLK_PLL3_USB_OTG>; + <&clks IMX6QDL_CLK_PLL3_USB_OTG>; }; &fec { diff --git a/arch/arm/boot/dts/imx6qdl-gw552x.dtsi b/arch/arm/boot/dts/imx6qdl-gw552x.dtsi index 805e23674a94..ee83161f674b 100644 --- a/arch/arm/boot/dts/imx6qdl-gw552x.dtsi +++ b/arch/arm/boot/dts/imx6qdl-gw552x.dtsi @@ -291,7 +291,7 @@ MX6QDL_PAD_KEY_COL1__UART5_TX_DATA 0x1b0b1 MX6QDL_PAD_KEY_ROW1__UART5_RX_DATA 0x1b0b1 >; - }; + }; pinctrl_wdog: wdoggrp { fsl,pins = < diff --git a/arch/arm/boot/dts/imx6qdl-icore.dtsi b/arch/arm/boot/dts/imx6qdl-icore.dtsi new file mode 100644 index 000000000000..023839a02dd0 --- /dev/null +++ b/arch/arm/boot/dts/imx6qdl-icore.dtsi @@ -0,0 +1,265 @@ +/* + * Copyright (C) 2016 Amarula Solutions B.V. + * Copyright (C) 2016 Engicam S.r.l. + * + * This file is dual-licensed: you can use it either under the terms + * of the GPL or the X11 license, at your option. Note that this dual + * licensing only applies to this file, and not this project as a + * whole. + * + * a) This file is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * version 2 as published by the Free Software Foundation. + * + * This file is distributed in the hope that it will be useful + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * Or, alternatively + * + * b) Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use + * copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following + * conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED , WITHOUT WARRANTY OF ANY KIND + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + */ + +#include <dt-bindings/gpio/gpio.h> +#include <dt-bindings/input/input.h> + +/ { + memory { + reg = <0x10000000 0x80000000>; + }; + + reg_3p3v: regulator-3p3v { + compatible = "regulator-fixed"; + regulator-name = "3P3V"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-boot-on; + regulator-always-on; + }; + + reg_usb_h1_vbus: regulator-usb-h1-vbus { + compatible = "regulator-fixed"; + regulator-name = "usb_h1_vbus"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + regulator-boot-on; + regulator-always-on; + }; + + reg_usb_otg_vbus: regulator-usb-otg-vbus { + compatible = "regulator-fixed"; + regulator-name = "usb_otg_vbus"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + regulator-boot-on; + regulator-always-on; + }; + + rmii_clk: clock-rmii-clk { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <25000000>; /* 25MHz for example */ + }; +}; + +&can1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_flexcan1>; + xceiver-supply = <®_3p3v>; +}; + +&can2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_flexcan2>; + xceiver-supply = <®_3p3v>; +}; + +&clks { + assigned-clocks = <&clks IMX6QDL_CLK_LVDS2_SEL>; + assigned-clock-parents = <&clks IMX6QDL_CLK_OSC>; +}; + +&fec { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_enet>; + phy-reset-gpios = <&gpio7 12 GPIO_ACTIVE_LOW>; + clocks = <&clks IMX6QDL_CLK_ENET>, <&clks IMX6QDL_CLK_ENET>, <&rmii_clk>; + phy-mode = "rmii"; + status = "okay"; +}; + +&gpmi { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_gpmi_nand>; + nand-on-flash-bbt; + status = "okay"; +}; + +&i2c1 { + clock-frequency = <100000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c1>; + status = "okay"; +}; + +&i2c2 { + clock-frequency = <100000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c2>; + status = "okay"; +}; + +&i2c3 { + clock-frequency = <100000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c3>; + status = "okay"; +}; + +&uart4 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart4>; + status = "okay"; +}; + +&usbh1 { + vbus-supply = <®_usb_h1_vbus>; + disable-over-current; + status = "okay"; +}; + +&usbotg { + vbus-supply = <®_usb_otg_vbus>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usbotg>; + disable-over-current; + status = "okay"; +}; + +&usdhc1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usdhc1>; + cd-gpios = <&gpio1 1 GPIO_ACTIVE_LOW>; + no-1-8-v; + status = "okay"; +}; + +&iomuxc { + pinctrl_enet: enetgrp { + fsl,pins = < + MX6QDL_PAD_ENET_CRS_DV__ENET_RX_EN 0x1b0b0 + MX6QDL_PAD_GPIO_16__ENET_REF_CLK 0x1b0b1 + MX6QDL_PAD_ENET_TX_EN__ENET_TX_EN 0x1b0b0 + MX6QDL_PAD_ENET_RXD1__ENET_RX_DATA1 0x1b0b0 + MX6QDL_PAD_ENET_RXD0__ENET_RX_DATA0 0x1b0b0 + MX6QDL_PAD_ENET_TXD1__ENET_TX_DATA1 0x1b0b0 + MX6QDL_PAD_ENET_TXD0__ENET_TX_DATA0 0x1b0b0 + MX6QDL_PAD_ENET_MDC__ENET_MDC 0x1b0b0 + MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x1b0b0 + MX6QDL_PAD_ENET_REF_CLK__GPIO1_IO23 0x1b0b0 + MX6QDL_PAD_GPIO_17__GPIO7_IO12 0x1b0b0 + >; + }; + + pinctrl_flexcan1: flexcan1grp { + fsl,pins = < + MX6QDL_PAD_KEY_ROW2__FLEXCAN1_RX 0x1b020 + MX6QDL_PAD_KEY_COL2__FLEXCAN1_TX 0x1b020 + >; + }; + + pinctrl_flexcan2: flexcan2grp { + fsl,pins = < + MX6QDL_PAD_KEY_COL4__FLEXCAN2_TX 0x1b020 + MX6QDL_PAD_KEY_ROW4__FLEXCAN2_RX 0x1b020 + >; + }; + + pinctrl_gpmi_nand: gpmi-nand { + fsl,pins = < + MX6QDL_PAD_NANDF_CLE__NAND_CLE 0xb0b1 + MX6QDL_PAD_NANDF_ALE__NAND_ALE 0xb0b1 + MX6QDL_PAD_NANDF_WP_B__NAND_WP_B 0xb0b1 + MX6QDL_PAD_NANDF_RB0__NAND_READY_B 0xb000 + MX6QDL_PAD_NANDF_CS0__NAND_CE0_B 0xb0b1 + MX6QDL_PAD_NANDF_CS1__NAND_CE1_B 0xb0b1 + MX6QDL_PAD_SD4_CMD__NAND_RE_B 0xb0b1 + MX6QDL_PAD_SD4_CLK__NAND_WE_B 0xb0b1 + MX6QDL_PAD_NANDF_D0__NAND_DATA00 0xb0b1 + MX6QDL_PAD_NANDF_D1__NAND_DATA01 0xb0b1 + MX6QDL_PAD_NANDF_D2__NAND_DATA02 0xb0b1 + MX6QDL_PAD_NANDF_D3__NAND_DATA03 0xb0b1 + MX6QDL_PAD_NANDF_D4__NAND_DATA04 0xb0b1 + MX6QDL_PAD_NANDF_D5__NAND_DATA05 0xb0b1 + MX6QDL_PAD_NANDF_D6__NAND_DATA06 0xb0b1 + MX6QDL_PAD_NANDF_D7__NAND_DATA07 0xb0b1 + MX6QDL_PAD_SD4_DAT0__NAND_DQS 0x00b1 + >; + }; + + pinctrl_i2c1: i2c1grp { + fsl,pins = < + MX6QDL_PAD_EIM_D21__I2C1_SCL 0x4001b8b1 + MX6QDL_PAD_EIM_D28__I2C1_SDA 0x4001b8b1 + >; + }; + + pinctrl_i2c2: i2c2grp { + fsl,pins = < + MX6QDL_PAD_EIM_EB2__I2C2_SCL 0x4001b8b1 + MX6QDL_PAD_KEY_ROW3__I2C2_SDA 0x4001b8b1 + >; + }; + + pinctrl_i2c3: i2c3grp { + fsl,pins = < + MX6QDL_PAD_GPIO_5__I2C3_SCL 0x4001b8b1 + MX6QDL_PAD_EIM_D18__I2C3_SDA 0x4001b8b1 + MX6QDL_PAD_GPIO_0__CCM_CLKO1 0x130b0 + >; + }; + + pinctrl_uart4: uart4grp { + fsl,pins = < + MX6QDL_PAD_KEY_COL0__UART4_TX_DATA 0x1b0b1 + MX6QDL_PAD_KEY_ROW0__UART4_RX_DATA 0x1b0b1 + >; + }; + + pinctrl_usbotg: usbotggrp { + fsl,pins = < + MX6QDL_PAD_GPIO_1__USB_OTG_ID 0x17059 + >; + }; + + pinctrl_usdhc1: usdhc1grp { + fsl,pins = < + MX6QDL_PAD_SD1_CMD__SD1_CMD 0x17070 + MX6QDL_PAD_SD1_CLK__SD1_CLK 0x10070 + MX6QDL_PAD_SD1_DAT0__SD1_DATA0 0x17070 + MX6QDL_PAD_SD1_DAT1__SD1_DATA1 0x17070 + MX6QDL_PAD_SD1_DAT2__SD1_DATA2 0x17070 + MX6QDL_PAD_SD1_DAT3__SD1_DATA3 0x17070 + >; + }; +}; diff --git a/arch/arm/boot/dts/imx6qdl-nit6xlite.dtsi b/arch/arm/boot/dts/imx6qdl-nit6xlite.dtsi index 880bd782a5b7..63acd54f5278 100644 --- a/arch/arm/boot/dts/imx6qdl-nit6xlite.dtsi +++ b/arch/arm/boot/dts/imx6qdl-nit6xlite.dtsi @@ -97,15 +97,6 @@ }; }; - bt_rfkill { - compatible = "rfkill-gpio"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_bt_rfkill>; - gpios = <&gpio6 8 GPIO_ACTIVE_HIGH>; - name = "bt_rfkill"; - type = <2>; - }; - gpio-keys { compatible = "gpio-keys"; pinctrl-names = "default"; @@ -160,7 +151,7 @@ }; }; - backlight_lcd { + backlight-lcd { compatible = "pwm-backlight"; pwms = <&pwm1 0 5000000>; brightness-levels = <0 4 8 16 32 64 128 255>; @@ -169,7 +160,7 @@ status = "okay"; }; - backlight_lvds0: backlight_lvds0 { + backlight_lvds0: backlight-lvds0 { compatible = "pwm-backlight"; pwms = <&pwm4 0 5000000>; brightness-levels = <0 4 8 16 32 64 128 255>; @@ -178,7 +169,7 @@ status = "okay"; }; - panel_lvds0 { + panel-lvds0 { compatible = "hannstar,hsd100pxn1"; backlight = <&backlight_lvds0>; @@ -328,19 +319,6 @@ >; }; - pinctrl_bt_rfkill: bt_rfkillgrp { - fsl,pins = < - /* BT wake */ - MX6QDL_PAD_NANDF_D2__GPIO2_IO02 0x1b0b0 - /* BT reset */ - MX6QDL_PAD_NANDF_ALE__GPIO6_IO08 0x0b0b0 - /* BT reg en */ - MX6QDL_PAD_NANDF_CS2__GPIO6_IO15 0x1b0b0 - /* BT host wake irq */ - MX6QDL_PAD_NANDF_CS3__GPIO6_IO16 0x100b0 - >; - }; - pinctrl_ecspi1: ecspi1grp { fsl,pins = < MX6QDL_PAD_EIM_D17__ECSPI1_MISO 0x100b1 @@ -374,7 +352,7 @@ >; }; - pinctrl_gpio_keys: gpio_keysgrp { + pinctrl_gpio_keys: gpio-keysgrp { fsl,pins = < /* Home Button: J14 pin 5 */ MX6QDL_PAD_GPIO_18__GPIO7_IO13 0x1b0b0 @@ -457,7 +435,7 @@ >; }; - pinctrl_wlan_vmmc: wlan_vmmcgrp { + pinctrl_wlan_vmmc: wlan-vmmcgrp { fsl,pins = < MX6QDL_PAD_NANDF_CLE__GPIO6_IO07 0x030b0 >; diff --git a/arch/arm/boot/dts/imx6qdl-nitrogen6_max.dtsi b/arch/arm/boot/dts/imx6qdl-nitrogen6_max.dtsi index b0b3220a1fd9..34887a10c5f1 100644 --- a/arch/arm/boot/dts/imx6qdl-nitrogen6_max.dtsi +++ b/arch/arm/boot/dts/imx6qdl-nitrogen6_max.dtsi @@ -229,7 +229,7 @@ }; }; - backlight_lcd: backlight_lcd { + backlight_lcd: backlight-lcd { compatible = "pwm-backlight"; pwms = <&pwm1 0 5000000>; brightness-levels = <0 4 8 16 32 64 128 255>; @@ -238,7 +238,7 @@ status = "okay"; }; - backlight_lvds0: backlight_lvds0 { + backlight_lvds0: backlight-lvds0 { compatible = "pwm-backlight"; pwms = <&pwm4 0 5000000>; brightness-levels = <0 4 8 16 32 64 128 255>; @@ -247,7 +247,7 @@ status = "okay"; }; - backlight_lvds1: backlight_lvds1 { + backlight_lvds1: backlight-lvds1 { compatible = "pwm-backlight"; pwms = <&pwm2 0 5000000>; brightness-levels = <0 4 8 16 32 64 128 255>; @@ -282,7 +282,7 @@ }; }; - panel_lcd { + panel-lcd { compatible = "okaya,rs800480t-7x0gp"; backlight = <&backlight_lcd>; @@ -293,7 +293,7 @@ }; }; - panel_lvds0 { + panel-lvds0 { compatible = "hannstar,hsd100pxn1"; backlight = <&backlight_lvds0>; @@ -304,7 +304,7 @@ }; }; - panel_lvds1 { + panel-lvds1 { compatible = "hannstar,hsd100pxn1"; backlight = <&backlight_lvds1>; @@ -447,7 +447,7 @@ }; &iomuxc { - imx6q-nitrogen6_max { + imx6q-nitrogen6-max { pinctrl_audmux: audmuxgrp { fsl,pins = < MX6QDL_PAD_CSI0_DAT7__AUD3_RXD 0x130b0 @@ -504,7 +504,7 @@ >; }; - pinctrl_gpio_keys: gpio_keysgrp { + pinctrl_gpio_keys: gpio-keysgrp { fsl,pins = < /* Power Button */ MX6QDL_PAD_NANDF_D3__GPIO2_IO03 0x1b0b0 @@ -720,7 +720,7 @@ >; }; - pinctrl_wlan_vmmc: wlan_vmmcgrp { + pinctrl_wlan_vmmc: wlan-vmmcgrp { fsl,pins = < MX6QDL_PAD_NANDF_CS0__GPIO6_IO11 0x100b0 MX6QDL_PAD_NANDF_CS2__GPIO6_IO15 0x000b0 diff --git a/arch/arm/boot/dts/imx6qdl-nitrogen6_som2.dtsi b/arch/arm/boot/dts/imx6qdl-nitrogen6_som2.dtsi new file mode 100644 index 000000000000..d80f21abea62 --- /dev/null +++ b/arch/arm/boot/dts/imx6qdl-nitrogen6_som2.dtsi @@ -0,0 +1,770 @@ +/* + * Copyright 2016 Boundary Devices, Inc. + * + * This file is dual-licensed: you can use it either under the terms + * of the GPL or the X11 license, at your option. Note that this dual + * licensing only applies to this file, and not this project as a + * whole. + * + * a) This file is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * version 2 as published by the Free Software Foundation. + * + * This file is distributed in the hope that it will be useful + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * Or, alternatively + * + * b) Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use + * copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following + * conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED , WITHOUT WARRANTY OF ANY KIND + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + */ +#include <dt-bindings/gpio/gpio.h> +#include <dt-bindings/input/input.h> + +/ { + chosen { + stdout-path = &uart2; + }; + + memory { + reg = <0x10000000 0x40000000>; + }; + + backlight_lcd: backlight-lcd { + compatible = "pwm-backlight"; + pwms = <&pwm1 0 5000000>; + brightness-levels = <0 4 8 16 32 64 128 255>; + default-brightness-level = <7>; + power-supply = <®_3p3v>; + status = "okay"; + }; + + backlight_lvds0: backlight-lvds0 { + compatible = "pwm-backlight"; + pwms = <&pwm4 0 5000000>; + brightness-levels = <0 4 8 16 32 64 128 255>; + default-brightness-level = <7>; + power-supply = <®_3p3v>; + status = "okay"; + }; + + backlight_lvds1: backlight-lvds1 { + compatible = "gpio-backlight"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_backlight_lvds1>; + gpios = <&gpio2 31 GPIO_ACTIVE_HIGH>; + default-on; + status = "okay"; + }; + + gpio-keys { + compatible = "gpio-keys"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_gpio_keys>; + + power { + label = "Power Button"; + gpios = <&gpio2 3 GPIO_ACTIVE_LOW>; + linux,code = <KEY_POWER>; + wakeup-source; + }; + + menu { + label = "Menu"; + gpios = <&gpio2 1 GPIO_ACTIVE_LOW>; + linux,code = <KEY_MENU>; + }; + + home { + label = "Home"; + gpios = <&gpio2 4 GPIO_ACTIVE_LOW>; + linux,code = <KEY_HOME>; + }; + + back { + label = "Back"; + gpios = <&gpio2 2 GPIO_ACTIVE_LOW>; + linux,code = <KEY_BACK>; + }; + + volume-up { + label = "Volume Up"; + gpios = <&gpio7 13 GPIO_ACTIVE_LOW>; + linux,code = <KEY_VOLUMEUP>; + }; + + volume-down { + label = "Volume Down"; + gpios = <&gpio7 1 GPIO_ACTIVE_LOW>; + linux,code = <KEY_VOLUMEDOWN>; + }; + }; + + lcd_display: display@di0 { + compatible = "fsl,imx-parallel-display"; + #address-cells = <1>; + #size-cells = <0>; + interface-pix-fmt = "bgr666"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_j15>; + status = "okay"; + + port@0 { + reg = <0>; + + lcd_display_in: endpoint { + remote-endpoint = <&ipu1_di0_disp0>; + }; + }; + + port@1 { + reg = <1>; + + lcd_display_out: endpoint { + remote-endpoint = <&lcd_panel_in>; + }; + }; + }; + + panel-lcd { + compatible = "okaya,rs800480t-7x0gp"; + backlight = <&backlight_lcd>; + + port { + lcd_panel_in: endpoint { + remote-endpoint = <&lcd_display_out>; + }; + }; + }; + + panel-lvds0 { + compatible = "hannstar,hsd100pxn1"; + backlight = <&backlight_lvds0>; + + port { + panel_in_lvds0: endpoint { + remote-endpoint = <&lvds0_out>; + }; + }; + }; + + panel-lvds1 { + compatible = "hannstar,hsd100pxn1"; + backlight = <&backlight_lvds1>; + + port { + panel_in_lvds1: endpoint { + remote-endpoint = <&lvds1_out>; + }; + }; + }; + + reg_1p8v: regulator-1v8 { + compatible = "regulator-fixed"; + regulator-name = "1P8V"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + }; + + reg_2p5v: regulator-2v5 { + compatible = "regulator-fixed"; + regulator-name = "2P5V"; + regulator-min-microvolt = <2500000>; + regulator-max-microvolt = <2500000>; + regulator-always-on; + }; + + reg_3p3v: regulator-3v3 { + compatible = "regulator-fixed"; + regulator-name = "3P3V"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + reg_can_xcvr: regulator-can-xcvr { + compatible = "regulator-fixed"; + regulator-name = "CAN XCVR"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_can_xcvr>; + gpio = <&gpio1 2 GPIO_ACTIVE_LOW>; + }; + + reg_usb_h1_vbus: regulator-usb-h1-vbus { + compatible = "regulator-fixed"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usbh1>; + regulator-name = "usb_h1_vbus"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + gpio = <&gpio7 12 GPIO_ACTIVE_HIGH>; + enable-active-high; + regulator-always-on; + }; + + reg_usb_otg_vbus: regulator-usb-otg-vbus { + compatible = "regulator-fixed"; + regulator-name = "usb_otg_vbus"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + gpio = <&gpio3 22 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + + reg_wlan_vmmc: regulator-wlan-vmmc { + compatible = "regulator-fixed"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_wlan_vmmc>; + regulator-name = "reg_wlan_vmmc"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + gpio = <&gpio6 15 GPIO_ACTIVE_HIGH>; + startup-delay-us = <70000>; + enable-active-high; + }; + + sound { + compatible = "fsl,imx6q-nitrogen6_som2-sgtl5000", + "fsl,imx-audio-sgtl5000"; + model = "imx6q-nitrogen6_som2-sgtl5000"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_sgtl5000>; + ssi-controller = <&ssi1>; + audio-codec = <&codec>; + audio-routing = + "MIC_IN", "Mic Jack", + "Mic Jack", "Mic Bias", + "Headphone Jack", "HP_OUT"; + mux-int-port = <1>; + mux-ext-port = <3>; + }; +}; + +&audmux { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_audmux>; + status = "okay"; +}; + +&can1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_can1>; + xceiver-supply = <®_can_xcvr>; + status = "okay"; +}; + +&clks { + assigned-clocks = <&clks IMX6QDL_CLK_LDB_DI0_SEL>, + <&clks IMX6QDL_CLK_LDB_DI1_SEL>; + assigned-clock-parents = <&clks IMX6QDL_CLK_PLL3_USB_OTG>, + <&clks IMX6QDL_CLK_PLL3_USB_OTG>; +}; + +&ecspi1 { + fsl,spi-num-chipselects = <1>; + cs-gpios = <&gpio3 19 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_ecspi1>; + status = "okay"; + + flash: m25p80@0 { + compatible = "microchip,sst25vf016b"; + spi-max-frequency = <20000000>; + reg = <0>; + }; +}; + +&fec { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_enet>; + phy-mode = "rgmii"; + interrupts-extended = <&gpio1 6 IRQ_TYPE_LEVEL_HIGH>, + <&intc 0 119 IRQ_TYPE_LEVEL_HIGH>; + fsl,err006687-workaround-present; + status = "okay"; +}; + +&hdmi { + ddc-i2c-bus = <&i2c2>; + status = "okay"; +}; + +&i2c1 { + clock-frequency = <100000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c1>; + status = "okay"; + + codec: sgtl5000@0a { + compatible = "fsl,sgtl5000"; + reg = <0x0a>; + clocks = <&clks IMX6QDL_CLK_CKO>; + VDDA-supply = <®_2p5v>; + VDDIO-supply = <®_3p3v>; + }; + + rtc@68 { + compatible = "st,rv4162"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_rv4162>; + reg = <0x68>; + interrupts-extended = <&gpio6 7 IRQ_TYPE_LEVEL_LOW>; + }; +}; + +&i2c2 { + clock-frequency = <100000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c2>; + status = "okay"; +}; + +&i2c3 { + clock-frequency = <100000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c3>; + status = "okay"; + + touchscreen@04 { + compatible = "eeti,egalax_ts"; + reg = <0x04>; + interrupt-parent = <&gpio1>; + interrupts = <9 IRQ_TYPE_EDGE_FALLING>; + wakeup-gpios = <&gpio1 9 GPIO_ACTIVE_LOW>; + }; + + touchscreen@38 { + compatible = "edt,edt-ft5x06"; + reg = <0x38>; + interrupt-parent = <&gpio1>; + interrupts = <9 IRQ_TYPE_EDGE_FALLING>; + }; +}; + +&iomuxc { + pinctrl_audmux: audmuxgrp { + fsl,pins = < + MX6QDL_PAD_CSI0_DAT7__AUD3_RXD 0x130b0 + MX6QDL_PAD_CSI0_DAT4__AUD3_TXC 0x130b0 + MX6QDL_PAD_CSI0_DAT5__AUD3_TXD 0x110b0 + MX6QDL_PAD_CSI0_DAT6__AUD3_TXFS 0x130b0 + >; + }; + + pinctrl_backlight_lvds1: backlight-lvds1grp { + fsl,pins = < + MX6QDL_PAD_EIM_EB3__GPIO2_IO31 0x0b0b0 + >; + }; + + pinctrl_can1: can1grp { + fsl,pins = < + MX6QDL_PAD_KEY_COL2__FLEXCAN1_TX 0x1b0b0 + MX6QDL_PAD_KEY_ROW2__FLEXCAN1_RX 0x1b0b0 + >; + }; + + pinctrl_can_xcvr: can-xcvrgrp { + fsl,pins = < + /* Flexcan XCVR enable */ + MX6QDL_PAD_GPIO_2__GPIO1_IO02 0x0b0b0 + >; + }; + + pinctrl_ecspi1: ecspi1grp { + fsl,pins = < + MX6QDL_PAD_EIM_D17__ECSPI1_MISO 0x100b1 + MX6QDL_PAD_EIM_D18__ECSPI1_MOSI 0x100b1 + MX6QDL_PAD_EIM_D16__ECSPI1_SCLK 0x100b1 + MX6QDL_PAD_EIM_D19__GPIO3_IO19 0x000b1 + >; + }; + + pinctrl_enet: enetgrp { + fsl,pins = < + MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x1b0b0 + MX6QDL_PAD_ENET_MDC__ENET_MDC 0x1b0b0 + MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x100b0 + MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x100b0 + MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x100b0 + MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x100b0 + MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x100b0 + MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x100b0 + MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x100b0 + MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b0b0 + MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x130b0 + MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x1b0b0 + MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x130b0 + MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b0b0 + MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x130b0 + MX6QDL_PAD_ENET_RXD0__GPIO1_IO27 0x030b0 + MX6QDL_PAD_ENET_TX_EN__GPIO1_IO28 0x1b0b0 + MX6QDL_PAD_GPIO_6__ENET_IRQ 0x000b1 + >; + }; + + pinctrl_gpio_keys: gpio-keysgrp { + fsl,pins = < + /* Power Button */ + MX6QDL_PAD_NANDF_D3__GPIO2_IO03 0x1b0b0 + /* Menu Button */ + MX6QDL_PAD_NANDF_D1__GPIO2_IO01 0x1b0b0 + /* Home Button */ + MX6QDL_PAD_NANDF_D4__GPIO2_IO04 0x1b0b0 + /* Back Button */ + MX6QDL_PAD_NANDF_D2__GPIO2_IO02 0x1b0b0 + /* Volume Up Button */ + MX6QDL_PAD_GPIO_18__GPIO7_IO13 0x1b0b0 + /* Volume Down Button */ + MX6QDL_PAD_SD3_DAT4__GPIO7_IO01 0x1b0b0 + >; + }; + + pinctrl_i2c1: i2c1grp { + fsl,pins = < + MX6QDL_PAD_EIM_D21__I2C1_SCL 0x4001b8b1 + MX6QDL_PAD_EIM_D28__I2C1_SDA 0x4001b8b1 + >; + }; + + pinctrl_i2c2: i2c2grp { + fsl,pins = < + MX6QDL_PAD_KEY_COL3__I2C2_SCL 0x4001b8b1 + MX6QDL_PAD_KEY_ROW3__I2C2_SDA 0x4001b8b1 + >; + }; + + pinctrl_i2c3: i2c3grp { + fsl,pins = < + MX6QDL_PAD_GPIO_5__I2C3_SCL 0x4001b8b1 + MX6QDL_PAD_GPIO_16__I2C3_SDA 0x4001b8b1 + MX6QDL_PAD_GPIO_9__GPIO1_IO09 0x1b0b0 + >; + }; + + pinctrl_i2c3mux: i2c3muxgrp { + fsl,pins = < + /* PCIe I2C enable */ + MX6QDL_PAD_EIM_OE__GPIO2_IO25 0x000b0 + >; + }; + + pinctrl_j15: j15grp { + fsl,pins = < + MX6QDL_PAD_DI0_DISP_CLK__IPU1_DI0_DISP_CLK 0x10 + MX6QDL_PAD_DI0_PIN15__IPU1_DI0_PIN15 0x10 + MX6QDL_PAD_DI0_PIN2__IPU1_DI0_PIN02 0x10 + MX6QDL_PAD_DI0_PIN3__IPU1_DI0_PIN03 0x10 + MX6QDL_PAD_DISP0_DAT0__IPU1_DISP0_DATA00 0x10 + MX6QDL_PAD_DISP0_DAT1__IPU1_DISP0_DATA01 0x10 + MX6QDL_PAD_DISP0_DAT2__IPU1_DISP0_DATA02 0x10 + MX6QDL_PAD_DISP0_DAT3__IPU1_DISP0_DATA03 0x10 + MX6QDL_PAD_DISP0_DAT4__IPU1_DISP0_DATA04 0x10 + MX6QDL_PAD_DISP0_DAT5__IPU1_DISP0_DATA05 0x10 + MX6QDL_PAD_DISP0_DAT6__IPU1_DISP0_DATA06 0x10 + MX6QDL_PAD_DISP0_DAT7__IPU1_DISP0_DATA07 0x10 + MX6QDL_PAD_DISP0_DAT8__IPU1_DISP0_DATA08 0x10 + MX6QDL_PAD_DISP0_DAT9__IPU1_DISP0_DATA09 0x10 + MX6QDL_PAD_DISP0_DAT10__IPU1_DISP0_DATA10 0x10 + MX6QDL_PAD_DISP0_DAT11__IPU1_DISP0_DATA11 0x10 + MX6QDL_PAD_DISP0_DAT12__IPU1_DISP0_DATA12 0x10 + MX6QDL_PAD_DISP0_DAT13__IPU1_DISP0_DATA13 0x10 + MX6QDL_PAD_DISP0_DAT14__IPU1_DISP0_DATA14 0x10 + MX6QDL_PAD_DISP0_DAT15__IPU1_DISP0_DATA15 0x10 + MX6QDL_PAD_DISP0_DAT16__IPU1_DISP0_DATA16 0x10 + MX6QDL_PAD_DISP0_DAT17__IPU1_DISP0_DATA17 0x10 + MX6QDL_PAD_DISP0_DAT18__IPU1_DISP0_DATA18 0x10 + MX6QDL_PAD_DISP0_DAT19__IPU1_DISP0_DATA19 0x10 + MX6QDL_PAD_DISP0_DAT20__IPU1_DISP0_DATA20 0x10 + MX6QDL_PAD_DISP0_DAT21__IPU1_DISP0_DATA21 0x10 + MX6QDL_PAD_DISP0_DAT22__IPU1_DISP0_DATA22 0x10 + MX6QDL_PAD_DISP0_DAT23__IPU1_DISP0_DATA23 0x10 + >; + }; + + pinctrl_pcie: pciegrp { + fsl,pins = < + /* PCIe reset */ + MX6QDL_PAD_EIM_BCLK__GPIO6_IO31 0x030b0 + MX6QDL_PAD_EIM_DA4__GPIO3_IO04 0x030b0 + >; + }; + + pinctrl_pwm1: pwm1grp { + fsl,pins = < + MX6QDL_PAD_SD1_DAT3__PWM1_OUT 0x030b1 + >; + }; + + pinctrl_pwm3: pwm3grp { + fsl,pins = < + MX6QDL_PAD_SD1_DAT1__PWM3_OUT 0x030b1 + >; + }; + + pinctrl_pwm4: pwm4grp { + fsl,pins = < + MX6QDL_PAD_SD1_CMD__PWM4_OUT 0x030b1 + >; + }; + + pinctrl_rv4162: rv4162grp { + fsl,pins = < + MX6QDL_PAD_NANDF_CLE__GPIO6_IO07 0x1b0b0 + >; + }; + + pinctrl_sgtl5000: sgtl5000grp { + fsl,pins = < + MX6QDL_PAD_GPIO_0__CCM_CLKO1 0x000b0 + MX6QDL_PAD_EIM_D29__GPIO3_IO29 0x130b0 + MX6QDL_PAD_EIM_DA2__GPIO3_IO02 0x130b0 + MX6QDL_PAD_ENET_RX_ER__GPIO1_IO24 0x130b0 + >; + }; + + pinctrl_uart1: uart1grp { + fsl,pins = < + MX6QDL_PAD_SD3_DAT7__UART1_TX_DATA 0x1b0b1 + MX6QDL_PAD_SD3_DAT6__UART1_RX_DATA 0x1b0b1 + >; + }; + + pinctrl_uart2: uart2grp { + fsl,pins = < + MX6QDL_PAD_EIM_D26__UART2_TX_DATA 0x1b0b1 + MX6QDL_PAD_EIM_D27__UART2_RX_DATA 0x1b0b1 + >; + }; + + pinctrl_uart3: uart3grp { + fsl,pins = < + MX6QDL_PAD_EIM_D24__UART3_TX_DATA 0x1b0b1 + MX6QDL_PAD_EIM_D25__UART3_RX_DATA 0x1b0b1 + MX6QDL_PAD_EIM_D23__UART3_CTS_B 0x1b0b1 + MX6QDL_PAD_EIM_D31__UART3_RTS_B 0x1b0b1 + >; + }; + + pinctrl_usbh1: usbh1grp { + fsl,pins = < + MX6QDL_PAD_GPIO_17__GPIO7_IO12 0x030b0 + >; + }; + + pinctrl_usbotg: usbotggrp { + fsl,pins = < + MX6QDL_PAD_GPIO_1__USB_OTG_ID 0x17059 + MX6QDL_PAD_KEY_COL4__USB_OTG_OC 0x1b0b0 + /* power enable, high active */ + MX6QDL_PAD_EIM_D22__GPIO3_IO22 0x030b0 + >; + }; + + pinctrl_usdhc2: usdhc2grp { + fsl,pins = < + MX6QDL_PAD_SD2_CLK__SD2_CLK 0x10071 + MX6QDL_PAD_SD2_CMD__SD2_CMD 0x17071 + MX6QDL_PAD_SD2_DAT0__SD2_DATA0 0x17071 + MX6QDL_PAD_SD2_DAT1__SD2_DATA1 0x17071 + MX6QDL_PAD_SD2_DAT2__SD2_DATA2 0x17071 + MX6QDL_PAD_SD2_DAT3__SD2_DATA3 0x17071 + >; + }; + + pinctrl_usdhc3: usdhc3grp { + fsl,pins = < + MX6QDL_PAD_SD3_CLK__SD3_CLK 0x10071 + MX6QDL_PAD_SD3_CMD__SD3_CMD 0x17071 + MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x17071 + MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x17071 + MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x17071 + MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x17071 + MX6QDL_PAD_SD3_DAT5__GPIO7_IO00 0x1b0b0 + >; + }; + + pinctrl_usdhc4: usdhc4grp { + fsl,pins = < + MX6QDL_PAD_SD4_CMD__SD4_CMD 0x17059 + MX6QDL_PAD_SD4_CLK__SD4_CLK 0x10059 + MX6QDL_PAD_SD4_DAT0__SD4_DATA0 0x17059 + MX6QDL_PAD_SD4_DAT1__SD4_DATA1 0x17059 + MX6QDL_PAD_SD4_DAT2__SD4_DATA2 0x17059 + MX6QDL_PAD_SD4_DAT3__SD4_DATA3 0x17059 + MX6QDL_PAD_SD4_DAT4__SD4_DATA4 0x17059 + MX6QDL_PAD_SD4_DAT5__SD4_DATA5 0x17059 + MX6QDL_PAD_SD4_DAT6__SD4_DATA6 0x17059 + MX6QDL_PAD_SD4_DAT7__SD4_DATA7 0x17059 + >; + }; + + pinctrl_wlan_vmmc: wlan-vmmcgrp { + fsl,pins = < + MX6QDL_PAD_NANDF_CS1__GPIO6_IO14 0x100b0 + MX6QDL_PAD_NANDF_CS2__GPIO6_IO15 0x030b0 + MX6QDL_PAD_NANDF_CS3__GPIO6_IO16 0x030b0 + MX6QDL_PAD_SD1_CLK__OSC32K_32K_OUT 0x000b0 + >; + }; +}; + +&ipu1_di0_disp0 { + remote-endpoint = <&lcd_display_in>; +}; + +&ldb { + status = "okay"; + + lvds-channel@0 { + fsl,data-mapping = "spwg"; + fsl,data-width = <18>; + status = "okay"; + + port@4 { + reg = <4>; + + lvds0_out: endpoint { + remote-endpoint = <&panel_in_lvds0>; + }; + }; + }; + + lvds-channel@1 { + fsl,data-mapping = "spwg"; + fsl,data-width = <18>; + status = "okay"; + + port@4 { + reg = <4>; + + lvds1_out: endpoint { + remote-endpoint = <&panel_in_lvds1>; + }; + }; + }; +}; + +&pcie { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pcie>; + reset-gpio = <&gpio6 31 GPIO_ACTIVE_LOW>; + status = "okay"; +}; + +&pwm1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pwm1>; + status = "okay"; +}; + +&pwm3 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pwm3>; + status = "okay"; +}; + +&pwm4 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pwm4>; + status = "okay"; +}; + +&ssi1 { + status = "okay"; +}; + +&uart1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart1>; + status = "okay"; +}; + +&uart2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart2>; + status = "okay"; +}; + +&uart3 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart3>; + uart-has-rtscts; + status = "okay"; +}; + +&usbh1 { + vbus-supply = <®_usb_h1_vbus>; + status = "okay"; +}; + +&usbotg { + vbus-supply = <®_usb_otg_vbus>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usbotg>; + disable-over-current; + status = "okay"; +}; + +&usdhc2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usdhc2>; + bus-width = <4>; + non-removable; + vmmc-supply = <®_wlan_vmmc>; + cap-power-off-card; + keep-power-in-suspend; + status = "okay"; + + #address-cells = <1>; + #size-cells = <0>; + wlcore: wlcore@2 { + compatible = "ti,wl1271"; + reg = <2>; + interrupt-parent = <&gpio6>; + interrupts = <14 IRQ_TYPE_LEVEL_HIGH>; + ref-clock-frequency = <38400000>; + }; +}; + +&usdhc3 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usdhc3>; + cd-gpios = <&gpio7 0 GPIO_ACTIVE_LOW>; + bus-width = <4>; + vmmc-supply = <®_3p3v>; + status = "okay"; +}; + +&usdhc4 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usdhc4>; + bus-width = <8>; + non-removable; + vmmc-supply = <®_1p8v>; + keep-power-in-suspend; + status = "okay"; +}; diff --git a/arch/arm/boot/dts/imx6qdl-nitrogen6x.dtsi b/arch/arm/boot/dts/imx6qdl-nitrogen6x.dtsi index db868bc42c0f..e476d01959ea 100644 --- a/arch/arm/boot/dts/imx6qdl-nitrogen6x.dtsi +++ b/arch/arm/boot/dts/imx6qdl-nitrogen6x.dtsi @@ -167,7 +167,7 @@ mux-ext-port = <3>; }; - backlight_lcd: backlight_lcd { + backlight_lcd: backlight-lcd { compatible = "pwm-backlight"; pwms = <&pwm1 0 5000000>; brightness-levels = <0 4 8 16 32 64 128 255>; @@ -176,7 +176,7 @@ status = "okay"; }; - backlight_lvds: backlight_lvds { + backlight_lvds: backlight-lvds { compatible = "pwm-backlight"; pwms = <&pwm4 0 5000000>; brightness-levels = <0 4 8 16 32 64 128 255>; @@ -211,7 +211,7 @@ }; }; - lcd_panel { + panel-lcd { compatible = "okaya,rs800480t-7x0gp"; backlight = <&backlight_lcd>; @@ -222,7 +222,7 @@ }; }; - panel { + panel-lvds0 { compatible = "hannstar,hsd100pxn1"; backlight = <&backlight_lvds>; @@ -413,7 +413,7 @@ >; }; - pinctrl_gpio_keys: gpio_keysgrp { + pinctrl_gpio_keys: gpio-keysgrp { fsl,pins = < /* Power Button */ MX6QDL_PAD_NANDF_D3__GPIO2_IO03 0x1b0b0 @@ -561,7 +561,7 @@ >; }; - pinctrl_wlan_vmmc: wlan_vmmcgrp { + pinctrl_wlan_vmmc: wlan-vmmcgrp { fsl,pins = < MX6QDL_PAD_NANDF_CS0__GPIO6_IO11 0x100b0 MX6QDL_PAD_NANDF_CS2__GPIO6_IO15 0x000b0 diff --git a/arch/arm/boot/dts/imx6qdl-phytec-pfla02.dtsi b/arch/arm/boot/dts/imx6qdl-phytec-pfla02.dtsi index e0280cac2484..e9801a26f3b4 100644 --- a/arch/arm/boot/dts/imx6qdl-phytec-pfla02.dtsi +++ b/arch/arm/boot/dts/imx6qdl-phytec-pfla02.dtsi @@ -427,10 +427,10 @@ }; &usdhc3 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usdhc3 + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usdhc3 &pinctrl_usdhc3_cdwp>; cd-gpios = <&gpio1 27 GPIO_ACTIVE_LOW>; wp-gpios = <&gpio1 29 GPIO_ACTIVE_HIGH>; - status = "disabled"; + status = "disabled"; }; diff --git a/arch/arm/boot/dts/imx6qdl-sabreauto.dtsi b/arch/arm/boot/dts/imx6qdl-sabreauto.dtsi index e000e6f12bf5..52390ba83e81 100644 --- a/arch/arm/boot/dts/imx6qdl-sabreauto.dtsi +++ b/arch/arm/boot/dts/imx6qdl-sabreauto.dtsi @@ -283,7 +283,7 @@ VD-supply = <®_audio>; VLS-supply = <®_audio>; VLC-supply = <®_audio>; - }; + }; }; @@ -613,8 +613,6 @@ &weim { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_weim_nor &pinctrl_weim_cs0>; - #address-cells = <2>; - #size-cells = <1>; ranges = <0 0 0x08000000 0x08000000>; status = "disabled"; /* pin conflict with SPI NOR */ diff --git a/arch/arm/boot/dts/imx6qdl-sabrelite.dtsi b/arch/arm/boot/dts/imx6qdl-sabrelite.dtsi index 81dd6cd1937d..1f9076e271e4 100644 --- a/arch/arm/boot/dts/imx6qdl-sabrelite.dtsi +++ b/arch/arm/boot/dts/imx6qdl-sabrelite.dtsi @@ -153,7 +153,7 @@ mux-ext-port = <4>; }; - backlight_lcd: backlight_lcd { + backlight_lcd: backlight-lcd { compatible = "pwm-backlight"; pwms = <&pwm1 0 5000000>; brightness-levels = <0 4 8 16 32 64 128 255>; @@ -162,7 +162,7 @@ status = "okay"; }; - backlight_lvds: backlight_lvds { + backlight_lvds: backlight-lvds { compatible = "pwm-backlight"; pwms = <&pwm4 0 5000000>; brightness-levels = <0 4 8 16 32 64 128 255>; @@ -197,7 +197,7 @@ }; }; - lcd_panel { + panel-lcd { compatible = "okaya,rs800480t-7x0gp"; backlight = <&backlight_lcd>; @@ -208,7 +208,7 @@ }; }; - panel { + panel-lvds0 { compatible = "hannstar,hsd100pxn1"; backlight = <&backlight_lvds>; @@ -378,7 +378,7 @@ >; }; - pinctrl_gpio_keys: gpio_keysgrp { + pinctrl_gpio_keys: gpio-keysgrp { fsl,pins = < /* Power Button */ MX6QDL_PAD_NANDF_D3__GPIO2_IO03 0x1b0b0 diff --git a/arch/arm/boot/dts/imx6qdl-sabresd.dtsi b/arch/arm/boot/dts/imx6qdl-sabresd.dtsi index 8e9e0d98db2f..55ef53571fdd 100644 --- a/arch/arm/boot/dts/imx6qdl-sabresd.dtsi +++ b/arch/arm/boot/dts/imx6qdl-sabresd.dtsi @@ -129,8 +129,8 @@ pinctrl-0 = <&pinctrl_gpio_leds>; red { - gpios = <&gpio1 2 0>; - default-state = "on"; + gpios = <&gpio1 2 0>; + default-state = "on"; }; }; diff --git a/arch/arm/boot/dts/imx6qdl-tx6.dtsi b/arch/arm/boot/dts/imx6qdl-tx6.dtsi index ac9529f85593..2bf2e623ac1e 100644 --- a/arch/arm/boot/dts/imx6qdl-tx6.dtsi +++ b/arch/arm/boot/dts/imx6qdl-tx6.dtsi @@ -429,8 +429,8 @@ pinctrl_edt_ft5x06: edt-ft5x06grp { fsl,pins = < MX6QDL_PAD_NANDF_CS2__GPIO6_IO15 0x1b0b0 /* Interrupt */ - MX6QDL_PAD_EIM_A16__GPIO2_IO22 0x1b0b0 /* Reset */ - MX6QDL_PAD_EIM_A17__GPIO2_IO21 0x1b0b0 /* Wake */ + MX6QDL_PAD_EIM_A16__GPIO2_IO22 0x1b0b0 /* Reset */ + MX6QDL_PAD_EIM_A17__GPIO2_IO21 0x1b0b0 /* Wake */ >; }; @@ -481,21 +481,21 @@ pinctrl_gpmi_nand: gpminandgrp { fsl,pins = < - MX6QDL_PAD_NANDF_CLE__NAND_CLE 0x0b0b1 - MX6QDL_PAD_NANDF_ALE__NAND_ALE 0x0b0b1 - MX6QDL_PAD_NANDF_WP_B__NAND_WP_B 0x0b0b1 + MX6QDL_PAD_NANDF_CLE__NAND_CLE 0x0b0b1 + MX6QDL_PAD_NANDF_ALE__NAND_ALE 0x0b0b1 + MX6QDL_PAD_NANDF_WP_B__NAND_WP_B 0x0b0b1 MX6QDL_PAD_NANDF_RB0__NAND_READY_B 0x0b000 - MX6QDL_PAD_NANDF_CS0__NAND_CE0_B 0x0b0b1 - MX6QDL_PAD_SD4_CMD__NAND_RE_B 0x0b0b1 - MX6QDL_PAD_SD4_CLK__NAND_WE_B 0x0b0b1 - MX6QDL_PAD_NANDF_D0__NAND_DATA00 0x0b0b1 - MX6QDL_PAD_NANDF_D1__NAND_DATA01 0x0b0b1 - MX6QDL_PAD_NANDF_D2__NAND_DATA02 0x0b0b1 - MX6QDL_PAD_NANDF_D3__NAND_DATA03 0x0b0b1 - MX6QDL_PAD_NANDF_D4__NAND_DATA04 0x0b0b1 - MX6QDL_PAD_NANDF_D5__NAND_DATA05 0x0b0b1 - MX6QDL_PAD_NANDF_D6__NAND_DATA06 0x0b0b1 - MX6QDL_PAD_NANDF_D7__NAND_DATA07 0x0b0b1 + MX6QDL_PAD_NANDF_CS0__NAND_CE0_B 0x0b0b1 + MX6QDL_PAD_SD4_CMD__NAND_RE_B 0x0b0b1 + MX6QDL_PAD_SD4_CLK__NAND_WE_B 0x0b0b1 + MX6QDL_PAD_NANDF_D0__NAND_DATA00 0x0b0b1 + MX6QDL_PAD_NANDF_D1__NAND_DATA01 0x0b0b1 + MX6QDL_PAD_NANDF_D2__NAND_DATA02 0x0b0b1 + MX6QDL_PAD_NANDF_D3__NAND_DATA03 0x0b0b1 + MX6QDL_PAD_NANDF_D4__NAND_DATA04 0x0b0b1 + MX6QDL_PAD_NANDF_D5__NAND_DATA05 0x0b0b1 + MX6QDL_PAD_NANDF_D6__NAND_DATA06 0x0b0b1 + MX6QDL_PAD_NANDF_D7__NAND_DATA07 0x0b0b1 >; }; diff --git a/arch/arm/boot/dts/imx6qdl-wandboard-revb1.dtsi b/arch/arm/boot/dts/imx6qdl-wandboard-revb1.dtsi index ef7fa62b9898..a32089132263 100644 --- a/arch/arm/boot/dts/imx6qdl-wandboard-revb1.dtsi +++ b/arch/arm/boot/dts/imx6qdl-wandboard-revb1.dtsi @@ -28,7 +28,7 @@ MX6QDL_PAD_EIM_D29__GPIO3_IO29 0x80000000 /* RGMII_nRST */ MX6QDL_PAD_EIM_DA13__GPIO3_IO13 0x80000000 /* BT_ON */ MX6QDL_PAD_EIM_DA14__GPIO3_IO14 0x80000000 /* BT_WAKE */ - MX6QDL_PAD_EIM_DA15__GPIO3_IO15 0x80000000 /* BT_HOST_WAKE */ + MX6QDL_PAD_EIM_DA15__GPIO3_IO15 0x80000000 /* BT_HOST_WAKE */ >; }; }; diff --git a/arch/arm/boot/dts/imx6qdl-wandboard.dtsi b/arch/arm/boot/dts/imx6qdl-wandboard.dtsi index 2b9c2be436f9..82dc5744ae19 100644 --- a/arch/arm/boot/dts/imx6qdl-wandboard.dtsi +++ b/arch/arm/boot/dts/imx6qdl-wandboard.dtsi @@ -129,8 +129,8 @@ pinctrl_i2c1: i2c1grp { fsl,pins = < - MX6QDL_PAD_EIM_D21__I2C1_SCL 0x4001b8b1 - MX6QDL_PAD_EIM_D28__I2C1_SDA 0x4001b8b1 + MX6QDL_PAD_EIM_D21__I2C1_SCL 0x4001b8b1 + MX6QDL_PAD_EIM_D28__I2C1_SDA 0x4001b8b1 >; }; diff --git a/arch/arm/boot/dts/imx6qdl.dtsi b/arch/arm/boot/dts/imx6qdl.dtsi index b13b0b2db881..53e6e63cbb02 100644 --- a/arch/arm/boot/dts/imx6qdl.dtsi +++ b/arch/arm/boot/dts/imx6qdl.dtsi @@ -13,9 +13,10 @@ #include <dt-bindings/clock/imx6qdl-clock.h> #include <dt-bindings/interrupt-controller/arm-gic.h> -#include "skeleton.dtsi" - / { + #address-cells = <1>; + #size-cells = <1>; + aliases { ethernet0 = &fec; can0 = &can1; @@ -204,9 +205,9 @@ #interrupt-cells = <1>; interrupt-map-mask = <0 0 0 0x7>; interrupt-map = <0 0 0 1 &gpc GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>, - <0 0 0 2 &gpc GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>, - <0 0 0 3 &gpc GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>, - <0 0 0 4 &gpc GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>; + <0 0 0 2 &gpc GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>, + <0 0 0 3 &gpc GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>, + <0 0 0 4 &gpc GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>; clocks = <&clks IMX6QDL_CLK_PCIE_AXI>, <&clks IMX6QDL_CLK_LVDS1_GATE>, <&clks IMX6QDL_CLK_PCIE_REF_125M>; @@ -1092,10 +1093,13 @@ }; weim: weim@021b8000 { + #address-cells = <2>; + #size-cells = <1>; compatible = "fsl,imx6q-weim"; reg = <0x021b8000 0x4000>; interrupts = <0 14 IRQ_TYPE_LEVEL_HIGH>; clocks = <&clks IMX6QDL_CLK_EIM_SLOW>; + fsl,weim-cs-gpr = <&gpr>; }; ocotp: ocotp@021bc000 { diff --git a/arch/arm/boot/dts/imx6qp.dtsi b/arch/arm/boot/dts/imx6qp.dtsi index 886dbf2eca49..e0fdd0fda361 100644 --- a/arch/arm/boot/dts/imx6qp.dtsi +++ b/arch/arm/boot/dts/imx6qp.dtsi @@ -85,5 +85,12 @@ pcie: pcie@0x01000000 { compatible = "fsl,imx6qp-pcie", "snps,dw-pcie"; }; + + aips-bus@02100000 { + mmdc0: mmdc@021b0000 { /* MMDC0 */ + compatible = "fsl,imx6qp-mmdc", "fsl,imx6q-mmdc"; + reg = <0x021b0000 0x4000>; + }; + }; }; }; diff --git a/arch/arm/boot/dts/imx6sl.dtsi b/arch/arm/boot/dts/imx6sl.dtsi index 02378db3f5fc..4fd6de29f07d 100644 --- a/arch/arm/boot/dts/imx6sl.dtsi +++ b/arch/arm/boot/dts/imx6sl.dtsi @@ -8,11 +8,13 @@ */ #include <dt-bindings/interrupt-controller/irq.h> -#include "skeleton.dtsi" #include "imx6sl-pinfunc.h" #include <dt-bindings/clock/imx6sl-clock.h> / { + #address-cells = <1>; + #size-cells = <1>; + aliases { ethernet0 = &fec; gpio0 = &gpio1; @@ -893,8 +895,11 @@ }; weim: weim@021b8000 { + #address-cells = <2>; + #size-cells = <1>; reg = <0x021b8000 0x4000>; interrupts = <0 14 IRQ_TYPE_LEVEL_HIGH>; + fsl,weim-cs-gpr = <&gpr>; }; ocotp: ocotp@021bc000 { diff --git a/arch/arm/boot/dts/imx6sx-sdb.dtsi b/arch/arm/boot/dts/imx6sx-sdb.dtsi index 9d70cfd40aff..da815527a7f8 100644 --- a/arch/arm/boot/dts/imx6sx-sdb.dtsi +++ b/arch/arm/boot/dts/imx6sx-sdb.dtsi @@ -192,10 +192,10 @@ }; &i2c4 { - clock-frequency = <100000>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c4>; - status = "okay"; + clock-frequency = <100000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c4>; + status = "okay"; codec: wm8962@1a { compatible = "wlf,wm8962"; @@ -290,6 +290,14 @@ status = "okay"; }; +&usbphy1 { + fsl,tx-d-cal = <106>; +}; + +&usbphy2 { + fsl,tx-d-cal = <106>; +}; + &usdhc2 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_usdhc2>; diff --git a/arch/arm/boot/dts/imx6sx-udoo-neo-basic.dts b/arch/arm/boot/dts/imx6sx-udoo-neo-basic.dts new file mode 100644 index 000000000000..0c1fc1a8f913 --- /dev/null +++ b/arch/arm/boot/dts/imx6sx-udoo-neo-basic.dts @@ -0,0 +1,69 @@ +/* + * Copyright (c) 2016 Andreas Färber + * + * This file is dual-licensed: you can use it either under the terms + * of the GPL or the X11 license, at your option. Note that this dual + * licensing only applies to this file, and not this project as a + * whole. + * + * a) This library is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of the + * License, or (at your option) any later version. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * Or, alternatively, + * + * b) Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, + * copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following + * conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + */ + +/dts-v1/; + +#include "imx6sx-udoo-neo.dtsi" + +/ { + model = "UDOO Neo Basic"; + compatible = "udoo,neobasic", "fsl,imx6sx"; + + memory { + reg = <0x80000000 0x20000000>; + }; +}; + +&fec1 { + phy-handle = <ðphy1>; + status = "okay"; + + mdio { + #address-cells = <1>; + #size-cells = <0>; + + ethphy1: ethernet-phy@0 { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <0>; + }; + }; +}; diff --git a/arch/arm/boot/dts/imx6sx-udoo-neo-extended.dts b/arch/arm/boot/dts/imx6sx-udoo-neo-extended.dts new file mode 100644 index 000000000000..5d6c2274ee2b --- /dev/null +++ b/arch/arm/boot/dts/imx6sx-udoo-neo-extended.dts @@ -0,0 +1,54 @@ +/* + * Copyright (c) 2016 Andreas Färber + * + * This file is dual-licensed: you can use it either under the terms + * of the GPL or the X11 license, at your option. Note that this dual + * licensing only applies to this file, and not this project as a + * whole. + * + * a) This library is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of the + * License, or (at your option) any later version. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * Or, alternatively, + * + * b) Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, + * copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following + * conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + */ + +/dts-v1/; + +#include "imx6sx-udoo-neo.dtsi" + +/ { + model = "UDOO Neo Extended"; + compatible = "udoo,neoextended", "fsl,imx6sx"; + + memory { + reg = <0x80000000 0x40000000>; + }; +}; diff --git a/arch/arm/boot/dts/imx6sx-udoo-neo-full.dts b/arch/arm/boot/dts/imx6sx-udoo-neo-full.dts new file mode 100644 index 000000000000..653ceb29e28b --- /dev/null +++ b/arch/arm/boot/dts/imx6sx-udoo-neo-full.dts @@ -0,0 +1,69 @@ +/* + * Copyright (c) 2016 Andreas Färber + * + * This file is dual-licensed: you can use it either under the terms + * of the GPL or the X11 license, at your option. Note that this dual + * licensing only applies to this file, and not this project as a + * whole. + * + * a) This library is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of the + * License, or (at your option) any later version. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * Or, alternatively, + * + * b) Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, + * copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following + * conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + */ + +/dts-v1/; + +#include "imx6sx-udoo-neo.dtsi" + +/ { + model = "UDOO Neo Full"; + compatible = "udoo,neofull", "fsl,imx6sx"; + + memory { + reg = <0x80000000 0x40000000>; + }; +}; + +&fec1 { + phy-handle = <ðphy1>; + status = "okay"; + + mdio { + #address-cells = <1>; + #size-cells = <0>; + + ethphy1: ethernet-phy@0 { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <0>; + }; + }; +}; diff --git a/arch/arm/boot/dts/imx6sx-udoo-neo.dtsi b/arch/arm/boot/dts/imx6sx-udoo-neo.dtsi new file mode 100644 index 000000000000..2b65d26f4396 --- /dev/null +++ b/arch/arm/boot/dts/imx6sx-udoo-neo.dtsi @@ -0,0 +1,293 @@ +/* + * Copyright (c) 2016 Andreas Färber + * + * This file is dual-licensed: you can use it either under the terms + * of the GPL or the X11 license, at your option. Note that this dual + * licensing only applies to this file, and not this project as a + * whole. + * + * a) This library is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of the + * License, or (at your option) any later version. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * Or, alternatively, + * + * b) Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, + * copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following + * conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + */ + +#include "imx6sx.dtsi" + +/ { + compatible = "fsl,imx6sx"; + + chosen { + stdout-path = "serial0:115200n8"; + }; + + leds { + compatible = "gpio-leds"; + + red { + label = "udoo-neo:red:mmc"; + gpios = <&gpio6 0 GPIO_ACTIVE_HIGH>; + default-state = "off"; + linux,default-trigger = "mmc0"; + }; + + orange { + label = "udoo-neo:orange:user"; + gpios = <&gpio4 6 GPIO_ACTIVE_HIGH>; + default-state = "keep"; + }; + }; + + reg_sdio_pwr: regulator-sdio-pwr { + compatible = "regulator-fixed"; + gpio = <&gpio6 1 GPIO_ACTIVE_HIGH>; + enable-active-high; + regulator-name = "SDIO_PWR"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-boot-on; + }; +}; + +&cpu0 { + arm-supply = <&sw1a_reg>; + soc-supply = <&sw1c_reg>; +}; + +&fec1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_enet1>; + phy-mode = "rmii"; + phy-reset-gpios = <&gpio2 1 GPIO_ACTIVE_LOW>; +}; + +&i2c1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c1>; + clock-frequency = <100000>; + status = "okay"; + + pmic: pmic@08 { + compatible = "fsl,pfuze3000"; + reg = <0x08>; + + regulators { + sw1a_reg: sw1a { + regulator-min-microvolt = <700000>; + regulator-max-microvolt = <1475000>; + regulator-boot-on; + regulator-always-on; + regulator-ramp-delay = <6250>; + }; + + sw1c_reg: sw1b { + regulator-min-microvolt = <700000>; + regulator-max-microvolt = <1475000>; + regulator-boot-on; + regulator-always-on; + regulator-ramp-delay = <6250>; + }; + + sw2_reg: sw2 { + regulator-min-microvolt = <1500000>; + regulator-max-microvolt = <1850000>; + regulator-boot-on; + regulator-always-on; + }; + + sw3a_reg: sw3 { + regulator-min-microvolt = <900000>; + regulator-max-microvolt = <1650000>; + regulator-boot-on; + regulator-always-on; + }; + + swbst_reg: swbst { + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5150000>; + }; + + snvs_reg: vsnvs { + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <3000000>; + regulator-boot-on; + regulator-always-on; + }; + + vref_reg: vrefddr { + regulator-boot-on; + regulator-always-on; + }; + + vgen1_reg: vldo1 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + vgen2_reg: vldo2 { + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <1550000>; + }; + + vgen3_reg: vccsd { + regulator-min-microvolt = <2850000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + vgen4_reg: v33 { + regulator-min-microvolt = <2850000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + vgen5_reg: vldo3 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + vgen6_reg: vldo4 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + }; + }; +}; + +&iomuxc { + pinctrl_enet1: enet1grp { + fsl,pins = + <MX6SX_PAD_ENET1_CRS__GPIO2_IO_1 0xa0b1>, + <MX6SX_PAD_ENET1_MDC__ENET1_MDC 0xa0b1>, + <MX6SX_PAD_ENET1_MDIO__ENET1_MDIO 0xa0b1>, + <MX6SX_PAD_RGMII1_TD0__ENET1_TX_DATA_0 0xa0b1>, + <MX6SX_PAD_RGMII1_TD1__ENET1_TX_DATA_1 0xa0b1>, + <MX6SX_PAD_RGMII1_TX_CTL__ENET1_TX_EN 0xa0b1>, + + <MX6SX_PAD_ENET1_TX_CLK__ENET1_REF_CLK1 0x3081>, + <MX6SX_PAD_ENET2_TX_CLK__GPIO2_IO_9 0x3081>, + <MX6SX_PAD_RGMII1_RD0__ENET1_RX_DATA_0 0x3081>, + <MX6SX_PAD_RGMII1_RD1__ENET1_RX_DATA_1 0x3081>, + <MX6SX_PAD_RGMII1_RX_CTL__ENET1_RX_EN 0x3081>, + <MX6SX_PAD_RGMII1_RXC__ENET1_RX_ER 0x3081>, + + <MX6SX_PAD_ENET2_RX_CLK__ENET2_REF_CLK_25M 0x91>; + }; + + pinctrl_i2c1: i2c1grp { + fsl,pins = + <MX6SX_PAD_GPIO1_IO00__I2C1_SCL 0x4001b8b1>, + <MX6SX_PAD_GPIO1_IO01__I2C1_SDA 0x4001b8b1>; + }; + + pinctrl_uart1: uart1grp { + fsl,pins = + <MX6SX_PAD_GPIO1_IO04__UART1_TX 0x1b0b1>, + <MX6SX_PAD_GPIO1_IO05__UART1_RX 0x1b0b1>; + }; + + pinctrl_uart2: uart2grp { + fsl,pins = + <MX6SX_PAD_GPIO1_IO06__UART2_TX 0x1b0b1>, + <MX6SX_PAD_GPIO1_IO07__UART2_RX 0x1b0b1>; + }; + + pinctrl_uart5: uart5grp { + fsl,pins = + <MX6SX_PAD_SD4_DATA4__UART5_RX 0x1b0b1>, + <MX6SX_PAD_SD4_DATA5__UART5_TX 0x1b0b1>; + }; + + pinctrl_uart6: uart6grp { + fsl,pins = + <MX6SX_PAD_CSI_DATA00__UART6_RI_B 0x1b0b1>, + <MX6SX_PAD_CSI_DATA01__UART6_DSR_B 0x1b0b1>, + <MX6SX_PAD_CSI_DATA02__UART6_DTR_B 0x1b0b1>, + <MX6SX_PAD_CSI_DATA03__UART6_DCD_B 0x1b0b1>, + <MX6SX_PAD_CSI_DATA04__UART6_RX 0x1b0b1>, + <MX6SX_PAD_CSI_DATA05__UART6_TX 0x1b0b1>, + <MX6SX_PAD_CSI_DATA06__UART6_RTS_B 0x1b0b1>, + <MX6SX_PAD_CSI_DATA07__UART6_CTS_B 0x1b0b1>; + }; + + pinctrl_usdhc2: usdhc2grp { + fsl,pins = + <MX6SX_PAD_SD2_CMD__USDHC2_CMD 0x17059>, + <MX6SX_PAD_SD2_CLK__USDHC2_CLK 0x10059>, + <MX6SX_PAD_SD2_DATA0__USDHC2_DATA0 0x17059>, + <MX6SX_PAD_SD2_DATA1__USDHC2_DATA1 0x17059>, + <MX6SX_PAD_SD2_DATA2__USDHC2_DATA2 0x17059>, + <MX6SX_PAD_SD2_DATA3__USDHC2_DATA3 0x17059>, + <MX6SX_PAD_SD1_DATA0__GPIO6_IO_2 0x17059>; /* CD */ + }; +}; + +&uart1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart1>; + status = "okay"; +}; + +/* Cortex-M4 serial */ +&uart2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart2>; + status = "disabled"; +}; + +/* Arduino serial */ +&uart5 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart5>; + status = "disabled"; +}; + +&uart6 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart6>; + uart-has-rtscts; + status = "disabled"; +}; + +&usdhc2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usdhc2>; + vmmc-supply = <®_sdio_pwr>; + bus-width = <4>; + cd-gpios = <&gpio6 2 GPIO_ACTIVE_LOW>; + no-1-8-v; + keep-power-in-suspend; + wakeup-source; + status = "okay"; +}; diff --git a/arch/arm/boot/dts/imx6sx.dtsi b/arch/arm/boot/dts/imx6sx.dtsi index 1a473e83efbf..076a30f9bcae 100644 --- a/arch/arm/boot/dts/imx6sx.dtsi +++ b/arch/arm/boot/dts/imx6sx.dtsi @@ -11,9 +11,11 @@ #include <dt-bindings/input/input.h> #include <dt-bindings/interrupt-controller/arm-gic.h> #include "imx6sx-pinfunc.h" -#include "skeleton.dtsi" / { + #address-cells = <1>; + #size-cells = <1>; + aliases { can0 = &flexcan1; can1 = &flexcan2; @@ -858,7 +860,7 @@ fsl,num-tx-queues=<3>; fsl,num-rx-queues=<3>; status = "disabled"; - }; + }; mlb: mlb@0218c000 { reg = <0x0218c000 0x4000>; @@ -968,10 +970,13 @@ }; weim: weim@021b8000 { + #address-cells = <2>; + #size-cells = <1>; compatible = "fsl,imx6sx-weim", "fsl,imx6q-weim"; reg = <0x021b8000 0x4000>; interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>; clocks = <&clks IMX6SX_CLK_EIM_SLOW>; + fsl,weim-cs-gpr = <&gpr>; }; ocotp: ocotp@021bc000 { @@ -1143,7 +1148,7 @@ lcdif1: lcdif@02220000 { compatible = "fsl,imx6sx-lcdif", "fsl,imx28-lcdif"; reg = <0x02220000 0x4000>; - interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>; + interrupts = <GIC_SPI 5 IRQ_TYPE_EDGE_RISING>; clocks = <&clks IMX6SX_CLK_LCDIF1_PIX>, <&clks IMX6SX_CLK_LCDIF_APB>, <&clks IMX6SX_CLK_DISPLAY_AXI>; @@ -1154,7 +1159,7 @@ lcdif2: lcdif@02224000 { compatible = "fsl,imx6sx-lcdif", "fsl,imx28-lcdif"; reg = <0x02224000 0x4000>; - interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>; + interrupts = <GIC_SPI 6 IRQ_TYPE_EDGE_RISING>; clocks = <&clks IMX6SX_CLK_LCDIF2_PIX>, <&clks IMX6SX_CLK_LCDIF_APB>, <&clks IMX6SX_CLK_DISPLAY_AXI>; @@ -1181,7 +1186,7 @@ fsl,adck-max-frequency = <30000000>, <40000000>, <20000000>; status = "disabled"; - }; + }; adc2: adc@02284000 { compatible = "fsl,imx6sx-adc", "fsl,vf610-adc"; @@ -1192,7 +1197,7 @@ fsl,adck-max-frequency = <30000000>, <40000000>, <20000000>; status = "disabled"; - }; + }; wdog3: wdog@02288000 { compatible = "fsl,imx6sx-wdt", "fsl,imx21-wdt"; diff --git a/arch/arm/boot/dts/imx6ul-14x14-evk.dts b/arch/arm/boot/dts/imx6ul-14x14-evk.dts index e281d5087d4a..00f98e5bfcaf 100644 --- a/arch/arm/boot/dts/imx6ul-14x14-evk.dts +++ b/arch/arm/boot/dts/imx6ul-14x14-evk.dts @@ -225,7 +225,7 @@ }; &usbotg1 { - dr_mode = "peripheral"; + dr_mode = "otg"; status = "okay"; }; @@ -235,6 +235,14 @@ status = "okay"; }; +&usbphy1 { + fsl,tx-d-cal = <106>; +}; + +&usbphy2 { + fsl,tx-d-cal = <106>; +}; + &usdhc1 { pinctrl-names = "default", "state_100mhz", "state_200mhz"; pinctrl-0 = <&pinctrl_usdhc1>; diff --git a/arch/arm/boot/dts/imx6ul-liteboard.dts b/arch/arm/boot/dts/imx6ul-liteboard.dts new file mode 100644 index 000000000000..6e04cb9202f4 --- /dev/null +++ b/arch/arm/boot/dts/imx6ul-liteboard.dts @@ -0,0 +1,147 @@ +/* + * Copyright 2016 Grinn + * + * Author: Marcin Niestroj <m.niestroj@grinn-global.com> + * + * This file is dual-licensed: you can use it either under the terms + * of the GPL or the X11 license, at your option. Note that this dual + * licensing only applies to this file, and not this project as a + * whole. + * + * a) This file is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * version 2 as published by the Free Software Foundation. + * + * This file is distributed in the hope that it will be useful + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * Or, alternatively + * + * b) Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use + * copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following + * conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED , WITHOUT WARRANTY OF ANY KIND + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + */ + +/dts-v1/; + +#include "imx6ul-litesom.dtsi" + +/ { + model = "Grinn i.MX6UL liteBoard"; + compatible = "grinn,imx6ul-liteboard", "grinn,imx6ul-litesom", + "fsl,imx6ul"; + + chosen { + stdout-path = &uart1; + }; + + reg_usb_otg1_vbus: regulator-usb-otg1-vbus { + compatible = "regulator-fixed"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usb_otg1_vbus>; + regulator-name = "usb_otg1_vbus"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + gpio = <&gpio2 8 GPIO_ACTIVE_LOW>; + }; +}; + +&iomuxc { + pinctrl_enet1: enet1grp { + fsl,pins = < + MX6UL_PAD_GPIO1_IO07__ENET1_MDC 0x1b0b0 + MX6UL_PAD_GPIO1_IO06__ENET1_MDIO 0x1b0b0 + MX6UL_PAD_ENET1_RX_EN__ENET1_RX_EN 0x1b0b0 + MX6UL_PAD_ENET1_RX_ER__ENET1_RX_ER 0x1b0b0 + MX6UL_PAD_ENET1_RX_DATA0__ENET1_RDATA00 0x1b0b0 + MX6UL_PAD_ENET1_RX_DATA1__ENET1_RDATA01 0x1b0b0 + MX6UL_PAD_ENET1_TX_EN__ENET1_TX_EN 0x1b0b0 + MX6UL_PAD_ENET1_TX_DATA0__ENET1_TDATA00 0x1b0b0 + MX6UL_PAD_ENET1_TX_DATA1__ENET1_TDATA01 0x1b0b0 + MX6UL_PAD_ENET1_TX_CLK__ENET1_REF_CLK1 0x4001b031 + >; + }; + + pinctrl_uart1: uart1grp { + fsl,pins = < + MX6UL_PAD_UART1_TX_DATA__UART1_DCE_TX 0x1b0b1 + MX6UL_PAD_UART1_RX_DATA__UART1_DCE_RX 0x1b0b1 + >; + }; + + pinctrl_usdhc1: usdhc1grp { + fsl,pins = < + MX6UL_PAD_UART1_RTS_B__GPIO1_IO19 0x17059 + MX6UL_PAD_SD1_CMD__USDHC1_CMD 0x17059 + MX6UL_PAD_SD1_CLK__USDHC1_CLK 0x10071 + MX6UL_PAD_SD1_DATA0__USDHC1_DATA0 0x17059 + MX6UL_PAD_SD1_DATA1__USDHC1_DATA1 0x17059 + MX6UL_PAD_SD1_DATA2__USDHC1_DATA2 0x17059 + MX6UL_PAD_SD1_DATA3__USDHC1_DATA3 0x17059 + >; + }; + + pinctrl_usb_otg1_vbus: usb-otg1-vbus { + fsl,pins = < + MX6UL_PAD_ENET2_RX_DATA0__GPIO2_IO08 0x79 + >; + }; +}; + +&fec1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_enet1>; + phy-mode = "rmii"; + phy-handle = <ðphy0>; + status = "okay"; + + mdio { + #address-cells = <1>; + #size-cells = <0>; + + ethphy0: ethernet-phy@0 { + reg = <0>; + }; + }; +}; + +&uart1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart1>; + status = "okay"; +}; + +&usbotg1 { + vbus-supply = <®_usb_otg1_vbus>; + dr_mode = "host"; + status = "okay"; +}; + +&usdhc1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usdhc1>; + cd-gpios = <&gpio1 19 GPIO_ACTIVE_LOW>; + no-1-8-v; + keep-power-in-suspend; + wakeup-source; + status = "okay"; +}; diff --git a/arch/arm/boot/dts/imx6ul-litesom.dtsi b/arch/arm/boot/dts/imx6ul-litesom.dtsi new file mode 100644 index 000000000000..461292d33417 --- /dev/null +++ b/arch/arm/boot/dts/imx6ul-litesom.dtsi @@ -0,0 +1,82 @@ +/* + * Copyright 2016 Grinn + * + * Author: Marcin Niestroj <m.niestroj@grinn-global.com> + * + * This file is dual-licensed: you can use it either under the terms + * of the GPL or the X11 license, at your option. Note that this dual + * licensing only applies to this file, and not this project as a + * whole. + * + * a) This file is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * version 2 as published by the Free Software Foundation. + * + * This file is distributed in the hope that it will be useful + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * Or, alternatively + * + * b) Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use + * copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following + * conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED , WITHOUT WARRANTY OF ANY KIND + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + */ + +#include "imx6ul.dtsi" + +/ { + model = "Grinn i.MX6UL liteSOM"; + compatible = "grinn,imx6ul-litesom", "fsl,imx6ul"; + + memory { + reg = <0x80000000 0x20000000>; + }; +}; + +&iomuxc { + pinctrl_usdhc2: usdhc2grp { + fsl,pins = < + MX6UL_PAD_NAND_RE_B__USDHC2_CLK 0x10069 + MX6UL_PAD_NAND_WE_B__USDHC2_CMD 0x17059 + MX6UL_PAD_NAND_DATA00__USDHC2_DATA0 0x17059 + MX6UL_PAD_NAND_DATA01__USDHC2_DATA1 0x17059 + MX6UL_PAD_NAND_DATA02__USDHC2_DATA2 0x17059 + MX6UL_PAD_NAND_DATA03__USDHC2_DATA3 0x17059 + MX6UL_PAD_NAND_DATA04__USDHC2_DATA4 0x17059 + MX6UL_PAD_NAND_DATA05__USDHC2_DATA5 0x17059 + MX6UL_PAD_NAND_DATA06__USDHC2_DATA6 0x17059 + MX6UL_PAD_NAND_DATA07__USDHC2_DATA7 0x17059 + MX6UL_PAD_NAND_ALE__USDHC2_RESET_B 0x17059 + >; + }; +}; + +&usdhc2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usdhc2>; + no-1-8-v; + non-removable; + keep-power-in-suspend; + wakeup-source; + bus-width = <8>; + status = "okay"; +}; diff --git a/arch/arm/boot/dts/imx6ul.dtsi b/arch/arm/boot/dts/imx6ul.dtsi index c5c05fdccc78..39845a7e0463 100644 --- a/arch/arm/boot/dts/imx6ul.dtsi +++ b/arch/arm/boot/dts/imx6ul.dtsi @@ -11,9 +11,11 @@ #include <dt-bindings/input/input.h> #include <dt-bindings/interrupt-controller/arm-gic.h> #include "imx6ul-pinfunc.h" -#include "skeleton.dtsi" / { + #address-cells = <1>; + #size-cells = <1>; + aliases { ethernet0 = &fec1; ethernet1 = &fec2; diff --git a/arch/arm/boot/dts/imx6ull-14x14-evk.dts b/arch/arm/boot/dts/imx6ull-14x14-evk.dts new file mode 100644 index 000000000000..db5bc076e1cc --- /dev/null +++ b/arch/arm/boot/dts/imx6ull-14x14-evk.dts @@ -0,0 +1,52 @@ +/* + * Copyright (C) 2016 Freescale Semiconductor, Inc. + * + * This file is dual-licensed: you can use it either under the terms + * of the GPL or the X11 license, at your option. Note that this dual + * licensing only applies to this file, and not this project as a + * whole. + * + * a) This file is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * version 2 as published by the Free Software Foundation. + * + * This file is distributed in the hope that it will be useful + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * Or, alternatively + * + * b) Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use + * copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following + * conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED , WITHOUT WARRANTY OF ANY KIND + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + */ + +#include "imx6ul-14x14-evk.dts" + +/ { + model = "Freescale i.MX6 UlltraLite 14x14 EVK Board"; + compatible = "fsl,imx6ull-14x14-evk", "fsl,imx6ull"; +}; + +&clks { + assigned-clocks = <&clks IMX6UL_CLK_PLL3_PFD2>; + assigned-clock-rates = <320000000>; +}; diff --git a/arch/arm/boot/dts/imx6ull-pinfunc.h b/arch/arm/boot/dts/imx6ull-pinfunc.h new file mode 100644 index 000000000000..118202336691 --- /dev/null +++ b/arch/arm/boot/dts/imx6ull-pinfunc.h @@ -0,0 +1,56 @@ +/* + * Copyright (C) 2016 Freescale Semiconductor, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#ifndef __DTS_IMX6ULL_PINFUNC_H +#define __DTS_IMX6ULL_PINFUNC_H + +#include "imx6ul-pinfunc.h" +/* + * The pin function ID is a tuple of + * <mux_reg conf_reg input_reg mux_mode input_val> + */ +#define MX6ULL_PAD_ENET2_RX_DATA0__EPDC_SDDO08 0x00E4 0x0370 0x0000 0x9 0x0 +#define MX6ULL_PAD_ENET2_RX_DATA1__EPDC_SDDO09 0x00E8 0x0374 0x0000 0x9 0x0 +#define MX6ULL_PAD_ENET2_RX_EN__EPDC_SDDO10 0x00EC 0x0378 0x0000 0x9 0x0 +#define MX6ULL_PAD_ENET2_TX_DATA0__EPDC_SDDO11 0x00F0 0x037C 0x0000 0x9 0x0 +#define MX6ULL_PAD_ENET2_TX_DATA1__EPDC_SDDO12 0x00F4 0x0380 0x0000 0x9 0x0 +#define MX6ULL_PAD_ENET2_TX_EN__EPDC_SDDO13 0x00F8 0x0384 0x0000 0x9 0x0 +#define MX6ULL_PAD_ENET2_TX_CLK__EPDC_SDDO14 0x00FC 0x0388 0x0000 0x9 0x0 +#define MX6ULL_PAD_ENET2_RX_ER__EPDC_SDDO15 0x0100 0x038C 0x0000 0x9 0x0 +#define MX6ULL_PAD_LCD_CLK__EPDC_SDCLK 0x0104 0x0390 0x0000 0x9 0x0 +#define MX6ULL_PAD_LCD_ENABLE__EPDC_SDLE 0x0108 0x0394 0x0000 0x9 0x0 +#define MX6ULL_PAD_LCD_HSYNC__EPDC_SDOE 0x010C 0x0398 0x0000 0x9 0x0 +#define MX6ULL_PAD_LCD_VSYNC__EPDC_SDCE0 0x0110 0x039C 0x0000 0x9 0x0 +#define MX6ULL_PAD_LCD_RESET__EPDC_GDOE 0x0114 0x03A0 0x0000 0x9 0x0 +#define MX6ULL_PAD_LCD_DATA00__EPDC_SDDO00 0x0118 0x03A4 0x0000 0x9 0x0 +#define MX6ULL_PAD_LCD_DATA01__EPDC_SDDO01 0x011C 0x03A8 0x0000 0x9 0x0 +#define MX6ULL_PAD_LCD_DATA02__EPDC_SDDO02 0x0120 0x03AC 0x0000 0x9 0x0 +#define MX6ULL_PAD_LCD_DATA03__EPDC_SDDO03 0x0124 0x03B0 0x0000 0x9 0x0 +#define MX6ULL_PAD_LCD_DATA04__EPDC_SDDO04 0x0128 0x03B4 0x0000 0x9 0x0 +#define MX6ULL_PAD_LCD_DATA05__EPDC_SDDO05 0x012C 0x03B8 0x0000 0x9 0x0 +#define MX6ULL_PAD_LCD_DATA06__EPDC_SDDO06 0x0130 0x03BC 0x0000 0x9 0x0 +#define MX6ULL_PAD_LCD_DATA07__EPDC_SDDO07 0x0134 0x03C0 0x0000 0x9 0x0 +#define MX6ULL_PAD_LCD_DATA14__EPDC_SDSHR 0x0150 0x03DC 0x0000 0x9 0x0 +#define MX6ULL_PAD_LCD_DATA15__EPDC_GDRL 0x0154 0x03E0 0x0000 0x9 0x0 +#define MX6ULL_PAD_LCD_DATA16__EPDC_GDCLK 0x0158 0x03E4 0x0000 0x9 0x0 +#define MX6ULL_PAD_LCD_DATA17__EPDC_GDSP 0x015C 0x03E8 0x0000 0x9 0x0 +#define MX6ULL_PAD_LCD_DATA21__EPDC_SDCE1 0x016C 0x03F8 0x0000 0x9 0x0 +#define MX6ULL_PAD_CSI_MCLK__ESAI_TX3_RX2 0x01D4 0x0460 0x0000 0x9 0x0 +#define MX6ULL_PAD_CSI_PIXCLK__ESAI_TX2_RX3 0x01D8 0x0464 0x0000 0x9 0x0 +#define MX6ULL_PAD_CSI_VSYNC__ESAI_TX4_RX1 0x01DC 0x0468 0x0000 0x9 0x0 +#define MX6ULL_PAD_CSI_HSYNC__ESAI_TX1 0x01E0 0x046C 0x0000 0x9 0x0 +#define MX6ULL_PAD_CSI_DATA00__ESAI_TX_HF_CLK 0x01E4 0x0470 0x0000 0x9 0x0 +#define MX6ULL_PAD_CSI_DATA01__ESAI_RX_HF_CLK 0x01E8 0x0474 0x0000 0x9 0x0 +#define MX6ULL_PAD_CSI_DATA02__ESAI_RX_FS 0x01EC 0x0478 0x0000 0x9 0x0 +#define MX6ULL_PAD_CSI_DATA03__ESAI_RX_CLK 0x01F0 0x047C 0x0000 0x9 0x0 +#define MX6ULL_PAD_CSI_DATA04__ESAI_TX_FS 0x01F4 0x0480 0x0000 0x9 0x0 +#define MX6ULL_PAD_CSI_DATA05__ESAI_TX_CLK 0x01F8 0x0484 0x0000 0x9 0x0 +#define MX6ULL_PAD_CSI_DATA06__ESAI_TX5_RX0 0x01FC 0x0488 0x0000 0x9 0x0 +#define MX6ULL_PAD_CSI_DATA07__ESAI_T0 0x0200 0x048C 0x0000 0x9 0x0 + +#endif /* __DTS_IMX6ULL_PINFUNC_H */ diff --git a/arch/arm/boot/dts/imx6ull.dtsi b/arch/arm/boot/dts/imx6ull.dtsi new file mode 100644 index 000000000000..dee8ab8135e1 --- /dev/null +++ b/arch/arm/boot/dts/imx6ull.dtsi @@ -0,0 +1,43 @@ +/* + * Copyright 2016 Freescale Semiconductor, Inc. + * + * This file is dual-licensed: you can use it either under the terms + * of the GPL or the X11 license, at your option. Note that this dual + * licensing only applies to this file, and not this project as a + * whole. + * + * a) This file is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * version 2 as published by the Free Software Foundation. + * + * This file is distributed in the hope that it will be useful + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * Or, alternatively + * + * b) Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use + * copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following + * conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED , WITHOUT WARRANTY OF ANY KIND + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + */ + +#include "imx6ul.dtsi" +#include "imx6ull-pinfunc.h" diff --git a/arch/arm/boot/dts/imx7s.dtsi b/arch/arm/boot/dts/imx7s.dtsi index 0d7d5ac6257b..51dfcc16e4b8 100644 --- a/arch/arm/boot/dts/imx7s.dtsi +++ b/arch/arm/boot/dts/imx7s.dtsi @@ -46,9 +46,11 @@ #include <dt-bindings/input/input.h> #include <dt-bindings/interrupt-controller/arm-gic.h> #include "imx7d-pinfunc.h" -#include "skeleton.dtsi" / { + #address-cells = <1>; + #size-cells = <1>; + aliases { gpio0 = &gpio1; gpio1 = &gpio2; diff --git a/arch/arm/boot/dts/integratorap.dts b/arch/arm/boot/dts/integratorap.dts index 6f16d09dc5a4..e8b249f92fb3 100644 --- a/arch/arm/boot/dts/integratorap.dts +++ b/arch/arm/boot/dts/integratorap.dts @@ -10,6 +10,41 @@ compatible = "arm,integrator-ap"; dma-ranges = <0x80000000 0x0 0x80000000>; + cpus { + #address-cells = <1>; + #size-cells = <0>; + + cpu@0 { + device_type = "cpu"; + /* + * Since the board has pluggable CPU modules, we + * cannot define a proper compatible here. Let the + * boot loader fill in the apropriate compatible + * string if necessary. + */ + /* compatible = "arm,arm926ej-s"; */ + reg = <0>; + /* + * The documentation in ARM DUI 0138E page 3-12 states + * that the maximum frequency for this clock is 200 MHz + * but painful trial-and-error has proved to me that it + * is actually just hanging the system above 71 MHz. + * Sad but true. + */ + /* kHz uV */ + operating-points = <71000 0 + 66000 0 + 60000 0 + 48000 0 + 36000 0 + 24000 0 + 12000 0>; + clocks = <&cmosc>; + clock-names = "cpu"; + clock-latency = <1000000>; /* 1 ms */ + }; + }; + aliases { arm,timer-primary = &timer2; arm,timer-secondary = &timer1; diff --git a/arch/arm/boot/dts/integratorcp.dts b/arch/arm/boot/dts/integratorcp.dts index 1b5e4b006b72..97f38b57a702 100644 --- a/arch/arm/boot/dts/integratorcp.dts +++ b/arch/arm/boot/dts/integratorcp.dts @@ -13,6 +13,32 @@ bootargs = "root=/dev/ram0 console=ttyAMA0,38400n8 earlyprintk"; }; + cpus { + #address-cells = <1>; + #size-cells = <0>; + + cpu@0 { + device_type = "cpu"; + /* + * Since the board has pluggable CPU modules, we + * cannot define a proper compatible here. Let the + * boot loader fill in the apropriate compatible + * string if necessary. + */ + /* compatible = "arm,arm920t"; */ + reg = <0>; + /* + * TBD comment. + */ + /* kHz uV */ + operating-points = <50000 0 + 48000 0>; + clocks = <&cmcore>; + clock-names = "cpu"; + clock-latency = <1000000>; /* 1 ms */ + }; + }; + /* * The Integrator/CP overall clocking architecture can be found in * ARM DUI 0184B page 7-28 "Integrator/CP922T system clocks" which diff --git a/arch/arm/boot/dts/keystone-k2g.dtsi b/arch/arm/boot/dts/keystone-k2g.dtsi index 2919c5190653..63c7cf0c6b6d 100644 --- a/arch/arm/boot/dts/keystone-k2g.dtsi +++ b/arch/arm/boot/dts/keystone-k2g.dtsi @@ -72,6 +72,7 @@ soc { #address-cells = <1>; #size-cells = <1>; + #pinctrl-cells = <1>; compatible = "ti,keystone","simple-bus"; ranges = <0x0 0x0 0x0 0xc0000000>; dma-ranges = <0x80000000 0x8 0x00000000 0x80000000>; diff --git a/arch/arm/boot/dts/keystone-k2l.dtsi b/arch/arm/boot/dts/keystone-k2l.dtsi index 2ee3d0ac2816..0c5e74e79ba2 100644 --- a/arch/arm/boot/dts/keystone-k2l.dtsi +++ b/arch/arm/boot/dts/keystone-k2l.dtsi @@ -59,6 +59,7 @@ reg = <0x02620690 0xc>; #address-cells = <1>; #size-cells = <0>; + #pinctrl-cells = <2>; pinctrl-single,bit-per-mux; pinctrl-single,register-width = <32>; pinctrl-single,function-mask = <0x1>; diff --git a/arch/arm/boot/dts/kirkwood-topkick.dts b/arch/arm/boot/dts/kirkwood-topkick.dts index 1e9a72100a45..330aada6d33f 100644 --- a/arch/arm/boot/dts/kirkwood-topkick.dts +++ b/arch/arm/boot/dts/kirkwood-topkick.dts @@ -4,7 +4,7 @@ #include "kirkwood-6282.dtsi" / { - model = "Univeral Scientific Industrial Co. Topkick-1281P2"; + model = "Universal Scientific Industrial Co. Topkick-1281P2"; compatible = "usi,topkick-1281P2", "usi,topkick", "marvell,kirkwood-88f6282", "marvell,kirkwood"; memory { diff --git a/arch/arm/boot/dts/lpc32xx.dtsi b/arch/arm/boot/dts/lpc32xx.dtsi index b5841fab51c1..d81fe433e3c8 100644 --- a/arch/arm/boot/dts/lpc32xx.dtsi +++ b/arch/arm/boot/dts/lpc32xx.dtsi @@ -479,6 +479,8 @@ compatible = "nxp,lpc3220-pwm"; reg = <0x4005C000 0x4>; clocks = <&clk LPC32XX_CLK_PWM1>; + assigned-clocks = <&clk LPC32XX_CLK_PWM1>; + assigned-clock-parents = <&clk LPC32XX_CLK_PERIPH>; status = "disabled"; }; @@ -486,6 +488,8 @@ compatible = "nxp,lpc3220-pwm"; reg = <0x4005C004 0x4>; clocks = <&clk LPC32XX_CLK_PWM2>; + assigned-clocks = <&clk LPC32XX_CLK_PWM2>; + assigned-clock-parents = <&clk LPC32XX_CLK_PERIPH>; status = "disabled"; }; diff --git a/arch/arm/boot/dts/ls1021a.dtsi b/arch/arm/boot/dts/ls1021a.dtsi index 368e21934285..282d854f4342 100644 --- a/arch/arm/boot/dts/ls1021a.dtsi +++ b/arch/arm/boot/dts/ls1021a.dtsi @@ -47,6 +47,7 @@ #include "skeleton64.dtsi" #include <dt-bindings/interrupt-controller/arm-gic.h> +#include <dt-bindings/thermal/thermal.h> / { compatible = "fsl,ls1021a"; @@ -70,14 +71,15 @@ #address-cells = <1>; #size-cells = <0>; - cpu@f00 { + cpu0: cpu@f00 { compatible = "arm,cortex-a7"; device_type = "cpu"; reg = <0xf00>; clocks = <&cluster1_clk>; + #cooling-cells = <2>; }; - cpu@f01 { + cpu1: cpu@f01 { compatible = "arm,cortex-a7"; device_type = "cpu"; reg = <0xf01>; @@ -251,6 +253,84 @@ }; }; + tmu: tmu@1f00000 { + compatible = "fsl,qoriq-tmu"; + reg = <0x0 0x1f00000 0x0 0x10000>; + interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>; + fsl,tmu-range = <0xb0000 0xa0026 0x80048 0x30061>; + fsl,tmu-calibration = <0x00000000 0x0000000f + 0x00000001 0x00000017 + 0x00000002 0x0000001e + 0x00000003 0x00000026 + 0x00000004 0x0000002e + 0x00000005 0x00000035 + 0x00000006 0x0000003d + 0x00000007 0x00000044 + 0x00000008 0x0000004c + 0x00000009 0x00000053 + 0x0000000a 0x0000005b + 0x0000000b 0x00000064 + + 0x00010000 0x00000011 + 0x00010001 0x0000001c + 0x00010002 0x00000024 + 0x00010003 0x0000002b + 0x00010004 0x00000034 + 0x00010005 0x00000039 + 0x00010006 0x00000042 + 0x00010007 0x0000004c + 0x00010008 0x00000051 + 0x00010009 0x0000005a + 0x0001000a 0x00000063 + + 0x00020000 0x00000013 + 0x00020001 0x00000019 + 0x00020002 0x00000024 + 0x00020003 0x0000002c + 0x00020004 0x00000035 + 0x00020005 0x0000003d + 0x00020006 0x00000046 + 0x00020007 0x00000050 + 0x00020008 0x00000059 + + 0x00030000 0x00000002 + 0x00030001 0x0000000d + 0x00030002 0x00000019 + 0x00030003 0x00000024>; + #thermal-sensor-cells = <1>; + }; + + thermal-zones { + cpu_thermal: cpu-thermal { + polling-delay-passive = <1000>; + polling-delay = <5000>; + + thermal-sensors = <&tmu 0>; + + trips { + cpu_alert: cpu-alert { + temperature = <85000>; + hysteresis = <2000>; + type = "passive"; + }; + cpu_crit: cpu-crit { + temperature = <95000>; + hysteresis = <2000>; + type = "critical"; + }; + }; + + cooling-maps { + map0 { + trip = <&cpu_alert>; + cooling-device = + <&cpu0 THERMAL_NO_LIMIT + THERMAL_NO_LIMIT>; + }; + }; + }; + }; + dspi0: dspi@2100000 { compatible = "fsl,ls1021a-v1.0-dspi"; #address-cells = <1>; diff --git a/arch/arm/boot/dts/mps2-an385.dts b/arch/arm/boot/dts/mps2-an385.dts index 31c374d72a6f..aebbebfc25d1 100644 --- a/arch/arm/boot/dts/mps2-an385.dts +++ b/arch/arm/boot/dts/mps2-an385.dts @@ -59,7 +59,7 @@ stdout-path = "serial0:9600n8"; }; - memory { + memory@21000000 { device_type = "memory"; reg = <0x21000000 0x1000000>; }; diff --git a/arch/arm/boot/dts/mps2-an399.dts b/arch/arm/boot/dts/mps2-an399.dts index 5e7e5ca2edbf..349abf70b2a5 100644 --- a/arch/arm/boot/dts/mps2-an399.dts +++ b/arch/arm/boot/dts/mps2-an399.dts @@ -59,7 +59,7 @@ stdout-path = "serial0:9600n8"; }; - memory { + memory@60000000 { device_type = "memory"; reg = <0x60000000 0x1000000>; }; diff --git a/arch/arm/boot/dts/mps2.dtsi b/arch/arm/boot/dts/mps2.dtsi index efb8a03cb970..23467390558d 100644 --- a/arch/arm/boot/dts/mps2.dtsi +++ b/arch/arm/boot/dts/mps2.dtsi @@ -42,10 +42,12 @@ * OTHER DEALINGS IN THE SOFTWARE. */ -#include "skeleton.dtsi" #include "armv7-m.dtsi" / { + #address-cells = <1>; + #size-cells = <1>; + oscclk0: clk-osc0 { compatible = "fixed-clock"; #clock-cells = <0>; diff --git a/arch/arm/boot/dts/mt2701.dtsi b/arch/arm/boot/dts/mt2701.dtsi index 18596a2c58a1..7eab6f4c4665 100644 --- a/arch/arm/boot/dts/mt2701.dtsi +++ b/arch/arm/boot/dts/mt2701.dtsi @@ -12,8 +12,10 @@ * GNU General Public License for more details. */ +#include <dt-bindings/clock/mt2701-clk.h> #include <dt-bindings/interrupt-controller/irq.h> #include <dt-bindings/interrupt-controller/arm-gic.h> +#include <dt-bindings/reset/mt2701-resets.h> #include "skeleton64.dtsi" #include "mt2701-pinfunc.h" @@ -71,10 +73,18 @@ #clock-cells = <0>; }; - uart_clk: dummy26m { + clk26m: oscillator@0 { compatible = "fixed-clock"; + #clock-cells = <0>; clock-frequency = <26000000>; + clock-output-names = "clk26m"; + }; + + rtc32k: oscillator@1 { + compatible = "fixed-clock"; #clock-cells = <0>; + clock-frequency = <32000>; + clock-output-names = "rtc32k"; }; timer { @@ -104,6 +114,26 @@ reg = <0 0x10005000 0 0x1000>; }; + topckgen: syscon@10000000 { + compatible = "mediatek,mt2701-topckgen", "syscon"; + reg = <0 0x10000000 0 0x1000>; + #clock-cells = <1>; + }; + + infracfg: syscon@10001000 { + compatible = "mediatek,mt2701-infracfg", "syscon"; + reg = <0 0x10001000 0 0x1000>; + #clock-cells = <1>; + #reset-cells = <1>; + }; + + pericfg: syscon@10003000 { + compatible = "mediatek,mt2701-pericfg", "syscon"; + reg = <0 0x10003000 0 0x1000>; + #clock-cells = <1>; + #reset-cells = <1>; + }; + watchdog: watchdog@10007000 { compatible = "mediatek,mt2701-wdt", "mediatek,mt6589-wdt"; @@ -128,6 +158,12 @@ reg = <0 0x10200100 0 0x1c>; }; + apmixedsys: syscon@10209000 { + compatible = "mediatek,mt2701-apmixedsys", "syscon"; + reg = <0 0x10209000 0 0x1000>; + #clock-cells = <1>; + }; + gic: interrupt-controller@10211000 { compatible = "arm,cortex-a7-gic"; interrupt-controller; @@ -144,7 +180,8 @@ "mediatek,mt6577-uart"; reg = <0 0x11002000 0 0x400>; interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_LOW>; - clocks = <&uart_clk>; + clocks = <&pericfg CLK_PERI_UART0_SEL>, <&pericfg CLK_PERI_UART0>; + clock-names = "baud", "bus"; status = "disabled"; }; @@ -153,7 +190,8 @@ "mediatek,mt6577-uart"; reg = <0 0x11003000 0 0x400>; interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_LOW>; - clocks = <&uart_clk>; + clocks = <&pericfg CLK_PERI_UART1_SEL>, <&pericfg CLK_PERI_UART1>; + clock-names = "baud", "bus"; status = "disabled"; }; @@ -162,7 +200,8 @@ "mediatek,mt6577-uart"; reg = <0 0x11004000 0 0x400>; interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_LOW>; - clocks = <&uart_clk>; + clocks = <&pericfg CLK_PERI_UART2_SEL>, <&pericfg CLK_PERI_UART2>; + clock-names = "baud", "bus"; status = "disabled"; }; @@ -171,7 +210,8 @@ "mediatek,mt6577-uart"; reg = <0 0x11005000 0 0x400>; interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_LOW>; - clocks = <&uart_clk>; + clocks = <&pericfg CLK_PERI_UART3_SEL>, <&pericfg CLK_PERI_UART3>; + clock-names = "baud", "bus"; status = "disabled"; }; }; diff --git a/arch/arm/boot/dts/omap2420.dtsi b/arch/arm/boot/dts/omap2420.dtsi index fb712b9aa874..aba542d63d6d 100644 --- a/arch/arm/boot/dts/omap2420.dtsi +++ b/arch/arm/boot/dts/omap2420.dtsi @@ -38,6 +38,7 @@ reg = <0x0 0x1000>; #address-cells = <1>; #size-cells = <1>; + #pinctrl-cells = <1>; ranges = <0 0x0 0x1000>; omap2420_pmx: pinmux@30 { @@ -46,6 +47,7 @@ reg = <0x30 0x0113>; #address-cells = <1>; #size-cells = <0>; + #pinctrl-cells = <1>; pinctrl-single,register-width = <8>; pinctrl-single,function-mask = <0x3f>; }; diff --git a/arch/arm/boot/dts/omap2430.dtsi b/arch/arm/boot/dts/omap2430.dtsi index 455aaea407dd..84635eeb99cd 100644 --- a/arch/arm/boot/dts/omap2430.dtsi +++ b/arch/arm/boot/dts/omap2430.dtsi @@ -38,6 +38,7 @@ reg = <0x2000 0x1000>; #address-cells = <1>; #size-cells = <1>; + #pinctrl-cells = <1>; ranges = <0 0x2000 0x1000>; omap2430_pmx: pinmux@30 { @@ -46,6 +47,7 @@ reg = <0x30 0x0154>; #address-cells = <1>; #size-cells = <0>; + #pinctrl-cells = <1>; pinctrl-single,register-width = <8>; pinctrl-single,function-mask = <0x3f>; }; diff --git a/arch/arm/boot/dts/omap3.dtsi b/arch/arm/boot/dts/omap3.dtsi index 353d818ce5a6..ecf5eb584c75 100644 --- a/arch/arm/boot/dts/omap3.dtsi +++ b/arch/arm/boot/dts/omap3.dtsi @@ -106,6 +106,7 @@ reg = <0x30 0x238>; #address-cells = <1>; #size-cells = <0>; + #pinctrl-cells = <1>; #interrupt-cells = <1>; interrupt-controller; pinctrl-single,register-width = <16>; @@ -145,6 +146,7 @@ reg = <0xa00 0x5c>; #address-cells = <1>; #size-cells = <0>; + #pinctrl-cells = <1>; #interrupt-cells = <1>; interrupt-controller; pinctrl-single,register-width = <16>; diff --git a/arch/arm/boot/dts/omap34xx.dtsi b/arch/arm/boot/dts/omap34xx.dtsi index e41c52d3b113..834fdf13601f 100644 --- a/arch/arm/boot/dts/omap34xx.dtsi +++ b/arch/arm/boot/dts/omap34xx.dtsi @@ -34,6 +34,7 @@ reg = <0x480025d8 0x24>; #address-cells = <1>; #size-cells = <0>; + #pinctrl-cells = <1>; #interrupt-cells = <1>; interrupt-controller; pinctrl-single,register-width = <16>; diff --git a/arch/arm/boot/dts/omap36xx.dtsi b/arch/arm/boot/dts/omap36xx.dtsi index 718fa88407cd..d1a3e56b50ce 100644 --- a/arch/arm/boot/dts/omap36xx.dtsi +++ b/arch/arm/boot/dts/omap36xx.dtsi @@ -66,6 +66,7 @@ reg = <0x480025a0 0x5c>; #address-cells = <1>; #size-cells = <0>; + #pinctrl-cells = <1>; #interrupt-cells = <1>; interrupt-controller; pinctrl-single,register-width = <16>; diff --git a/arch/arm/boot/dts/omap4-droid4-xt894.dts b/arch/arm/boot/dts/omap4-droid4-xt894.dts new file mode 100644 index 000000000000..f3ccb4ceed9e --- /dev/null +++ b/arch/arm/boot/dts/omap4-droid4-xt894.dts @@ -0,0 +1,188 @@ +/* + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ +/dts-v1/; + +#include "omap443x.dtsi" + +/ { + model = "Motorola Droid 4 XT894"; + compatible = "motorola,droid4", "ti,omap4430", "ti,omap4"; + + chosen { + stdout-path = &uart3; + }; + + /* + * We seem to have only 1021 MB accessible, 1021 - 1022 is locked, + * then 1023 - 1024 seems to contain mbm. For SRAM, see the notes + * below about SRAM and L3_ICLK2 being unused by default, + */ + memory { + device_type = "memory"; + reg = <0x80000000 0x3fd00000>; /* 1021 MB */ + }; + + /* CPCAP really supports 1650000 to 3400000 range */ + vmmc: regulator-mmc { + compatible = "regulator-fixed"; + regulator-name = "vmmc"; + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3000000>; + regulator-always-on; + }; + + /* CPCAP really supports 3000000 to 3100000 range */ + vemmc: regulator-emmc { + compatible = "regulator-fixed"; + regulator-name = "vemmc"; + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3000000>; + regulator-always-on; + }; + + /* CPCAP really supports 1650000 to 1950000 range */ + wl12xx_vmmc: regulator-wl12xx { + compatible = "regulator-fixed"; + regulator-name = "vwl1271"; + regulator-min-microvolt = <1650000>; + regulator-max-microvolt = <1650000>; + gpio = <&gpio3 30 GPIO_ACTIVE_HIGH>; /* gpio94 */ + startup-delay-us = <70000>; + enable-active-high; + }; +}; + +/* L3_2 interconnect is unused, SRAM, GPMC and L3_ICLK2 disabled */ +&gpmc { + status = "disabled"; +}; + +&mmc1 { + vmmc-supply = <&vmmc>; + bus-width = <4>; + cd-gpios = <&gpio4 10 GPIO_ACTIVE_LOW>; /* gpio106 */ +}; + +&mmc2 { + vmmc-supply = <&vemmc>; + bus-width = <8>; + non-removable; +}; + +&mmc3 { + vmmc-supply = <&wl12xx_vmmc>; + interrupts-extended = <&wakeupgen GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH + &omap4_pmx_core 0xde>; + + non-removable; + bus-width = <4>; + cap-power-off-card; + + #address-cells = <1>; + #size-cells = <0>; + wlcore: wlcore@2 { + compatible = "ti,wl1283"; + reg = <2>; + interrupt-parent = <&gpio4>; + interrupts = <4 IRQ_TYPE_LEVEL_HIGH>; /* gpio100 */ + ref-clock-frequency = <26000000>; + tcxo-clock-frequency = <26000000>; + }; +}; + +/* L3_2 interconnect is unused, SRAM, GPMC and L3_ICLK2 disabled */ +&ocmcram { + status = "disabled"; +}; + +&omap4_pmx_core { + usb_gpio_mux_sel1: pinmux_usb_gpio_mux_sel1_pins { + /* gpio_60 */ + pinctrl-single,pins = < + OMAP4_IOPAD(0x088, PIN_OUTPUT | MUX_MODE3) + >; + }; + + usb_ulpi_pins: pinmux_usb_ulpi_pins { + pinctrl-single,pins = < + OMAP4_IOPAD(0x196, MUX_MODE7) + OMAP4_IOPAD(0x198, MUX_MODE7) + OMAP4_IOPAD(0x1b2, PIN_INPUT_PULLUP | MUX_MODE0) + OMAP4_IOPAD(0x1b4, PIN_INPUT_PULLUP | MUX_MODE0) + OMAP4_IOPAD(0x1b6, PIN_INPUT_PULLUP | MUX_MODE0) + OMAP4_IOPAD(0x1b8, PIN_INPUT_PULLUP | MUX_MODE0) + OMAP4_IOPAD(0x1ba, PIN_INPUT_PULLUP | MUX_MODE0) + OMAP4_IOPAD(0x1bc, PIN_INPUT_PULLUP | MUX_MODE0) + OMAP4_IOPAD(0x1be, PIN_INPUT_PULLUP | MUX_MODE0) + OMAP4_IOPAD(0x1c0, PIN_INPUT_PULLUP | MUX_MODE0) + OMAP4_IOPAD(0x1c2, PIN_INPUT_PULLUP | MUX_MODE0) + OMAP4_IOPAD(0x1c4, PIN_INPUT_PULLUP | MUX_MODE0) + OMAP4_IOPAD(0x1c6, PIN_INPUT_PULLUP | MUX_MODE0) + OMAP4_IOPAD(0x1c8, PIN_INPUT_PULLUP | MUX_MODE0) + >; + }; + + /* usb0_otg_dp and usb0_otg_dm */ + usb_utmi_pins: pinmux_usb_utmi_pins { + pinctrl-single,pins = < + OMAP4_IOPAD(0x196, PIN_INPUT | MUX_MODE0) + OMAP4_IOPAD(0x198, PIN_INPUT | MUX_MODE0) + OMAP4_IOPAD(0x1b2, PIN_INPUT_PULLUP | MUX_MODE7) + OMAP4_IOPAD(0x1b4, PIN_INPUT_PULLUP | MUX_MODE7) + OMAP4_IOPAD(0x1b6, PIN_INPUT_PULLUP | MUX_MODE7) + OMAP4_IOPAD(0x1b8, PIN_INPUT_PULLUP | MUX_MODE7) + OMAP4_IOPAD(0x1ba, PIN_INPUT_PULLUP | MUX_MODE7) + OMAP4_IOPAD(0x1bc, PIN_INPUT_PULLUP | MUX_MODE7) + OMAP4_IOPAD(0x1be, PIN_INPUT_PULLUP | MUX_MODE7) + OMAP4_IOPAD(0x1c0, PIN_INPUT_PULLUP | MUX_MODE7) + OMAP4_IOPAD(0x1c2, PIN_INPUT_PULLUP | MUX_MODE7) + OMAP4_IOPAD(0x1c4, PIN_INPUT_PULLUP | MUX_MODE7) + OMAP4_IOPAD(0x1c6, PIN_INPUT_PULLUP | MUX_MODE7) + OMAP4_IOPAD(0x1c8, PIN_INPUT_PULLUP | MUX_MODE7) + >; + }; + + /* uart3_tx_irtx and uart3_rx_irrx */ + uart3_pins: pinmux_uart3_pins { + pinctrl-single,pins = < + OMAP4_IOPAD(0x196, MUX_MODE7) + OMAP4_IOPAD(0x198, MUX_MODE7) + OMAP4_IOPAD(0x1b2, PIN_INPUT_PULLUP | MUX_MODE7) + OMAP4_IOPAD(0x1b4, PIN_INPUT_PULLUP | MUX_MODE7) + OMAP4_IOPAD(0x1b6, PIN_INPUT_PULLUP | MUX_MODE7) + OMAP4_IOPAD(0x1b8, PIN_INPUT_PULLUP | MUX_MODE7) + OMAP4_IOPAD(0x1ba, MUX_MODE2) + OMAP4_IOPAD(0x1bc, PIN_INPUT | MUX_MODE2) + OMAP4_IOPAD(0x1be, PIN_INPUT_PULLUP | MUX_MODE7) + OMAP4_IOPAD(0x1c0, PIN_INPUT_PULLUP | MUX_MODE7) + OMAP4_IOPAD(0x1c2, PIN_INPUT_PULLUP | MUX_MODE7) + OMAP4_IOPAD(0x1c4, PIN_INPUT_PULLUP | MUX_MODE7) + OMAP4_IOPAD(0x1c6, PIN_INPUT_PULLUP | MUX_MODE7) + OMAP4_IOPAD(0x1c8, PIN_INPUT_PULLUP | MUX_MODE7) + >; + }; +}; + +&omap4_pmx_wkup { + usb_gpio_mux_sel2: pinmux_usb_gpio_mux_sel2_pins { + /* gpio_wk0 */ + pinctrl-single,pins = < + OMAP4_IOPAD(0x040, PIN_OUTPUT_PULLDOWN | MUX_MODE3) + >; + }; +}; + +&uart3 { + interrupts-extended = <&wakeupgen GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH + &omap4_pmx_core 0x17c>; +}; + +/* Internal UTMI+ PHY used for OTG, CPCAP ULPI PHY for detection and charger */ +&usb_otg_hs { + interface-type = <1>; + mode = <3>; + power = <50>; +}; diff --git a/arch/arm/boot/dts/omap4.dtsi b/arch/arm/boot/dts/omap4.dtsi index 0ced079b7ae3..8087456b5fbe 100644 --- a/arch/arm/boot/dts/omap4.dtsi +++ b/arch/arm/boot/dts/omap4.dtsi @@ -184,6 +184,7 @@ reg = <0x40 0x0196>; #address-cells = <1>; #size-cells = <0>; + #pinctrl-cells = <1>; #interrupt-cells = <1>; interrupt-controller; pinctrl-single,register-width = <16>; @@ -256,6 +257,7 @@ reg = <0x1e040 0x0038>; #address-cells = <1>; #size-cells = <0>; + #pinctrl-cells = <1>; #interrupt-cells = <1>; interrupt-controller; pinctrl-single,register-width = <16>; diff --git a/arch/arm/boot/dts/omap5-uevm.dts b/arch/arm/boot/dts/omap5-uevm.dts index 53d31a87b44b..2fcdc516da45 100644 --- a/arch/arm/boot/dts/omap5-uevm.dts +++ b/arch/arm/boot/dts/omap5-uevm.dts @@ -27,12 +27,98 @@ default-state = "off"; }; }; + + evm_keys { + compatible = "gpio-keys"; + + pinctrl-names = "default"; + pinctrl-0 = <&evm_keys_pins>; + + #address-cells = <7>; + #size-cells = <0>; + + btn1 { + label = "BTN1"; + linux,code = <169>; + gpios = <&gpio3 19 GPIO_ACTIVE_LOW>; /* gpio3_83 */ + gpio-key,wakeup; + autorepeat; + debounce_interval = <50>; + }; + }; + + evm_leds { + compatible = "gpio-leds"; + + led1 { + label = "omap5:red:led"; + gpios = <&gpio9 17 GPIO_ACTIVE_HIGH>; + linux,default-trigger = "mmc0"; + default-state = "off"; + }; + + led2 { + label = "omap5:green:led"; + gpios = <&gpio9 18 GPIO_ACTIVE_HIGH>; + linux,default-trigger = "mmc1"; + default-state = "off"; + }; + + led3 { + label = "omap5:blue:led"; + gpios = <&gpio9 19 GPIO_ACTIVE_HIGH>; + linux,default-trigger = "mmc2"; + default-state = "off"; + }; + + led4 { + label = "omap5:green:led1"; + gpios = <&gpio9 2 GPIO_ACTIVE_HIGH>; + linux,default-trigger = "heartbeat"; + default-state = "off"; + }; + + led5 { + label = "omap5:green:led2"; + gpios = <&gpio9 3 GPIO_ACTIVE_HIGH>; + linux,default-trigger = "default-on"; + default-state = "off"; + }; + + led6 { + label = "omap5:green:led3"; + gpios = <&gpio9 4 GPIO_ACTIVE_HIGH>; + linux,default-trigger = "heartbeat"; + default-state = "off"; + }; + + led7 { + label = "omap5:green:led4"; + gpios = <&gpio9 5 GPIO_ACTIVE_HIGH>; + linux,default-trigger = "default-on"; + default-state = "off"; + }; + + led8 { + label = "omap5:green:led5"; + gpios = <&gpio9 6 GPIO_ACTIVE_HIGH>; + linux,default-trigger = "heartbeat"; + default-state = "off"; + }; + }; }; &hdmi { vdda-supply = <&ldo4_reg>; }; +&i2c1 { + eeprom@50 { + compatible = "atmel,24c02"; + reg = <0x50>; + }; +}; + &i2c5 { pinctrl-names = "default"; pinctrl-0 = <&i2c5_pins>; @@ -48,6 +134,12 @@ }; &omap5_pmx_core { + evm_keys_pins: pinmux_evm_keys_gpio_pins { + pinctrl-single,pins = < + OMAP5_IOPAD(0x0b6, PIN_INPUT | MUX_MODE6) /* gpio3_83 */ + >; + }; + i2c5_pins: pinmux_i2c5_pins { pinctrl-single,pins = < OMAP5_IOPAD(0x1c6, PIN_INPUT | MUX_MODE0) /* i2c5_scl */ diff --git a/arch/arm/boot/dts/omap5.dtsi b/arch/arm/boot/dts/omap5.dtsi index 25262118ec3d..968c67a49dbd 100644 --- a/arch/arm/boot/dts/omap5.dtsi +++ b/arch/arm/boot/dts/omap5.dtsi @@ -171,6 +171,7 @@ reg = <0x40 0x01b6>; #address-cells = <1>; #size-cells = <0>; + #pinctrl-cells = <1>; #interrupt-cells = <1>; interrupt-controller; pinctrl-single,register-width = <16>; @@ -270,6 +271,7 @@ reg = <0xc840 0x003c>; #address-cells = <1>; #size-cells = <0>; + #pinctrl-cells = <1>; #interrupt-cells = <1>; interrupt-controller; pinctrl-single,register-width = <16>; diff --git a/arch/arm/boot/dts/orion5x-lschl.dts b/arch/arm/boot/dts/orion5x-lschl.dts new file mode 100644 index 000000000000..947409252845 --- /dev/null +++ b/arch/arm/boot/dts/orion5x-lschl.dts @@ -0,0 +1,171 @@ +/* + * Device Tree file for Buffalo Linkstation LS-CHLv3 + * + * Copyright (C) 2016 Ash Hughes <ashley.hughes@blueyonder.co.uk> + * Copyright (C) 2015, 2016 + * Roger Shimizu <rogershimizu@gmail.com> + * + * This file is dual-licensed: you can use it either under the terms + * of the GPL or the X11 license, at your option. Note that this dual + * licensing only applies to this file, and not this project as a + * whole. + * + * a) This file is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of the + * License, or (at your option) any later version. + * + * This file is distributed in the hope that it will be useful + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * Or, alternatively + * + * b) Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use + * copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following + * conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED , WITHOUT WARRANTY OF ANY KIND + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + */ + +/dts-v1/; + +#include "orion5x-linkstation.dtsi" +#include "mvebu-linkstation-gpio-simple.dtsi" +#include "mvebu-linkstation-fan.dtsi" +#include <dt-bindings/gpio/gpio.h> + +/ { + model = "Buffalo Linkstation Live v3 (LS-CHL)"; + compatible = "buffalo,lschl", "marvell,orion5x-88f5182", "marvell,orion5x"; + + memory { /* 128 MB */ + device_type = "memory"; + reg = <0x00000000 0x8000000>; + }; + + gpio_keys { + func { + label = "Function Button"; + linux,code = <KEY_OPTION>; + gpios = <&gpio0 15 GPIO_ACTIVE_LOW>; + }; + + power-on-switch { + gpios = <&gpio0 8 GPIO_ACTIVE_LOW>; + }; + + power-auto-switch { + gpios = <&gpio0 10 GPIO_ACTIVE_LOW>; + }; + }; + + gpio_leds { + pinctrl-0 = <&pmx_led_power &pmx_led_alarm &pmx_led_info &pmx_led_func>; + blue-power-led { + gpios = <&gpio0 0 GPIO_ACTIVE_LOW>; + }; + + red-alarm-led { + gpios = <&gpio0 2 GPIO_ACTIVE_LOW>; + }; + + amber-info-led { + gpios = <&gpio0 3 GPIO_ACTIVE_LOW>; + }; + + func { + label = "lschl:func:blue:top"; + gpios = <&gpio0 17 GPIO_ACTIVE_LOW>; + }; + }; + + gpio_fan { + gpios = <&gpio0 14 GPIO_ACTIVE_LOW + &gpio0 16 GPIO_ACTIVE_LOW>; + + alarm-gpios = <&gpio0 6 GPIO_ACTIVE_HIGH>; + }; +}; + +&pinctrl { + pmx_led_power: pmx-leds { + marvell,pins = "mpp0"; + marvell,function = "gpio"; + }; + + pmx_power_hdd: pmx-power-hdd { + marvell,pins = "mpp1"; + marvell,function = "gpio"; + }; + + pmx_led_alarm: pmx-leds { + marvell,pins = "mpp2"; + marvell,function = "gpio"; + }; + + pmx_led_info: pmx-leds { + marvell,pins = "mpp3"; + marvell,function = "gpio"; + }; + + pmx_fan_lock: pmx-fan-lock { + marvell,pins = "mpp6"; + marvell,function = "gpio"; + }; + + pmx_power_switch: pmx-power-switch { + marvell,pins = "mpp8", "mpp10", "mpp15"; + marvell,function = "gpio"; + }; + + pmx_power_usb: pmx-power-usb { + marvell,pins = "mpp9"; + marvell,function = "gpio"; + }; + + pmx_fan_high: pmx-fan-high { + marvell,pins = "mpp14"; + marvell,function = "gpio"; + }; + + pmx_fan_low: pmx-fan-low { + marvell,pins = "mpp16"; + marvell,function = "gpio"; + }; + + pmx_led_func: pmx-leds { + marvell,pins = "mpp17"; + marvell,function = "gpio"; + }; + + pmx_sw_init: pmx-sw-init { + marvell,pins = "mpp7"; + marvell,function = "gpio"; + }; +}; + +&hdd_power { + gpios = <&gpio0 1 GPIO_ACTIVE_HIGH>; +}; + +&usb_power { + gpios = <&gpio0 9 GPIO_ACTIVE_HIGH>; +}; + diff --git a/arch/arm/boot/dts/ox820.dtsi b/arch/arm/boot/dts/ox820.dtsi new file mode 100644 index 000000000000..e40f282a023a --- /dev/null +++ b/arch/arm/boot/dts/ox820.dtsi @@ -0,0 +1,296 @@ +/* + * ox820.dtsi - Device tree file for Oxford Semiconductor OX820 SoC + * + * Copyright (C) 2016 Neil Armstrong <narmstrong@baylibre.com> + * + * Licensed under GPLv2 or later + */ + +/include/ "skeleton.dtsi" +#include <dt-bindings/interrupt-controller/arm-gic.h> + +/ { + compatible = "oxsemi,ox820"; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + enable-method = "oxsemi,ox820-smp"; + + cpu@0 { + device_type = "cpu"; + compatible = "arm,arm11mpcore"; + clocks = <&armclk>; + reg = <0>; + }; + + cpu@1 { + device_type = "cpu"; + compatible = "arm,arm11mpcore"; + clocks = <&armclk>; + reg = <1>; + }; + }; + + memory { + /* Max 512MB @ 0x60000000 */ + reg = <0x60000000 0x20000000>; + }; + + clocks { + osc: oscillator { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <25000000>; + }; + + gmacclk: gmacclk { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <125000000>; + }; + + sysclk: sysclk { + compatible = "fixed-factor-clock"; + #clock-cells = <0>; + clock-div = <4>; + clock-mult = <1>; + clocks = <&osc>; + }; + + plla: plla { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <850000000>; + }; + + armclk: armclk { + compatible = "fixed-factor-clock"; + #clock-cells = <0>; + clock-div = <2>; + clock-mult = <1>; + clocks = <&plla>; + }; + }; + + soc { + #address-cells = <1>; + #size-cells = <1>; + compatible = "simple-bus"; + ranges; + interrupt-parent = <&gic>; + + nandc: nand-controller@41000000 { + compatible = "oxsemi,ox820-nand"; + reg = <0x41000000 0x100000>; + clocks = <&stdclk 11>; + resets = <&reset 15>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + etha: ethernet@40400000 { + compatible = "oxsemi,ox820-dwmac", "snps,dwmac"; + reg = <0x40400000 0x2000>; + interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "macirq", "eth_wake_irq"; + mac-address = [000000000000]; /* Filled in by U-Boot */ + phy-mode = "rgmii"; + + clocks = <&stdclk 9>, <&gmacclk>; + clock-names = "gmac", "stmmaceth"; + resets = <&reset 6>; + + /* Regmap for sys registers */ + oxsemi,sys-ctrl = <&sys>; + + status = "disabled"; + }; + + apb-bridge@44000000 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "simple-bus"; + ranges = <0 0x44000000 0x1000000>; + + pinctrl: pinctrl { + compatible = "oxsemi,ox820-pinctrl"; + + /* Regmap for sys registers */ + oxsemi,sys-ctrl = <&sys>; + + pinctrl_uart0: uart0 { + uart0 { + pins = "gpio30", "gpio31"; + function = "fct5"; + }; + }; + + pinctrl_uart0_modem: uart0_modem { + uart0_modem_a { + pins = "gpio24", "gpio24", "gpio26", "gpio27"; + function = "fct4"; + }; + uart0_modem_b { + pins = "gpio28", "gpio29"; + function = "fct5"; + }; + }; + + pinctrl_uart1: uart1 { + uart1 { + pins = "gpio7", "gpio8"; + function = "fct4"; + }; + }; + + pinctrl_uart1_modem: uart1_modem { + uart1_modem { + pins = "gpio5", "gpio6", "gpio40", "gpio41", "gpio42", "gpio43"; + function = "fct4"; + }; + }; + + pinctrl_etha_mdio: etha_mdio { + etha_mdio { + pins = "gpio3", "gpio4"; + function = "fct1"; + }; + }; + + pinctrl_nand: nand { + nand { + pins = "gpio12", "gpio13", "gpio14", "gpio15", + "gpio16", "gpio17", "gpio18", "gpio19", + "gpio20", "gpio21", "gpio22", "gpio23", + "gpio24"; + function = "fct1"; + }; + }; + }; + + gpio0: gpio@000000 { + compatible = "oxsemi,ox820-gpio"; + reg = <0x000000 0x100000>; + interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>; + #gpio-cells = <2>; + gpio-controller; + interrupt-controller; + #interrupt-cells = <2>; + ngpios = <32>; + oxsemi,gpio-bank = <0>; + gpio-ranges = <&pinctrl 0 0 32>; + }; + + gpio1: gpio@100000 { + compatible = "oxsemi,ox820-gpio"; + reg = <0x100000 0x100000>; + interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>; + #gpio-cells = <2>; + gpio-controller; + interrupt-controller; + #interrupt-cells = <2>; + ngpios = <18>; + oxsemi,gpio-bank = <1>; + gpio-ranges = <&pinctrl 0 32 18>; + }; + + uart0: serial@200000 { + compatible = "ns16550a"; + reg = <0x200000 0x100000>; + interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>; + reg-shift = <0>; + fifo-size = <16>; + reg-io-width = <1>; + current-speed = <115200>; + no-loopback-test; + status = "disabled"; + clocks = <&sysclk>; + resets = <&reset 17>; + }; + + uart1: serial@300000 { + compatible = "ns16550a"; + reg = <0x200000 0x100000>; + interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>; + reg-shift = <0>; + fifo-size = <16>; + reg-io-width = <1>; + current-speed = <115200>; + no-loopback-test; + status = "disabled"; + clocks = <&sysclk>; + resets = <&reset 18>; + }; + + rps@400000 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "simple-bus"; + ranges = <0 0x400000 0x100000>; + + intc: interrupt-controller@0 { + compatible = "oxsemi,ox820-rps-irq", "oxsemi,ox810se-rps-irq"; + interrupt-controller; + reg = <0 0x200>; + interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>; + #interrupt-cells = <1>; + valid-mask = <0xFFFFFFFF>; + clear-mask = <0>; + }; + + timer0: timer@200 { + compatible = "oxsemi,ox820-rps-timer"; + reg = <0x200 0x40>; + clocks = <&sysclk>; + interrupt-parent = <&intc>; + interrupts = <4>; + }; + }; + + sys: sys-ctrl@e00000 { + compatible = "oxsemi,ox820-sys-ctrl", "syscon", "simple-mfd"; + reg = <0xe00000 0x200000>; + + reset: reset-controller { + compatible = "oxsemi,ox820-reset", "oxsemi,ox810se-reset"; + #reset-cells = <1>; + }; + + stdclk: stdclk { + compatible = "oxsemi,ox820-stdclk", "oxsemi,ox810se-stdclk"; + #clock-cells = <1>; + }; + }; + }; + + apb-bridge@47000000 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "simple-bus"; + ranges = <0 0x47000000 0x1000000>; + + scu: scu@0 { + compatible = "arm,arm11mp-scu"; + reg = <0x0 0x100>; + }; + + local-timer@600 { + compatible = "arm,arm11mp-twd-timer"; + reg = <0x600 0x20>; + interrupts = <GIC_PPI 13 (GIC_CPU_MASK_RAW(3)|IRQ_TYPE_LEVEL_HIGH)>; + clocks = <&armclk>; + }; + + gic: gic@1000 { + compatible = "arm,arm11mp-gic"; + interrupt-controller; + #interrupt-cells = <3>; + reg = <0x1000 0x1000>, + <0x100 0x500>; + }; + }; + }; +}; diff --git a/arch/arm/boot/dts/pxa25x.dtsi b/arch/arm/boot/dts/pxa25x.dtsi new file mode 100644 index 000000000000..f9f4726396a0 --- /dev/null +++ b/arch/arm/boot/dts/pxa25x.dtsi @@ -0,0 +1,117 @@ +/* + * Copyright (C) 2016 Robert Jarzmik <robert.jarzmik@free.fr> + * + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ +#include "pxa2xx.dtsi" +#include "dt-bindings/clock/pxa-clock.h" + +/ { + model = "Marvell PXA25x family SoC"; + compatible = "marvell,pxa250"; + + clocks { + /* + * The muxing of external clocks/internal dividers for osc* clock + * sources has been hidden under the carpet by now. + */ + #address-cells = <1>; + #size-cells = <1>; + ranges; + + clks: pxa2xx_clks@41300004 { + compatible = "marvell,pxa250-core-clocks"; + #clock-cells = <1>; + status = "okay"; + }; + + /* timer oscillator */ + clktimer: oscillator { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <3686400>; + clock-output-names = "ostimer"; + }; + }; + + pxabus { + pdma: dma-controller@40000000 { + compatible = "marvell,pdma-1.0"; + reg = <0x40000000 0x10000>; + interrupts = <25>; + #dma-channels = <16>; + #dma-cells = <2>; + #dma-requests = <40>; + status = "okay"; + }; + + pxairq: interrupt-controller@40d00000 { + marvell,intc-priority; + marvell,intc-nr-irqs = <32>; + }; + + pinctrl: pinctrl@40e00000 { + reg = <0x40e00054 0x20 0x40e0000c 0xc 0x40e0010c 4 + 0x40f00020 0x10>; + compatible = "marvell,pxa25x-pinctrl"; + }; + + gpio: gpio@40e00000 { + compatible = "intel,pxa25x-gpio"; + gpio-ranges = <&pinctrl 0 0 84>; + clocks = <&clks CLK_NONE>; + }; + + pwm0: pwm@40b00000 { + compatible = "marvell,pxa250-pwm"; + reg = <0x40b00000 0x10>; + #pwm-cells = <1>; + clocks = <&clks CLK_PWM0>; + }; + + pwm1: pwm@40b00010 { + compatible = "marvell,pxa250-pwm"; + reg = <0x40b00010 0x10>; + #pwm-cells = <1>; + clocks = <&clks CLK_PWM1>; + }; + }; + + timer@40a00000 { + compatible = "marvell,pxa-timer"; + reg = <0x40a00000 0x20>; + interrupts = <26>; + clocks = <&clktimer>; + status = "okay"; + }; + + pxa250_opp_table: opp_table0 { + compatible = "operating-points-v2"; + + opp@99532800 { + opp-hz = /bits/ 64 <99532800>; + opp-microvolt = <1000000 950000 1650000>; + clock-latency-ns = <20>; + }; + opp@199065600 { + opp-hz = /bits/ 64 <199065600>; + opp-microvolt = <1000000 950000 1650000>; + clock-latency-ns = <20>; + }; + opp@298598400 { + opp-hz = /bits/ 64 <298598400>; + opp-microvolt = <1100000 1045000 1650000>; + clock-latency-ns = <20>; + }; + opp@398131200 { + opp-hz = /bits/ 64 <398131200>; + opp-microvolt = <1300000 1235000 1650000>; + clock-latency-ns = <20>; + }; + }; +}; diff --git a/arch/arm/boot/dts/pxa27x.dtsi b/arch/arm/boot/dts/pxa27x.dtsi index 9e73dc6b3ed3..e0fab48ba6fa 100644 --- a/arch/arm/boot/dts/pxa27x.dtsi +++ b/arch/arm/boot/dts/pxa27x.dtsi @@ -137,4 +137,44 @@ clocks = <&clks CLK_OSTIMER>; status = "okay"; }; + + pxa270_opp_table: opp_table0 { + compatible = "operating-points-v2"; + + opp@104000000 { + opp-hz = /bits/ 64 <104000000>; + opp-microvolt = <900000 900000 1705000>; + clock-latency-ns = <20>; + }; + opp@156000000 { + opp-hz = /bits/ 64 <156000000>; + opp-microvolt = <1000000 1000000 1705000>; + clock-latency-ns = <20>; + }; + opp@208000000 { + opp-hz = /bits/ 64 <208000000>; + opp-microvolt = <1180000 1180000 1705000>; + clock-latency-ns = <20>; + }; + opp@312000000 { + opp-hz = /bits/ 64 <312000000>; + opp-microvolt = <1250000 1250000 1705000>; + clock-latency-ns = <20>; + }; + opp@416000000 { + opp-hz = /bits/ 64 <416000000>; + opp-microvolt = <1350000 1350000 1705000>; + clock-latency-ns = <20>; + }; + opp@520000000 { + opp-hz = /bits/ 64 <520000000>; + opp-microvolt = <1450000 1450000 1705000>; + clock-latency-ns = <20>; + }; + opp@624000000 { + opp-hz = /bits/ 64 <624000000>; + opp-microvolt = <1550000 1550000 1705000>; + clock-latency-ns = <20>; + }; + }; }; diff --git a/arch/arm/boot/dts/pxa2xx.dtsi b/arch/arm/boot/dts/pxa2xx.dtsi index 3ff077ca4400..e4ebcde17837 100644 --- a/arch/arm/boot/dts/pxa2xx.dtsi +++ b/arch/arm/boot/dts/pxa2xx.dtsi @@ -54,8 +54,8 @@ reg = <0x40e00000 0x10000>; gpio-controller; #gpio-cells = <0x2>; - interrupts = <10>; - interrupt-names = "gpio_mux"; + interrupts = <8>, <9>, <10>; + interrupt-names = "gpio0", "gpio1", "gpio_mux"; interrupt-controller; #interrupt-cells = <0x2>; ranges; diff --git a/arch/arm/boot/dts/pxa3xx.dtsi b/arch/arm/boot/dts/pxa3xx.dtsi index 9d6f3aacedb7..7a0cc4ea819a 100644 --- a/arch/arm/boot/dts/pxa3xx.dtsi +++ b/arch/arm/boot/dts/pxa3xx.dtsi @@ -138,6 +138,7 @@ reg = <0x40e10000 0xffff>; #address-cells = <1>; #size-cells = <0>; + #pinctrl-cells = <1>; pinctrl-single,register-width = <32>; pinctrl-single,function-mask = <0x7>; }; diff --git a/arch/arm/boot/dts/qcom-apq8060-dragonboard.dts b/arch/arm/boot/dts/qcom-apq8060-dragonboard.dts index 6c0038398ef2..4b8872cc8bf9 100644 --- a/arch/arm/boot/dts/qcom-apq8060-dragonboard.dts +++ b/arch/arm/boot/dts/qcom-apq8060-dragonboard.dts @@ -51,6 +51,29 @@ regulator-boot-on; }; + /* GPIO controlled ethernet power regulator */ + dragon_veth: xc622a331mrg { + compatible = "regulator-fixed"; + regulator-name = "XC6222A331MR-G"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + vin-supply = <&vph>; + gpio = <&pm8058_gpio 40 GPIO_ACTIVE_HIGH>; + enable-active-high; + pinctrl-names = "default"; + pinctrl-0 = <&dragon_veth_gpios>; + regulator-always-on; + }; + + /* VDDvario fixed regulator */ + dragon_vario: nds332p { + compatible = "regulator-fixed"; + regulator-name = "NDS332P"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + vin-supply = <&pm8058_s3>; + }; + /* This is a levelshifter for SDCC5 */ dragon_vio_txb: txb0104rgyr { compatible = "regulator-fixed"; @@ -167,6 +190,36 @@ bias-pull-up; }; }; + + dragon_ebi2_pins: ebi2 { + /* + * Pins used by EBI2 on the Dragonboard, actually only + * CS2 is used by a real peripheral. CS0 is just + * routed to a test point. + */ + mux0 { + pins = + /* "gpio39", CS1A_N this is not good to mux */ + "gpio40", /* CS2A_N */ + "gpio134"; /* CS0_N testpoint TP29 */ + function = "ebi2cs"; + }; + mux1 { + pins = + /* EBI2_ADDR_7 downto EBI2_ADDR_0 address bus */ + "gpio123", "gpio124", "gpio125", "gpio126", + "gpio127", "gpio128", "gpio129", "gpio130", + /* EBI2_DATA_15 downto EBI2_DATA_0 data bus */ + "gpio135", "gpio136", "gpio137", "gpio138", + "gpio139", "gpio140", "gpio141", "gpio142", + "gpio143", "gpio144", "gpio145", "gpio146", + "gpio147", "gpio148", "gpio149", "gpio150", + "gpio151", /* EBI2_OE_N */ + "gpio153", /* EBI2_ADV */ + "gpio157"; /* EBI2_WE_N */ + function = "ebi2"; + }; + }; }; qcom,ssbi@500000 { @@ -201,6 +254,15 @@ }; gpio@150 { + dragon_ethernet_gpios: ethernet-gpios { + pinconf { + pins = "gpio7"; + function = "normal"; + input-enable; + bias-disable; + power-source = <PM8058_GPIO_S3>; + }; + }; dragon_bmp085_gpios: bmp085-gpios { pinconf { pins = "gpio16"; @@ -238,6 +300,14 @@ power-source = <PM8058_GPIO_S3>; }; }; + dragon_veth_gpios: veth-gpios { + pinconf { + pins = "gpio40"; + function = "normal"; + bias-disable; + drive-push-pull; + }; + }; }; led@48 { @@ -322,6 +392,55 @@ }; }; + external-bus@1a100000 { + /* The EBI2 will instantiate first, then populate its children */ + status = "ok"; + pinctrl-names = "default"; + pinctrl-0 = <&dragon_ebi2_pins>; + + /* + * An on-board SMSC LAN9221 chip for "debug ethernet", + * which is actually just an ordinary ethernet on the + * EBI2. This has a 25MHz chrystal next to it, so no + * clocking is needed. + */ + ethernet-ebi2@2,0 { + compatible = "smsc,lan9221", "smsc,lan9115"; + reg = <2 0x0 0x100>; + /* + * GPIO7 has interrupt 198 on the PM8058 + * The second interrupt is the PME interrupt + * for network wakeup, connected to the TLMM. + */ + interrupts-extended = <&pmicintc 198 IRQ_TYPE_EDGE_FALLING>, + <&tlmm 29 IRQ_TYPE_EDGE_RISING>; + reset-gpios = <&tlmm 30 GPIO_ACTIVE_LOW>; + vdd33a-supply = <&dragon_veth>; + vddvario-supply = <&dragon_vario>; + pinctrl-names = "default"; + pinctrl-0 = <&dragon_ethernet_gpios>; + phy-mode = "mii"; + reg-io-width = <2>; + smsc,force-external-phy; + /* IRQ on edge falling = active low */ + smsc,irq-active-low; + smsc,irq-push-pull; + + /* + * SLOW chipselect config + * Delay 9 cycles (140ns@64MHz) between SMSC + * LAN9221 Ethernet controller reads and writes + * on CS2. + */ + qcom,xmem-recovery-cycles = <0>; + qcom,xmem-write-hold-cycles = <3>; + qcom,xmem-write-delta-cycles = <31>; + qcom,xmem-read-delta-cycles = <28>; + qcom,xmem-write-wait-cycles = <9>; + qcom,xmem-read-wait-cycles = <9>; + }; + }; + rpm@104000 { /* * Set up of the PMIC RPM regulators for this board diff --git a/arch/arm/boot/dts/qcom-apq8064-asus-nexus7-flo.dts b/arch/arm/boot/dts/qcom-apq8064-asus-nexus7-flo.dts index b72e09506448..e39440a86739 100644 --- a/arch/arm/boot/dts/qcom-apq8064-asus-nexus7-flo.dts +++ b/arch/arm/boot/dts/qcom-apq8064-asus-nexus7-flo.dts @@ -15,6 +15,20 @@ stdout-path = "serial0:115200n8"; }; + reserved-memory { + #address-cells = <1>; + #size-cells = <1>; + ranges; + + ramoops@88d00000{ + compatible = "ramoops"; + reg = <0x88d00000 0x100000>; + record-size = <0x00020000>; + console-size = <0x00020000>; + ftrace-size = <0x00020000>; + }; + }; + ext_3p3v: regulator-fixed@1 { compatible = "regulator-fixed"; regulator-min-microvolt = <3300000>; @@ -99,6 +113,7 @@ l2 { regulator-min-microvolt = <1200000>; regulator-max-microvolt = <1200000>; + regulator-always-on; }; /* msm_otg-HSUSB_3p3 */ @@ -133,13 +148,14 @@ regulator-min-microvolt = <3000000>; regulator-max-microvolt = <3000000>; bias-pull-down; + regulator-always-on; }; /* pwm_power for backlight */ l17 { regulator-min-microvolt = <3000000>; - regulator-max-microvolt = <3600000>; - bias-pull-down; + regulator-max-microvolt = <3000000>; + regulator-always-on; }; /* camera, qdsp6 */ @@ -184,6 +200,63 @@ }; }; + mdp@5100000 { + status = "okay"; + ports { + port@1 { + mdp_dsi1_out: endpoint { + remote-endpoint = <&dsi0_in>; + }; + }; + }; + }; + + dsi0: mdss_dsi@4700000 { + status = "okay"; + vdda-supply = <&pm8921_l2>;/*VDD_MIPI1 to 4*/ + vdd-supply = <&pm8921_l8>; + vddio-supply = <&pm8921_lvs7>; + avdd-supply = <&pm8921_l11>; + vcss-supply = <&ext_3p3v>; + + panel@0 { + reg = <0>; + compatible = "jdi,lt070me05000"; + + vddp-supply = <&pm8921_l17>; + iovcc-supply = <&pm8921_lvs7>; + + enable-gpios = <&pm8921_gpio 36 GPIO_ACTIVE_HIGH>; + reset-gpios = <&tlmm_pinmux 54 GPIO_ACTIVE_LOW>; + dcdc-en-gpios = <&pm8921_gpio 23 GPIO_ACTIVE_HIGH>; + + port { + panel_in: endpoint { + remote-endpoint = <&dsi0_out>; + }; + }; + }; + ports { + port@0 { + dsi0_in: endpoint { + remote-endpoint = <&mdp_dsi1_out>; + }; + }; + + port@1 { + dsi0_out: endpoint { + remote-endpoint = <&panel_in>; + data-lanes = <0 1 2 3>; + }; + }; + }; + }; + + dsi-phy@4700200 { + status = "okay"; + vddio-supply = <&pm8921_lvs7>;/*VDD_PLL2_1 to 7*/ + }; + gsbi@16200000 { status = "okay"; qcom,mode = <GSBI_PROT_I2C>; diff --git a/arch/arm/boot/dts/qcom-apq8064-ifc6410.dts b/arch/arm/boot/dts/qcom-apq8064-ifc6410.dts index 2eeb0904eaa7..3d37cab3b9a9 100644 --- a/arch/arm/boot/dts/qcom-apq8064-ifc6410.dts +++ b/arch/arm/boot/dts/qcom-apq8064-ifc6410.dts @@ -43,6 +43,17 @@ }; }; + hdmi-out { + compatible = "hdmi-connector"; + type = "d"; + + port { + hdmi_con: endpoint { + remote-endpoint = <&hdmi_out>; + }; + }; + }; + soc { pinctrl@800000 { card_detect: card_detect { @@ -64,6 +75,25 @@ bias-disable; }; }; + + hdmi_pinctrl: hdmi-pinctrl { + mux { + pins = "gpio70", "gpio71", "gpio72"; + function = "hdmi"; + }; + + pinconf_ddc { + pins = "gpio70", "gpio71"; + bias-pull-up; + drive-strength = <2>; + }; + + pinconf_hpd { + pins = "gpio72"; + bias-pull-down; + drive-strength = <16>; + }; + }; }; rpm@108000 { @@ -329,5 +359,49 @@ mmc-pwrseq = <&sdcc4_pwrseq>; }; }; + + hdmi-tx@4a00000 { + status = "okay"; + + core-vdda-supply = <&pm8921_hdmi_switch>; + hdmi-mux-supply = <&ext_3p3v>; + + hpd-gpios = <&tlmm_pinmux 72 GPIO_ACTIVE_HIGH>; + + pinctrl-names = "default"; + pinctrl-0 = <&hdmi_pinctrl>; + + ports { + port@0 { + endpoint { + remote-endpoint = <&mdp_dtv_out>; + }; + }; + + port@1 { + endpoint { + remote-endpoint = <&hdmi_con>; + }; + }; + }; + }; + + hdmi-phy@4a00400 { + status = "okay"; + + core-vdda-supply = <&pm8921_hdmi_switch>; + }; + + mdp@5100000 { + status = "okay"; + + ports { + port@3 { + endpoint { + remote-endpoint = <&hdmi_in>; + }; + }; + }; + }; }; }; diff --git a/arch/arm/boot/dts/qcom-apq8064.dtsi b/arch/arm/boot/dts/qcom-apq8064.dtsi index 1dbe697b2e90..268bd470c865 100644 --- a/arch/arm/boot/dts/qcom-apq8064.dtsi +++ b/arch/arm/boot/dts/qcom-apq8064.dtsi @@ -1060,6 +1060,231 @@ reg = <0x1a400000 0x100>; }; + gpu: adreno-3xx@4300000 { + compatible = "qcom,adreno-3xx"; + reg = <0x04300000 0x20000>; + reg-names = "kgsl_3d0_reg_memory"; + interrupts = <GIC_SPI 80 0>; + interrupt-names = "kgsl_3d0_irq"; + clock-names = + "core_clk", + "iface_clk", + "mem_clk", + "mem_iface_clk"; + clocks = + <&mmcc GFX3D_CLK>, + <&mmcc GFX3D_AHB_CLK>, + <&mmcc GFX3D_AXI_CLK>, + <&mmcc MMSS_IMEM_AHB_CLK>; + qcom,chipid = <0x03020002>; + + iommus = <&gfx3d 0 + &gfx3d 1 + &gfx3d 2 + &gfx3d 3 + &gfx3d 4 + &gfx3d 5 + &gfx3d 6 + &gfx3d 7 + &gfx3d 8 + &gfx3d 9 + &gfx3d 10 + &gfx3d 11 + &gfx3d 12 + &gfx3d 13 + &gfx3d 14 + &gfx3d 15 + &gfx3d 16 + &gfx3d 17 + &gfx3d 18 + &gfx3d 19 + &gfx3d 20 + &gfx3d 21 + &gfx3d 22 + &gfx3d 23 + &gfx3d 24 + &gfx3d 25 + &gfx3d 26 + &gfx3d 27 + &gfx3d 28 + &gfx3d 29 + &gfx3d 30 + &gfx3d 31 + &gfx3d1 0 + &gfx3d1 1 + &gfx3d1 2 + &gfx3d1 3 + &gfx3d1 4 + &gfx3d1 5 + &gfx3d1 6 + &gfx3d1 7 + &gfx3d1 8 + &gfx3d1 9 + &gfx3d1 10 + &gfx3d1 11 + &gfx3d1 12 + &gfx3d1 13 + &gfx3d1 14 + &gfx3d1 15 + &gfx3d1 16 + &gfx3d1 17 + &gfx3d1 18 + &gfx3d1 19 + &gfx3d1 20 + &gfx3d1 21 + &gfx3d1 22 + &gfx3d1 23 + &gfx3d1 24 + &gfx3d1 25 + &gfx3d1 26 + &gfx3d1 27 + &gfx3d1 28 + &gfx3d1 29 + &gfx3d1 30 + &gfx3d1 31>; + + qcom,gpu-pwrlevels { + compatible = "qcom,gpu-pwrlevels"; + qcom,gpu-pwrlevel@0 { + qcom,gpu-freq = <450000000>; + }; + qcom,gpu-pwrlevel@1 { + qcom,gpu-freq = <27000000>; + }; + }; + }; + + mmss_sfpb: syscon@5700000 { + compatible = "syscon"; + reg = <0x5700000 0x70>; + }; + + dsi0: mdss_dsi@4700000 { + compatible = "qcom,mdss-dsi-ctrl"; + label = "MDSS DSI CTRL->0"; + #address-cells = <1>; + #size-cells = <0>; + interrupts = <GIC_SPI 82 0>; + reg = <0x04700000 0x200>; + reg-names = "dsi_ctrl"; + + clocks = <&mmcc DSI_M_AHB_CLK>, + <&mmcc DSI_S_AHB_CLK>, + <&mmcc AMP_AHB_CLK>, + <&mmcc DSI_CLK>, + <&mmcc DSI1_BYTE_CLK>, + <&mmcc DSI_PIXEL_CLK>, + <&mmcc DSI1_ESC_CLK>; + clock-names = "iface_clk", "bus_clk", "core_mmss_clk", + "src_clk", "byte_clk", "pixel_clk", + "core_clk"; + + assigned-clocks = <&mmcc DSI1_BYTE_SRC>, + <&mmcc DSI1_ESC_SRC>, + <&mmcc DSI_SRC>, + <&mmcc DSI_PIXEL_SRC>; + assigned-clock-parents = <&dsi0_phy 0>, + <&dsi0_phy 0>, + <&dsi0_phy 1>, + <&dsi0_phy 1>; + syscon-sfpb = <&mmss_sfpb>; + phys = <&dsi0_phy>; + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + dsi0_in: endpoint { + }; + }; + + port@1 { + reg = <1>; + dsi0_out: endpoint { + }; + }; + }; + }; + + + dsi0_phy: dsi-phy@4700200 { + compatible = "qcom,dsi-phy-28nm-8960"; + #clock-cells = <1>; + + reg = <0x04700200 0x100>, + <0x04700300 0x200>, + <0x04700500 0x5c>; + reg-names = "dsi_pll", "dsi_phy", "dsi_phy_regulator"; + clock-names = "iface_clk"; + clocks = <&mmcc DSI_M_AHB_CLK>; + }; + + + mdp_port0: iommu@7500000 { + compatible = "qcom,apq8064-iommu"; + #iommu-cells = <1>; + clock-names = + "smmu_pclk", + "iommu_clk"; + clocks = + <&mmcc SMMU_AHB_CLK>, + <&mmcc MDP_AXI_CLK>; + reg = <0x07500000 0x100000>; + interrupts = + <GIC_SPI 63 0>, + <GIC_SPI 64 0>; + qcom,ncb = <2>; + }; + + mdp_port1: iommu@7600000 { + compatible = "qcom,apq8064-iommu"; + #iommu-cells = <1>; + clock-names = + "smmu_pclk", + "iommu_clk"; + clocks = + <&mmcc SMMU_AHB_CLK>, + <&mmcc MDP_AXI_CLK>; + reg = <0x07600000 0x100000>; + interrupts = + <GIC_SPI 61 0>, + <GIC_SPI 62 0>; + qcom,ncb = <2>; + }; + + gfx3d: iommu@7c00000 { + compatible = "qcom,apq8064-iommu"; + #iommu-cells = <1>; + clock-names = + "smmu_pclk", + "iommu_clk"; + clocks = + <&mmcc SMMU_AHB_CLK>, + <&mmcc GFX3D_AXI_CLK>; + reg = <0x07c00000 0x100000>; + interrupts = + <GIC_SPI 69 0>, + <GIC_SPI 70 0>; + qcom,ncb = <3>; + }; + + gfx3d1: iommu@7d00000 { + compatible = "qcom,apq8064-iommu"; + #iommu-cells = <1>; + clock-names = + "smmu_pclk", + "iommu_clk"; + clocks = + <&mmcc SMMU_AHB_CLK>, + <&mmcc GFX3D_AXI_CLK>; + reg = <0x07d00000 0x100000>; + interrupts = + <GIC_SPI 210 0>, + <GIC_SPI 211 0>; + qcom,ncb = <3>; + }; + pcie: pci@1b500000 { compatible = "qcom,pcie-apq8064", "snps,dw-pcie"; reg = <0x1b500000 0x1000 @@ -1095,6 +1320,102 @@ reset-names = "axi", "ahb", "por", "pci", "phy"; status = "disabled"; }; + + hdmi: hdmi-tx@4a00000 { + compatible = "qcom,hdmi-tx-8960"; + reg = <0x04a00000 0x2f0>; + reg-names = "core_physical"; + interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&mmcc HDMI_APP_CLK>, + <&mmcc HDMI_M_AHB_CLK>, + <&mmcc HDMI_S_AHB_CLK>; + clock-names = "core_clk", + "master_iface_clk", + "slave_iface_clk"; + + phys = <&hdmi_phy>; + phy-names = "hdmi-phy"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + hdmi_in: endpoint { + }; + }; + + port@1 { + reg = <1>; + hdmi_out: endpoint { + }; + }; + }; + }; + + hdmi_phy: hdmi-phy@4a00400 { + compatible = "qcom,hdmi-phy-8960"; + reg = <0x4a00400 0x60>, + <0x4a00500 0x100>; + reg-names = "hdmi_phy", + "hdmi_pll"; + + clocks = <&mmcc HDMI_S_AHB_CLK>; + clock-names = "slave_iface_clk"; + }; + + mdp: mdp@5100000 { + compatible = "qcom,mdp4"; + reg = <0x05100000 0xf0000>; + interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&mmcc MDP_CLK>, + <&mmcc MDP_AHB_CLK>, + <&mmcc MDP_AXI_CLK>, + <&mmcc MDP_LUT_CLK>, + <&mmcc HDMI_TV_CLK>, + <&mmcc MDP_TV_CLK>; + clock-names = "core_clk", + "iface_clk", + "bus_clk", + "lut_clk", + "hdmi_clk", + "tv_clk"; + + iommus = <&mdp_port0 0 + &mdp_port0 2 + &mdp_port1 0 + &mdp_port1 2>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + mdp_lvds_out: endpoint { + }; + }; + + port@1 { + reg = <1>; + mdp_dsi1_out: endpoint { + }; + }; + + port@2 { + reg = <2>; + mdp_dsi2_out: endpoint { + }; + }; + + port@3 { + reg = <3>; + mdp_dtv_out: endpoint { + }; + }; + }; + }; }; }; #include "qcom-apq8064-pins.dtsi" diff --git a/arch/arm/boot/dts/qcom-mdm9615-wp8548-mangoh-green.dts b/arch/arm/boot/dts/qcom-mdm9615-wp8548-mangoh-green.dts new file mode 100644 index 000000000000..26160c324802 --- /dev/null +++ b/arch/arm/boot/dts/qcom-mdm9615-wp8548-mangoh-green.dts @@ -0,0 +1,281 @@ +/* + * Device Tree Source for mangOH Green Board with WP8548 Module + * + * Copyright (C) 2016 BayLibre, SAS. + * Author : Neil Armstrong <narmstrong@baylibre.com> + * + * This file is dual-licensed: you can use it either under the terms + * of the GPL or the X11 license, at your option. Note that this dual + * licensing only applies to this file, and not this project as a + * whole. + * + * a) This file is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of the + * License, or (at your option) any later version. + * + * This file is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * Or, alternatively, + * + * b) Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, + * copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following + * conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + */ + +#include <dt-bindings/input/input.h> + +#include "qcom-mdm9615-wp8548.dtsi" +#include <dt-bindings/interrupt-controller/irq.h> +#include <dt-bindings/gpio/gpio.h> + +/ { + model = "MangOH Green with WP8548 Module"; + compatible = "swir,mangoh-green-wp8548", "swir,wp8548", "qcom,mdm9615"; + + aliases { + spi0 = &gsbi3_spi; + serial0 = &gsbi4_serial; + serial1 = &gsbi5_serial; + i2c0 = &gsbi5_i2c; + mmc0 = &sdcc1; + }; + + chosen { + stdout-path = "serial1:115200n8"; + }; +}; + +&msmgpio { + /* MangOH GPIO Mapping : + * - 2 : GPIOEXP_INT2 + * - 7 : IOT1_GPIO2 + * - 8 : IOT0_GPIO4 + * - 13: IOT0_GPIO3 + * - 21: IOT1_GPIO4 + * - 22: IOT2_GPIO1 + * - 23: IOT2_GPIO2 + * - 24: IOT2_GPIO3 + * - 25: IOT1_GPIO1 + * - 32: IOT1_GPIO3 + * - 33: IOT0_GPIO2 + * - 42: IOT0_GPIO1 and SD Card Detect + */ + + gpioext1_pins: gpioext1_pins { + pins { + pins = "gpio2"; + function = "gpio"; + input-enable; + bias-disable; + }; + }; + + sdc_cd_pins: sdc_cd_pins { + pins { + pins = "gpio42"; + function = "gpio"; + drive-strength = <2>; + bias-pull-up; + }; + }; +}; + +&gsbi3_spi { + spi@0 { + compatible = "swir,mangoh-iotport-spi", "spidev"; + spi-max-frequency = <24000000>; + reg = <0>; + }; +}; + +&gsbi5_i2c { + mux@71 { + compatible = "nxp,pca9548"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x71>; + + i2c_iot0: i2c@0 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0>; + }; + + i2c_iot1: i2c@1 { + #address-cells = <1>; + #size-cells = <0>; + reg = <1>; + }; + + i2c_iot2: i2c@2 { + #address-cells = <1>; + #size-cells = <0>; + reg = <2>; + }; + + i2c@3 { + #address-cells = <1>; + #size-cells = <0>; + reg = <3>; + + usbhub: hub@8 { + compatible = "smsc,usb3503a"; + reg = <0x8>; + connect-gpios = <&gpioext2 1 GPIO_ACTIVE_HIGH>; + intn-gpios = <&gpioext2 0 GPIO_ACTIVE_LOW>; + initial-mode = <1>; + }; + }; + + i2c@4 { + #address-cells = <1>; + #size-cells = <0>; + reg = <4>; + + gpioext0: gpio@3e { + /* GPIO Expander 0 Mapping : + * - 0: ARDUINO_RESET_Level shift + * - 1: BattChrgr_PG_N + * - 2: BattGauge_GPIO + * - 3: LED_ON (out active high) + * - 4: ATmega_reset_GPIO + * - 5: X + * - 6: PCM_ANALOG_SELECT (out active high) + * - 7: X + * - 8: Board_rev_res1 (in) + * - 9: Board_rev_res2 (in) + * - 10: UART_EXP1_ENn (out active low / pull-down) + * - 11: UART_EXP1_IN (out pull-down) + * - 12: UART_EXP2_IN (out pull-down) + * - 13: SDIO_SEL (out pull-down) + * - 14: SPI_EXP1_ENn (out active low / pull-down) + * - 15: SPI_EXP1_IN (out pull-down) + */ + #gpio-cells = <2>; + #interrupt-cells = <2>; + compatible = "semtech,sx1509q"; + reg = <0x3e>; + interrupt-parent = <&gpioext1>; + interrupts = <0 IRQ_TYPE_EDGE_FALLING>; + + probe-reset; + + gpio-controller; + interrupt-controller; + }; + }; + + i2c@5 { + #address-cells = <1>; + #size-cells = <0>; + reg = <5>; + + gpioext1: gpio@3f { + /* GPIO Expander 1 Mapping : + * - 0: GPIOEXP_INT1 + * - 1: Battery detect + * - 2: GPIO_SCF3_RESET + * - 3: LED_CARD_DETECT_IOT0 (in) + * - 4: LED_CARD_DETECT_IOT1 (in) + * - 5: LED_CARD_DETECT_IOT2 (in) + * - 6: UIM2_PWM_SELECT + * - 7: UIM2_M2_S_SELECT + * - 8: TP900 + * - 9: SENSOR_INT1 (in) + * - 10: SENSOR_INT2 (in) + * - 11: CARD_DETECT_IOT0 (in pull-up) + * - 12: CARD_DETECT_IOT2 (in pull-up) + * - 13: CARD_DETECT_IOT1 (in pull-up) + * - 14: GPIOEXP_INT3 (in active low / pull-up) + * - 15: BattChrgr_INT_N + */ + pinctrl-0 = <&gpioext1_pins>; + pinctrl-names = "default"; + + #gpio-cells = <2>; + #interrupt-cells = <2>; + compatible = "semtech,sx1509q"; + reg = <0x3f>; + interrupt-parent = <&msmgpio>; + interrupts = <0 IRQ_TYPE_EDGE_FALLING>; + + probe-reset; + + gpio-controller; + interrupt-controller; + }; + }; + + i2c@6 { + #address-cells = <1>; + #size-cells = <0>; + reg = <6>; + + gpioext2: gpio@70 { + /* GPIO Expander 2 Mapping : + * - 0: USB_HUB_INTn + * - 1: HUB_CONNECT + * - 2: GPIO_IOT2_RESET (out active low / pull-up) + * - 3: GPIO_IOT1_RESET (out active low / pull-up) + * - 4: GPIO_IOT0_RESET (out active low / pull-up) + * - 5: TP901 + * - 6: TP902 + * - 7: TP903 + * - 8: UART_EXP2_ENn (out active low / pull-down) + * - 9: PCM_EXP1_ENn (out active low) + * - 10: PCM_EXP1_SEL (out) + * - 11: ARD_FTDI + * - 12: TP904 + * - 13: TP905 + * - 14: TP906 + * - 15: RS232_Enable (out active high / pull-up) + */ + #gpio-cells = <2>; + #interrupt-cells = <2>; + compatible = "semtech,sx1509q"; + reg = <0x70>; + interrupt-parent = <&gpioext1>; + interrupts = <14 IRQ_TYPE_EDGE_FALLING>; + + probe-reset; + + gpio-controller; + interrupt-controller; + }; + }; + + i2c@7 { + #address-cells = <1>; + #size-cells = <0>; + reg = <7>; + }; + }; +}; + +&sdcc1 { + pinctrl-0 = <&sdc_cd_pins>; + pinctrl-names = "default"; + disable-wp; + cd-gpios = <&msmgpio 42 GPIO_ACTIVE_LOW>; /* Active low CD */ +}; diff --git a/arch/arm/boot/dts/qcom-mdm9615-wp8548.dtsi b/arch/arm/boot/dts/qcom-mdm9615-wp8548.dtsi new file mode 100644 index 000000000000..7869898e392d --- /dev/null +++ b/arch/arm/boot/dts/qcom-mdm9615-wp8548.dtsi @@ -0,0 +1,170 @@ +/* + * Device Tree Source for Sierra Wireless WP8548 Module + * + * Copyright (C) 2016 BayLibre, SAS. + * Author : Neil Armstrong <narmstrong@baylibre.com> + * + * This file is dual-licensed: you can use it either under the terms + * of the GPL or the X11 license, at your option. Note that this dual + * licensing only applies to this file, and not this project as a + * whole. + * + * a) This file is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of the + * License, or (at your option) any later version. + * + * This file is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * Or, alternatively, + * + * b) Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, + * copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following + * conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + */ + +#include "qcom-mdm9615.dtsi" + +/ { + model = "Sierra Wireless WP8548 Module"; + compatible = "swir,wp8548", "qcom,mdm9615"; + + memory { + reg = <0x48000000 0x7F00000>; + }; +}; + +&msmgpio { + pinctrl-0 = <&reset_out_pins>; + pinctrl-names = "default"; + + gsbi3_pins: gsbi3_pins { + mux { + pins = "gpio8", "gpio9", "gpio10", "gpio11"; + function = "gsbi3"; + drive-strength = <8>; + bias-disable; + }; + }; + + gsbi4_pins: gsbi4_pins { + mux { + pins = "gpio12", "gpio13", "gpio14", "gpio15"; + function = "gsbi4"; + drive-strength = <8>; + bias-disable; + }; + }; + + gsbi5_i2c_pins: gsbi5_i2c_pins { + pin16 { + pins = "gpio16"; + function = "gsbi5_i2c"; + drive-strength = <8>; + bias-disable; + }; + + pin17 { + pins = "gpio17"; + function = "gsbi5_i2c"; + drive-strength = <2>; + bias-disable; + }; + }; + + gsbi5_uart_pins: gsbi5_uart_pins { + mux { + pins = "gpio18", "gpio19"; + function = "gsbi5_uart"; + drive-strength = <8>; + bias-disable; + }; + }; + + reset_out_pins: reset_out_pins { + pins { + pins = "gpio66"; + function = "gpio"; + drive-strength = <2>; + bias-pull-up; + output-high; + }; + }; +}; + +&pmicgpio { + usb_vbus_5v_pins: usb_vbus_5v_pins { + pins = "gpio4"; + function = "normal"; + output-high; + bias-disable; + qcom,drive-strength = <1>; + power-source = <2>; + }; +}; + +&gsbi3 { + status = "ok"; + qcom,mode = <GSBI_PROT_SPI>; +}; + +&gsbi3_spi { + status = "ok"; + pinctrl-0 = <&gsbi3_pins>; + pinctrl-names = "default"; + assigned-clocks = <&gcc GSBI3_QUP_CLK>; + assigned-clock-rates = <24000000>; +}; + +&gsbi4 { + status = "ok"; + qcom,mode = <GSBI_PROT_UART_W_FC>; +}; + +&gsbi4_serial { + status = "ok"; + pinctrl-0 = <&gsbi4_pins>; + pinctrl-names = "default"; +}; + +&gsbi5 { + status = "ok"; + qcom,mode = <GSBI_PROT_I2C_UART>; +}; + +&gsbi5_i2c { + status = "ok"; + clock-frequency = <200000>; + pinctrl-0 = <&gsbi5_i2c_pins>; + pinctrl-names = "default"; +}; + +&gsbi5_serial { + status = "ok"; + pinctrl-0 = <&gsbi5_uart_pins>; + pinctrl-names = "default"; +}; + +&sdcc1 { + status = "ok"; +}; diff --git a/arch/arm/boot/dts/qcom-mdm9615.dtsi b/arch/arm/boot/dts/qcom-mdm9615.dtsi new file mode 100644 index 000000000000..5ae4ec59e6ea --- /dev/null +++ b/arch/arm/boot/dts/qcom-mdm9615.dtsi @@ -0,0 +1,557 @@ +/* + * Device Tree Source for Qualcomm MDM9615 SoC + * + * Copyright (C) 2016 BayLibre, SAS. + * Author : Neil Armstrong <narmstrong@baylibre.com> + * + * This file is dual-licensed: you can use it either under the terms + * of the GPL or the X11 license, at your option. Note that this dual + * licensing only applies to this file, and not this project as a + * whole. + * + * a) This file is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of the + * License, or (at your option) any later version. + * + * This file is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * Or, alternatively, + * + * b) Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, + * copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following + * conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + */ + +/dts-v1/; + +/include/ "skeleton.dtsi" + +#include <dt-bindings/interrupt-controller/arm-gic.h> +#include <dt-bindings/clock/qcom,gcc-mdm9615.h> +#include <dt-bindings/reset/qcom,gcc-mdm9615.h> +#include <dt-bindings/mfd/qcom-rpm.h> +#include <dt-bindings/soc/qcom,gsbi.h> + +/ { + model = "Qualcomm MDM9615"; + compatible = "qcom,mdm9615"; + interrupt-parent = <&intc>; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + + cpu0: cpu@0 { + compatible = "arm,cortex-a5"; + device_type = "cpu"; + next-level-cache = <&L2>; + }; + }; + + cpu-pmu { + compatible = "arm,cortex-a5-pmu"; + interrupts = <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_HIGH)>; + }; + + clocks { + cxo_board { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <19200000>; + }; + }; + + regulators { + vsdcc_fixed: vsdcc-regulator { + compatible = "regulator-fixed"; + regulator-name = "SDCC Power"; + regulator-min-microvolt = <2700000>; + regulator-max-microvolt = <2700000>; + regulator-always-on; + }; + }; + + soc: soc { + #address-cells = <1>; + #size-cells = <1>; + ranges; + compatible = "simple-bus"; + + L2: l2-cache@2040000 { + compatible = "arm,pl310-cache"; + reg = <0x02040000 0x1000>; + arm,data-latency = <2 2 0>; + cache-unified; + cache-level = <2>; + }; + + intc: interrupt-controller@2000000 { + compatible = "qcom,msm-qgic2"; + interrupt-controller; + #interrupt-cells = <3>; + reg = <0x02000000 0x1000>, + <0x02002000 0x1000>; + }; + + timer@200a000 { + compatible = "qcom,kpss-timer", "qcom,msm-timer"; + interrupts = <GIC_PPI 1 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_EDGE_RISING)>, + <GIC_PPI 2 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_EDGE_RISING)>, + <GIC_PPI 3 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_EDGE_RISING)>; + reg = <0x0200a000 0x100>; + clock-frequency = <27000000>, + <32768>; + cpu-offset = <0x80000>; + }; + + msmgpio: pinctrl@800000 { + compatible = "qcom,mdm9615-pinctrl"; + gpio-controller; + #gpio-cells = <2>; + interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>; + interrupt-controller; + #interrupt-cells = <2>; + reg = <0x800000 0x4000>; + }; + + gcc: clock-controller@900000 { + compatible = "qcom,gcc-mdm9615"; + #clock-cells = <1>; + #reset-cells = <1>; + reg = <0x900000 0x4000>; + }; + + lcc: clock-controller@28000000 { + compatible = "qcom,lcc-mdm9615"; + reg = <0x28000000 0x1000>; + #clock-cells = <1>; + #reset-cells = <1>; + }; + + l2cc: clock-controller@2011000 { + compatible = "syscon"; + reg = <0x02011000 0x1000>; + }; + + rng@1a500000 { + compatible = "qcom,prng"; + reg = <0x1a500000 0x200>; + clocks = <&gcc PRNG_CLK>; + clock-names = "core"; + assigned-clocks = <&gcc PRNG_CLK>; + assigned-clock-rates = <32000000>; + }; + + gsbi2: gsbi@16100000 { + compatible = "qcom,gsbi-v1.0.0"; + cell-index = <2>; + reg = <0x16100000 0x100>; + clocks = <&gcc GSBI2_H_CLK>; + clock-names = "iface"; + status = "disabled"; + #address-cells = <1>; + #size-cells = <1>; + ranges; + + gsbi2_i2c: i2c@16180000 { + compatible = "qcom,i2c-qup-v1.1.1"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x16180000 0x1000>; + interrupts = <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>; + + clocks = <&gcc GSBI2_QUP_CLK>, <&gcc GSBI2_H_CLK>; + clock-names = "core", "iface"; + status = "disabled"; + }; + }; + + gsbi3: gsbi@16200000 { + compatible = "qcom,gsbi-v1.0.0"; + cell-index = <3>; + reg = <0x16200000 0x100>; + clocks = <&gcc GSBI3_H_CLK>; + clock-names = "iface"; + status = "disabled"; + #address-cells = <1>; + #size-cells = <1>; + ranges; + + gsbi3_spi: spi@16280000 { + compatible = "qcom,spi-qup-v1.1.1"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x16280000 0x1000>; + interrupts = <GIC_SPI 151 IRQ_TYPE_LEVEL_HIGH>; + spi-max-frequency = <24000000>; + + clocks = <&gcc GSBI3_QUP_CLK>, <&gcc GSBI3_H_CLK>; + clock-names = "core", "iface"; + status = "disabled"; + }; + }; + + gsbi4: gsbi@16300000 { + compatible = "qcom,gsbi-v1.0.0"; + cell-index = <4>; + reg = <0x16300000 0x100>; + clocks = <&gcc GSBI4_H_CLK>; + clock-names = "iface"; + status = "disabled"; + #address-cells = <1>; + #size-cells = <1>; + ranges; + + syscon-tcsr = <&tcsr>; + + gsbi4_serial: serial@16340000 { + compatible = "qcom,msm-uartdm-v1.3", "qcom,msm-uartdm"; + reg = <0x16340000 0x1000>, + <0x16300000 0x1000>; + interrupts = <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&gcc GSBI4_UART_CLK>, <&gcc GSBI4_H_CLK>; + clock-names = "core", "iface"; + status = "disabled"; + }; + }; + + gsbi5: gsbi@16400000 { + compatible = "qcom,gsbi-v1.0.0"; + cell-index = <5>; + reg = <0x16400000 0x100>; + clocks = <&gcc GSBI5_H_CLK>; + clock-names = "iface"; + status = "disabled"; + #address-cells = <1>; + #size-cells = <1>; + ranges; + + syscon-tcsr = <&tcsr>; + + gsbi5_i2c: i2c@16480000 { + compatible = "qcom,i2c-qup-v1.1.1"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x16480000 0x1000>; + interrupts = <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>; + + /* QUP clock is not initialized, set rate */ + assigned-clocks = <&gcc GSBI5_QUP_CLK>; + assigned-clock-rates = <24000000>; + + clocks = <&gcc GSBI5_QUP_CLK>, <&gcc GSBI5_H_CLK>; + clock-names = "core", "iface"; + status = "disabled"; + }; + + gsbi5_serial: serial@16440000 { + compatible = "qcom,msm-uartdm-v1.3", "qcom,msm-uartdm"; + reg = <0x16440000 0x1000>, + <0x16400000 0x1000>; + interrupts = <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&gcc GSBI5_UART_CLK>, <&gcc GSBI5_H_CLK>; + clock-names = "core", "iface"; + status = "disabled"; + }; + }; + + qcom,ssbi@500000 { + compatible = "qcom,ssbi"; + reg = <0x500000 0x1000>; + qcom,controller-type = "pmic-arbiter"; + + pmicintc: pmic@0 { + compatible = "qcom,pm8018", "qcom,pm8921"; + interrupts = <GIC_PPI 226 IRQ_TYPE_LEVEL_HIGH>; + #interrupt-cells = <2>; + interrupt-controller; + #address-cells = <1>; + #size-cells = <0>; + + pwrkey@1c { + compatible = "qcom,pm8018-pwrkey", "qcom,pm8921-pwrkey"; + reg = <0x1c>; + interrupt-parent = <&pmicintc>; + interrupts = <50 IRQ_TYPE_EDGE_RISING>, + <51 IRQ_TYPE_EDGE_RISING>; + debounce = <15625>; + pull-up; + }; + + pmicmpp: mpp@50 { + compatible = "qcom,pm8018-mpp", "qcom,ssbi-mpp"; + interrupt-parent = <&pmicintc>; + interrupts = <24 IRQ_TYPE_NONE>, + <25 IRQ_TYPE_NONE>, + <26 IRQ_TYPE_NONE>, + <27 IRQ_TYPE_NONE>, + <28 IRQ_TYPE_NONE>, + <29 IRQ_TYPE_NONE>; + reg = <0x50>; + gpio-controller; + #gpio-cells = <2>; + }; + + rtc@11d { + compatible = "qcom,pm8018-rtc", "qcom,pm8921-rtc"; + interrupt-parent = <&pmicintc>; + interrupts = <39 IRQ_TYPE_EDGE_RISING>; + reg = <0x11d>; + allow-set-time; + }; + + pmicgpio: gpio@150 { + compatible = "qcom,pm8018-gpio", "qcom,ssbi-gpio"; + interrupt-parent = <&pmicintc>; + interrupts = <24 IRQ_TYPE_NONE>, + <25 IRQ_TYPE_NONE>, + <26 IRQ_TYPE_NONE>, + <27 IRQ_TYPE_NONE>, + <28 IRQ_TYPE_NONE>, + <29 IRQ_TYPE_NONE>; + gpio-controller; + #gpio-cells = <2>; + }; + }; + }; + + sdcc1bam: dma@12182000{ + compatible = "qcom,bam-v1.3.0"; + reg = <0x12182000 0x8000>; + interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&gcc SDC1_H_CLK>; + clock-names = "bam_clk"; + #dma-cells = <1>; + qcom,ee = <0>; + }; + + sdcc2bam: dma@12142000{ + compatible = "qcom,bam-v1.3.0"; + reg = <0x12142000 0x8000>; + interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&gcc SDC2_H_CLK>; + clock-names = "bam_clk"; + #dma-cells = <1>; + qcom,ee = <0>; + }; + + amba { + compatible = "arm,amba-bus"; + #address-cells = <1>; + #size-cells = <1>; + ranges; + sdcc1: sdcc@12180000 { + status = "disabled"; + compatible = "arm,pl18x", "arm,primecell"; + arm,primecell-periphid = <0x00051180>; + reg = <0x12180000 0x2000>; + interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "cmd_irq"; + clocks = <&gcc SDC1_CLK>, <&gcc SDC1_H_CLK>; + clock-names = "mclk", "apb_pclk"; + bus-width = <8>; + max-frequency = <48000000>; + cap-sd-highspeed; + cap-mmc-highspeed; + vmmc-supply = <&vsdcc_fixed>; + dmas = <&sdcc1bam 2>, <&sdcc1bam 1>; + dma-names = "tx", "rx"; + assigned-clocks = <&gcc SDC1_CLK>; + assigned-clock-rates = <400000>; + }; + + sdcc2: sdcc@12140000 { + compatible = "arm,pl18x", "arm,primecell"; + arm,primecell-periphid = <0x00051180>; + status = "disabled"; + reg = <0x12140000 0x2000>; + interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "cmd_irq"; + clocks = <&gcc SDC2_CLK>, <&gcc SDC2_H_CLK>; + clock-names = "mclk", "apb_pclk"; + bus-width = <4>; + cap-sd-highspeed; + cap-mmc-highspeed; + max-frequency = <48000000>; + no-1-8-v; + vmmc-supply = <&vsdcc_fixed>; + dmas = <&sdcc2bam 2>, <&sdcc2bam 1>; + dma-names = "tx", "rx"; + assigned-clocks = <&gcc SDC2_CLK>; + assigned-clock-rates = <400000>; + }; + }; + + tcsr: syscon@1a400000 { + compatible = "qcom,tcsr-mdm9615", "syscon"; + reg = <0x1a400000 0x100>; + }; + + rpm: rpm@108000 { + compatible = "qcom,rpm-mdm9615"; + reg = <0x108000 0x1000>; + + qcom,ipc = <&l2cc 0x8 2>; + + interrupts = <GIC_SPI 19 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 21 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 22 IRQ_TYPE_EDGE_RISING>; + interrupt-names = "ack", "err", "wakeup"; + + regulators { + compatible = "qcom,rpm-pm8018-regulators"; + + vin_lvs1-supply = <&pm8018_s3>; + + vdd_l7-supply = <&pm8018_s4>; + vdd_l8-supply = <&pm8018_s3>; + vdd_l9_l10_l11_l12-supply = <&pm8018_s5>; + + /* Buck SMPS */ + pm8018_s1: s1 { + regulator-min-microvolt = <500000>; + regulator-max-microvolt = <1150000>; + qcom,switch-mode-frequency = <1600000>; + bias-pull-down; + }; + + pm8018_s2: s2 { + regulator-min-microvolt = <1225000>; + regulator-max-microvolt = <1300000>; + qcom,switch-mode-frequency = <1600000>; + bias-pull-down; + }; + + pm8018_s3: s3 { + regulator-always-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + qcom,switch-mode-frequency = <1600000>; + bias-pull-down; + }; + + pm8018_s4: s4 { + regulator-min-microvolt = <2100000>; + regulator-max-microvolt = <2200000>; + qcom,switch-mode-frequency = <1600000>; + bias-pull-down; + }; + + pm8018_s5: s5 { + regulator-always-on; + regulator-min-microvolt = <1350000>; + regulator-max-microvolt = <1350000>; + qcom,switch-mode-frequency = <1600000>; + bias-pull-down; + }; + + /* PMOS LDO */ + pm8018_l2: l2 { + regulator-always-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + bias-pull-down; + }; + + pm8018_l3: l3 { + regulator-always-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + bias-pull-down; + }; + + pm8018_l4: l4 { + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + bias-pull-down; + }; + + pm8018_l5: l5 { + regulator-min-microvolt = <2850000>; + regulator-max-microvolt = <2850000>; + bias-pull-down; + }; + + pm8018_l6: l6 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <2850000>; + bias-pull-down; + }; + + pm8018_l7: l7 { + regulator-min-microvolt = <1850000>; + regulator-max-microvolt = <1900000>; + bias-pull-down; + }; + + pm8018_l8: l8 { + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + bias-pull-down; + }; + + pm8018_l9: l9 { + regulator-min-microvolt = <750000>; + regulator-max-microvolt = <1150000>; + bias-pull-down; + }; + + pm8018_l10: l10 { + regulator-min-microvolt = <1050000>; + regulator-max-microvolt = <1050000>; + bias-pull-down; + }; + + pm8018_l11: l11 { + regulator-min-microvolt = <1050000>; + regulator-max-microvolt = <1050000>; + bias-pull-down; + }; + + pm8018_l12: l12 { + regulator-min-microvolt = <1050000>; + regulator-max-microvolt = <1050000>; + bias-pull-down; + }; + + pm8018_l13: l13 { + regulator-min-microvolt = <1850000>; + regulator-max-microvolt = <2950000>; + bias-pull-down; + }; + + pm8018_l14: l14 { + regulator-min-microvolt = <2850000>; + regulator-max-microvolt = <2850000>; + bias-pull-down; + }; + + /* Low Voltage Switch */ + pm8018_lvs1: lvs1 { + bias-pull-down; + }; + }; + }; + }; +}; diff --git a/arch/arm/boot/dts/qcom-msm8660.dtsi b/arch/arm/boot/dts/qcom-msm8660.dtsi index 8c65e0d82559..4d828f810746 100644 --- a/arch/arm/boot/dts/qcom-msm8660.dtsi +++ b/arch/arm/boot/dts/qcom-msm8660.dtsi @@ -141,6 +141,23 @@ }; }; + external-bus@1a100000 { + compatible = "qcom,msm8660-ebi2"; + #address-cells = <2>; + #size-cells = <1>; + ranges = <0 0x0 0x1a800000 0x00800000>, + <1 0x0 0x1b000000 0x00800000>, + <2 0x0 0x1b800000 0x00800000>, + <3 0x0 0x1d000000 0x08000000>, + <4 0x0 0x1c800000 0x00800000>, + <5 0x0 0x1c000000 0x00800000>; + reg = <0x1a100000 0x1000>, <0x1a110000 0x1000>; + reg-names = "ebi2", "xmem"; + clocks = <&gcc EBI2_2X_CLK>, <&gcc EBI2_CLK>; + clock-names = "ebi2x", "ebi2"; + status = "disabled"; + }; + qcom,ssbi@500000 { compatible = "qcom,ssbi"; reg = <0x500000 0x1000>; diff --git a/arch/arm/boot/dts/qcom-msm8974-lge-nexus5-hammerhead.dts b/arch/arm/boot/dts/qcom-msm8974-lge-nexus5-hammerhead.dts index c0fb4a698c56..382bcc3231a9 100644 --- a/arch/arm/boot/dts/qcom-msm8974-lge-nexus5-hammerhead.dts +++ b/arch/arm/boot/dts/qcom-msm8974-lge-nexus5-hammerhead.dts @@ -224,6 +224,35 @@ status = "ok"; }; + pinctrl@fd510000 { + sdhc1_pin_a: sdhc1-pin-active { + clk { + pins = "sdc1_clk"; + drive-strength = <16>; + bias-disable; + }; + + cmd-data { + pins = "sdc1_cmd", "sdc1_data"; + drive-strength = <10>; + bias-pull-up; + }; + }; + }; + + sdhci@f9824900 { + status = "ok"; + + vmmc-supply = <&pm8941_l20>; + vqmmc-supply = <&pm8941_s3>; + + bus-width = <8>; + non-removable; + + pinctrl-names = "default"; + pinctrl-0 = <&sdhc1_pin_a>; + }; + gpio-keys { compatible = "gpio-keys"; input-name = "gpio-keys"; diff --git a/arch/arm/boot/dts/r7s72100-rskrza1.dts b/arch/arm/boot/dts/r7s72100-rskrza1.dts index e5dea5bb4032..dd4418195ca6 100644 --- a/arch/arm/boot/dts/r7s72100-rskrza1.dts +++ b/arch/arm/boot/dts/r7s72100-rskrza1.dts @@ -56,6 +56,11 @@ }; }; +&sdhi1 { + bus-width = <4>; + status = "okay"; +}; + &scif2 { status = "okay"; }; diff --git a/arch/arm/boot/dts/r7s72100.dtsi b/arch/arm/boot/dts/r7s72100.dtsi index fb9ef9ca120e..3dd427d68c83 100644 --- a/arch/arm/boot/dts/r7s72100.dtsi +++ b/arch/arm/boot/dts/r7s72100.dtsi @@ -117,6 +117,15 @@ clock-output-names = "ether"; }; + mstp8_clks: mstp8_clks@fcfe0434 { + #clock-cells = <1>; + compatible = "renesas,r7s72100-mstp-clocks", "renesas,cpg-mstp-clocks"; + reg = <0xfcfe0434 4>; + clocks = <&p1_clk>; + clock-indices = <R7S72100_CLK_MMCIF>; + clock-output-names = "mmcif"; + }; + mstp9_clks: mstp9_clks@fcfe0438 { #clock-cells = <1>; compatible = "renesas,r7s72100-mstp-clocks", "renesas,cpg-mstp-clocks"; @@ -140,6 +149,14 @@ >; clock-output-names = "spi0", "spi1", "spi2", "spi3", "spi4"; }; + mstp12_clks: mstp12_clks@fcfe0444 { + #clock-cells = <1>; + compatible = "renesas,r7s72100-mstp-clocks", "renesas,cpg-mstp-clocks"; + reg = <0xfcfe0444 4>; + clocks = <&p1_clk>, <&p1_clk>; + clock-indices = <R7S72100_CLK_SDHI1 R7S72100_CLK_SDHI0>; + clock-output-names = "sdhi1", "sdhi0"; + }; }; cpus { @@ -441,4 +458,42 @@ #size-cells = <0>; status = "disabled"; }; + + mmcif: mmc@e804c800 { + compatible = "renesas,mmcif-r7s72100", "renesas,sh-mmcif"; + reg = <0xe804c800 0x80>; + interrupts = <GIC_SPI 268 IRQ_TYPE_LEVEL_HIGH + GIC_SPI 269 IRQ_TYPE_LEVEL_HIGH + GIC_SPI 267 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&mstp8_clks R7S72100_CLK_MMCIF>; + reg-io-width = <4>; + bus-width = <8>; + status = "disabled"; + }; + + sdhi0: sd@e804e000 { + compatible = "renesas,sdhi-r7s72100"; + reg = <0xe804e000 0x100>; + interrupts = <GIC_SPI 270 IRQ_TYPE_LEVEL_HIGH + GIC_SPI 271 IRQ_TYPE_LEVEL_HIGH + GIC_SPI 272 IRQ_TYPE_LEVEL_HIGH>; + + clocks = <&mstp12_clks R7S72100_CLK_SDHI0>; + cap-sd-highspeed; + cap-sdio-irq; + status = "disabled"; + }; + + sdhi1: sd@e804e800 { + compatible = "renesas,sdhi-r7s72100"; + reg = <0xe804e800 0x100>; + interrupts = <GIC_SPI 273 IRQ_TYPE_LEVEL_HIGH + GIC_SPI 274 IRQ_TYPE_LEVEL_HIGH + GIC_SPI 275 IRQ_TYPE_LEVEL_HIGH>; + + clocks = <&mstp12_clks R7S72100_CLK_SDHI1>; + cap-sd-highspeed; + cap-sdio-irq; + status = "disabled"; + }; }; diff --git a/arch/arm/boot/dts/r8a7740.dtsi b/arch/arm/boot/dts/r8a7740.dtsi index 159e04eb1b9e..34159a8349de 100644 --- a/arch/arm/boot/dts/r8a7740.dtsi +++ b/arch/arm/boot/dts/r8a7740.dtsi @@ -8,8 +8,6 @@ * kind, whether express or implied. */ -/include/ "skeleton.dtsi" - #include <dt-bindings/clock/r8a7740-clock.h> #include <dt-bindings/interrupt-controller/arm-gic.h> #include <dt-bindings/interrupt-controller/irq.h> @@ -17,6 +15,8 @@ / { compatible = "renesas,r8a7740"; interrupt-parent = <&gic>; + #address-cells = <1>; + #size-cells = <1>; cpus { #address-cells = <1>; diff --git a/arch/arm/boot/dts/r8a7778.dtsi b/arch/arm/boot/dts/r8a7778.dtsi index e571d66ea0fe..f3ffe1d31544 100644 --- a/arch/arm/boot/dts/r8a7778.dtsi +++ b/arch/arm/boot/dts/r8a7778.dtsi @@ -14,8 +14,6 @@ * kind, whether express or implied. */ -/include/ "skeleton.dtsi" - #include <dt-bindings/clock/r8a7778-clock.h> #include <dt-bindings/interrupt-controller/arm-gic.h> #include <dt-bindings/interrupt-controller/irq.h> @@ -23,6 +21,8 @@ / { compatible = "renesas,r8a7778"; interrupt-parent = <&gic>; + #address-cells = <1>; + #size-cells = <1>; cpus { #address-cells = <1>; diff --git a/arch/arm/boot/dts/r8a7779-marzen.dts b/arch/arm/boot/dts/r8a7779-marzen.dts index 541678df90a9..676151b70185 100644 --- a/arch/arm/boot/dts/r8a7779-marzen.dts +++ b/arch/arm/boot/dts/r8a7779-marzen.dts @@ -170,7 +170,7 @@ du_pins: du { du0 { - groups = "du0_rgb888", "du0_sync_1", "du0_clk_out_0"; + groups = "du0_rgb888", "du0_sync_1", "du0_clk_out_0", "du0_clk_in"; function = "du0"; }; du1 { diff --git a/arch/arm/boot/dts/r8a7779.dtsi b/arch/arm/boot/dts/r8a7779.dtsi index b9bbcce69dfb..3005308a1807 100644 --- a/arch/arm/boot/dts/r8a7779.dtsi +++ b/arch/arm/boot/dts/r8a7779.dtsi @@ -9,8 +9,6 @@ * kind, whether express or implied. */ -/include/ "skeleton.dtsi" - #include <dt-bindings/clock/r8a7779-clock.h> #include <dt-bindings/interrupt-controller/arm-gic.h> #include <dt-bindings/interrupt-controller/irq.h> @@ -19,6 +17,8 @@ / { compatible = "renesas,r8a7779"; interrupt-parent = <&gic>; + #address-cells = <1>; + #size-cells = <1>; cpus { #address-cells = <1>; @@ -420,7 +420,7 @@ du: display@fff80000 { compatible = "renesas,du-r8a7779"; - reg = <0 0xfff80000 0 0x40000>; + reg = <0xfff80000 0x40000>; interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>; clocks = <&mstp1_clks R8A7779_CLK_DU>; power-domains = <&sysc R8A7779_PD_ALWAYS_ON>; diff --git a/arch/arm/boot/dts/r8a7790-lager.dts b/arch/arm/boot/dts/r8a7790-lager.dts index 52b56fcaddf2..434268262d88 100644 --- a/arch/arm/boot/dts/r8a7790-lager.dts +++ b/arch/arm/boot/dts/r8a7790-lager.dts @@ -231,12 +231,23 @@ }; }; + hdmi-in { + compatible = "hdmi-connector"; + type = "a"; + + port { + hdmi_con_in: endpoint { + remote-endpoint = <&adv7612_in>; + }; + }; + }; + hdmi-out { compatible = "hdmi-connector"; type = "a"; port { - hdmi_con: endpoint { + hdmi_con_out: endpoint { remote-endpoint = <&adv7511_out>; }; }; @@ -427,6 +438,11 @@ function = "usb2"; }; + vin0_pins: vin0 { + groups = "vin0_data24", "vin0_sync", "vin0_clkenb", "vin0_clk"; + function = "vin0"; + }; + vin1_pins: vin1 { groups = "vin1_data8", "vin1_clk"; function = "vin1"; @@ -646,7 +662,34 @@ port@1 { reg = <1>; adv7511_out: endpoint { - remote-endpoint = <&hdmi_con>; + remote-endpoint = <&hdmi_con_out>; + }; + }; + }; + }; + + hdmi-in@4c { + compatible = "adi,adv7612"; + reg = <0x4c>; + interrupt-parent = <&gpio1>; + interrupts = <20 IRQ_TYPE_LEVEL_LOW>; + default-input = <0>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + adv7612_in: endpoint { + remote-endpoint = <&hdmi_con_in>; + }; + }; + + port@2 { + reg = <2>; + adv7612_out: endpoint { + remote-endpoint = <&vin0ep2>; }; }; }; @@ -722,6 +765,25 @@ status = "okay"; }; +/* HDMI video input */ +&vin0 { + pinctrl-0 = <&vin0_pins>; + pinctrl-names = "default"; + + status = "okay"; + + port { + vin0ep2: endpoint { + remote-endpoint = <&adv7612_out>; + bus-width = <24>; + hsync-active = <0>; + vsync-active = <0>; + pclk-sample = <1>; + data-active = <1>; + }; + }; +}; + /* composite video input */ &vin1 { pinctrl-0 = <&vin1_pins>; diff --git a/arch/arm/boot/dts/r8a7790.dtsi b/arch/arm/boot/dts/r8a7790.dtsi index 351fcc2f87df..a946474be9cf 100644 --- a/arch/arm/boot/dts/r8a7790.dtsi +++ b/arch/arm/boot/dts/r8a7790.dtsi @@ -711,7 +711,7 @@ scifb0: serial@e6c20000 { compatible = "renesas,scifb-r8a7790", "renesas,rcar-gen2-scifb", "renesas,scifb"; - reg = <0 0xe6c20000 0 64>; + reg = <0 0xe6c20000 0 0x100>; interrupts = <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>; clocks = <&mstp2_clks R8A7790_CLK_SCIFB0>; clock-names = "fck"; @@ -725,7 +725,7 @@ scifb1: serial@e6c30000 { compatible = "renesas,scifb-r8a7790", "renesas,rcar-gen2-scifb", "renesas,scifb"; - reg = <0 0xe6c30000 0 64>; + reg = <0 0xe6c30000 0 0x100>; interrupts = <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>; clocks = <&mstp2_clks R8A7790_CLK_SCIFB1>; clock-names = "fck"; @@ -739,7 +739,7 @@ scifb2: serial@e6ce0000 { compatible = "renesas,scifb-r8a7790", "renesas,rcar-gen2-scifb", "renesas,scifb"; - reg = <0 0xe6ce0000 0 64>; + reg = <0 0xe6ce0000 0 0x100>; interrupts = <GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH>; clocks = <&mstp2_clks R8A7790_CLK_SCIFB2>; clock-names = "fck"; diff --git a/arch/arm/boot/dts/r8a7791-koelsch.dts b/arch/arm/boot/dts/r8a7791-koelsch.dts index f8a7d090fd01..c457b43deb7d 100644 --- a/arch/arm/boot/dts/r8a7791-koelsch.dts +++ b/arch/arm/boot/dts/r8a7791-koelsch.dts @@ -265,12 +265,23 @@ }; }; + hdmi-in { + compatible = "hdmi-connector"; + type = "a"; + + port { + hdmi_con_in: endpoint { + remote-endpoint = <&adv7612_in>; + }; + }; + }; + hdmi-out { compatible = "hdmi-connector"; type = "a"; port { - hdmi_con: endpoint { + hdmi_con_out: endpoint { remote-endpoint = <&adv7511_out>; }; }; @@ -360,16 +371,37 @@ sdhi0_pins: sd0 { groups = "sdhi0_data4", "sdhi0_ctrl"; function = "sdhi0"; + power-source = <3300>; + }; + + sdhi0_pins_uhs: sd0_uhs { + groups = "sdhi0_data4", "sdhi0_ctrl"; + function = "sdhi0"; + power-source = <1800>; }; sdhi1_pins: sd1 { groups = "sdhi1_data4", "sdhi1_ctrl"; function = "sdhi1"; + power-source = <3300>; + }; + + sdhi1_pins_uhs: sd1_uhs { + groups = "sdhi1_data4", "sdhi1_ctrl"; + function = "sdhi1"; + power-source = <1800>; }; sdhi2_pins: sd2 { groups = "sdhi2_data4", "sdhi2_ctrl"; function = "sdhi2"; + power-source = <3300>; + }; + + sdhi2_pins_uhs: sd2_uhs { + groups = "sdhi2_data4", "sdhi2_ctrl"; + function = "sdhi2"; + power-source = <1800>; }; qspi_pins: qspi { @@ -393,6 +425,11 @@ function = "usb1"; }; + vin0_pins: vin0 { + groups = "vin0_data24", "vin0_sync", "vin0_clkenb", "vin0_clk"; + function = "vin0"; + }; + vin1_pins: vin1 { groups = "vin1_data8", "vin1_clk"; function = "vin1"; @@ -454,33 +491,39 @@ &sdhi0 { pinctrl-0 = <&sdhi0_pins>; - pinctrl-names = "default"; + pinctrl-1 = <&sdhi0_pins_uhs>; + pinctrl-names = "default", "state_uhs"; vmmc-supply = <&vcc_sdhi0>; vqmmc-supply = <&vccq_sdhi0>; cd-gpios = <&gpio6 6 GPIO_ACTIVE_LOW>; wp-gpios = <&gpio6 7 GPIO_ACTIVE_HIGH>; + sd-uhs-sdr50; status = "okay"; }; &sdhi1 { pinctrl-0 = <&sdhi1_pins>; - pinctrl-names = "default"; + pinctrl-1 = <&sdhi1_pins_uhs>; + pinctrl-names = "default", "state_uhs"; vmmc-supply = <&vcc_sdhi1>; vqmmc-supply = <&vccq_sdhi1>; cd-gpios = <&gpio6 14 GPIO_ACTIVE_LOW>; wp-gpios = <&gpio6 15 GPIO_ACTIVE_HIGH>; + sd-uhs-sdr50; status = "okay"; }; &sdhi2 { pinctrl-0 = <&sdhi2_pins>; - pinctrl-names = "default"; + pinctrl-1 = <&sdhi2_pins_uhs>; + pinctrl-names = "default", "state_uhs"; vmmc-supply = <&vcc_sdhi2>; vqmmc-supply = <&vccq_sdhi2>; cd-gpios = <&gpio6 22 GPIO_ACTIVE_LOW>; + sd-uhs-sdr50; status = "okay"; }; @@ -590,7 +633,34 @@ port@1 { reg = <1>; adv7511_out: endpoint { - remote-endpoint = <&hdmi_con>; + remote-endpoint = <&hdmi_con_out>; + }; + }; + }; + }; + + hdmi-in@4c { + compatible = "adi,adv7612"; + reg = <0x4c>; + interrupt-parent = <&gpio4>; + interrupts = <2 IRQ_TYPE_LEVEL_LOW>; + default-input = <0>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + adv7612_in: endpoint { + remote-endpoint = <&hdmi_con_in>; + }; + }; + + port@2 { + reg = <2>; + adv7612_out: endpoint { + remote-endpoint = <&vin0ep2>; }; }; }; @@ -672,6 +742,27 @@ cpu0-supply = <&vdd_dvfs>; }; +/* HDMI video input */ +&vin0 { + status = "okay"; + pinctrl-0 = <&vin0_pins>; + pinctrl-names = "default"; + + port { + #address-cells = <1>; + #size-cells = <0>; + + vin0ep2: endpoint { + remote-endpoint = <&adv7612_out>; + bus-width = <24>; + hsync-active = <0>; + vsync-active = <0>; + pclk-sample = <1>; + data-active = <1>; + }; + }; +}; + /* composite video input */ &vin1 { status = "okay"; diff --git a/arch/arm/boot/dts/r8a7791.dtsi b/arch/arm/boot/dts/r8a7791.dtsi index 162b55c665a3..091d7fb6ee7d 100644 --- a/arch/arm/boot/dts/r8a7791.dtsi +++ b/arch/arm/boot/dts/r8a7791.dtsi @@ -584,6 +584,7 @@ dmas = <&dmac0 0xcd>, <&dmac0 0xce>, <&dmac1 0xcd>, <&dmac1 0xce>; dma-names = "tx", "rx", "tx", "rx"; + max-frequency = <195000000>; power-domains = <&sysc R8A7791_PD_ALWAYS_ON>; status = "disabled"; }; @@ -596,6 +597,7 @@ dmas = <&dmac0 0xc1>, <&dmac0 0xc2>, <&dmac1 0xc1>, <&dmac1 0xc2>; dma-names = "tx", "rx", "tx", "rx"; + max-frequency = <97500000>; power-domains = <&sysc R8A7791_PD_ALWAYS_ON>; status = "disabled"; }; @@ -608,6 +610,7 @@ dmas = <&dmac0 0xd3>, <&dmac0 0xd4>, <&dmac1 0xd3>, <&dmac1 0xd4>; dma-names = "tx", "rx", "tx", "rx"; + max-frequency = <97500000>; power-domains = <&sysc R8A7791_PD_ALWAYS_ON>; status = "disabled"; }; @@ -699,7 +702,7 @@ scifb0: serial@e6c20000 { compatible = "renesas,scifb-r8a7791", "renesas,rcar-gen2-scifb", "renesas,scifb"; - reg = <0 0xe6c20000 0 64>; + reg = <0 0xe6c20000 0 0x100>; interrupts = <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>; clocks = <&mstp2_clks R8A7791_CLK_SCIFB0>; clock-names = "fck"; @@ -713,7 +716,7 @@ scifb1: serial@e6c30000 { compatible = "renesas,scifb-r8a7791", "renesas,rcar-gen2-scifb", "renesas,scifb"; - reg = <0 0xe6c30000 0 64>; + reg = <0 0xe6c30000 0 0x100>; interrupts = <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>; clocks = <&mstp2_clks R8A7791_CLK_SCIFB1>; clock-names = "fck"; @@ -727,7 +730,7 @@ scifb2: serial@e6ce0000 { compatible = "renesas,scifb-r8a7791", "renesas,rcar-gen2-scifb", "renesas,scifb"; - reg = <0 0xe6ce0000 0 64>; + reg = <0 0xe6ce0000 0 0x100>; interrupts = <GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH>; clocks = <&mstp2_clks R8A7791_CLK_SCIFB2>; clock-names = "fck"; diff --git a/arch/arm/boot/dts/r8a7792-wheat.dts b/arch/arm/boot/dts/r8a7792-wheat.dts index 6dbb94114a93..c24f26fdab1f 100644 --- a/arch/arm/boot/dts/r8a7792-wheat.dts +++ b/arch/arm/boot/dts/r8a7792-wheat.dts @@ -86,6 +86,34 @@ gpio = <&gpio11 12 GPIO_ACTIVE_HIGH>; enable-active-high; }; + + hdmi-out0 { + compatible = "hdmi-connector"; + type = "a"; + + port { + hdmi_con0: endpoint { + remote-endpoint = <&adv7513_0_out>; + }; + }; + }; + + hdmi-out1 { + compatible = "hdmi-connector"; + type = "a"; + + port { + hdmi_con1: endpoint { + remote-endpoint = <&adv7513_1_out>; + }; + }; + }; + + osc2_clk: osc2 { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <74250000>; + }; }; &extal_clk { @@ -128,6 +156,16 @@ groups = "qspi_ctrl", "qspi_data4"; function = "qspi"; }; + + du0_pins: du0 { + groups = "du0_rgb888", "du0_sync", "du0_disp"; + function = "du0"; + }; + + du1_pins: du1 { + groups = "du1_rgb666", "du1_sync", "du1_disp"; + function = "du1"; + }; }; &scif0 { @@ -197,3 +235,91 @@ }; }; }; + +&i2c4 { + status = "okay"; + clock-frequency = <400000>; + + hdmi@3d { + compatible = "adi,adv7513"; + reg = <0x3d>; + + adi,input-depth = <8>; + adi,input-colorspace = "rgb"; + adi,input-clock = "1x"; + adi,input-style = <1>; + adi,input-justification = "evenly"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + adv7513_0_in: endpoint { + remote-endpoint = <&du_out_rgb0>; + }; + }; + + port@1 { + reg = <1>; + adv7513_0_out: endpoint { + remote-endpoint = <&hdmi_con0>; + }; + }; + }; + }; + + hdmi@39 { + compatible = "adi,adv7513"; + reg = <0x39>; + + adi,input-depth = <8>; + adi,input-colorspace = "rgb"; + adi,input-clock = "1x"; + adi,input-style = <1>; + adi,input-justification = "evenly"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + adv7513_1_in: endpoint { + remote-endpoint = <&du_out_rgb1>; + }; + }; + + port@1 { + reg = <1>; + adv7513_1_out: endpoint { + remote-endpoint = <&hdmi_con1>; + }; + }; + }; + }; +}; + +&du { + pinctrl-0 = <&du0_pins &du1_pins>; + pinctrl-names = "default"; + + clocks = <&mstp7_clks R8A7792_CLK_DU0>, <&mstp7_clks R8A7792_CLK_DU1>, + <&osc2_clk>; + clock-names = "du.0", "du.1", "dclkin.0"; + status = "okay"; + + ports { + port@0 { + endpoint { + remote-endpoint = <&adv7513_0_in>; + }; + }; + port@1 { + endpoint { + remote-endpoint = <&adv7513_1_in>; + }; + }; + }; +}; diff --git a/arch/arm/boot/dts/r8a7792.dtsi b/arch/arm/boot/dts/r8a7792.dtsi index 713141d38b3e..a75e0cd312c5 100644 --- a/arch/arm/boot/dts/r8a7792.dtsi +++ b/arch/arm/boot/dts/r8a7792.dtsi @@ -26,6 +26,8 @@ i2c4 = &i2c4; i2c5 = &i2c5; spi0 = &qspi; + spi1 = &msiof0; + spi2 = &msiof1; vin0 = &vin0; vin1 = &vin1; vin2 = &vin2; @@ -572,6 +574,34 @@ status = "disabled"; }; + msiof0: spi@e6e20000 { + compatible = "renesas,msiof-r8a7792"; + reg = <0 0xe6e20000 0 0x0064>; + interrupts = <GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&mstp0_clks R8A7792_CLK_MSIOF0>; + dmas = <&dmac0 0x51>, <&dmac0 0x52>, + <&dmac1 0x51>, <&dmac1 0x52>; + dma-names = "tx", "rx", "tx", "rx"; + power-domains = <&sysc R8A7792_PD_ALWAYS_ON>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + msiof1: spi@e6e10000 { + compatible = "renesas,msiof-r8a7792"; + reg = <0 0xe6e10000 0 0x0064>; + interrupts = <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&mstp2_clks R8A7792_CLK_MSIOF1>; + dmas = <&dmac0 0x55>, <&dmac0 0x56>, + <&dmac1 0x55>, <&dmac1 0x56>; + dma-names = "tx", "rx", "tx", "rx"; + power-domains = <&sysc R8A7792_PD_ALWAYS_ON>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + du: display@feb00000 { compatible = "renesas,du-r8a7792"; reg = <0 0xfeb00000 0 0x40000>; @@ -763,6 +793,13 @@ clock-div = <48>; clock-mult = <1>; }; + mp_clk: mp { + compatible = "fixed-factor-clock"; + clocks = <&pll1_div2_clk>; + #clock-cells = <0>; + clock-div = <15>; + clock-mult = <1>; + }; m2_clk: m2 { compatible = "fixed-factor-clock"; clocks = <&cpg_clocks R8A7792_CLK_PLL1>; @@ -793,6 +830,15 @@ }; /* Gate clocks */ + mstp0_clks: mstp0_clks@e6150130 { + compatible = "renesas,r8a7792-mstp-clocks", + "renesas,cpg-mstp-clocks"; + reg = <0 0xe6150130 0 4>, <0 0xe6150030 0 4>; + clocks = <&mp_clk>; + #clock-cells = <1>; + clock-indices = <R8A7792_CLK_MSIOF0>; + clock-output-names = "msiof0"; + }; mstp1_clks: mstp1_clks@e6150134 { compatible = "renesas,r8a7792-mstp-clocks", "renesas,cpg-mstp-clocks"; @@ -811,12 +857,13 @@ compatible = "renesas,r8a7792-mstp-clocks", "renesas,cpg-mstp-clocks"; reg = <0 0xe6150138 0 4>, <0 0xe6150040 0 4>; - clocks = <&zs_clk>, <&zs_clk>; + clocks = <&mp_clk>, <&zs_clk>, <&zs_clk>; #clock-cells = <1>; clock-indices = < + R8A7792_CLK_MSIOF1 R8A7792_CLK_SYS_DMAC1 R8A7792_CLK_SYS_DMAC0 >; - clock-output-names = "sys-dmac1", "sys-dmac0"; + clock-output-names = "msiof1", "sys-dmac1", "sys-dmac0"; }; mstp3_clks: mstp3_clks@e615013c { compatible = "renesas,r8a7792-mstp-clocks", diff --git a/arch/arm/boot/dts/r8a7793-gose.dts b/arch/arm/boot/dts/r8a7793-gose.dts index 90af18600124..dc311eba4444 100644 --- a/arch/arm/boot/dts/r8a7793-gose.dts +++ b/arch/arm/boot/dts/r8a7793-gose.dts @@ -346,18 +346,18 @@ }; sdhi0_pins: sd0 { - renesas,groups = "sdhi0_data4", "sdhi0_ctrl"; - renesas,function = "sdhi0"; + groups = "sdhi0_data4", "sdhi0_ctrl"; + function = "sdhi0"; }; sdhi1_pins: sd1 { - renesas,groups = "sdhi1_data4", "sdhi1_ctrl"; - renesas,function = "sdhi1"; + groups = "sdhi1_data4", "sdhi1_ctrl"; + function = "sdhi1"; }; sdhi2_pins: sd2 { - renesas,groups = "sdhi2_data4", "sdhi2_ctrl"; - renesas,function = "sdhi2"; + groups = "sdhi2_data4", "sdhi2_ctrl"; + function = "sdhi2"; }; qspi_pins: qspi { diff --git a/arch/arm/boot/dts/r8a7793.dtsi b/arch/arm/boot/dts/r8a7793.dtsi index 8d02aacf2892..629d3d60d1cd 100644 --- a/arch/arm/boot/dts/r8a7793.dtsi +++ b/arch/arm/boot/dts/r8a7793.dtsi @@ -666,7 +666,7 @@ scifb0: serial@e6c20000 { compatible = "renesas,scifb-r8a7793", "renesas,rcar-gen2-scifb", "renesas,scifb"; - reg = <0 0xe6c20000 0 64>; + reg = <0 0xe6c20000 0 0x100>; interrupts = <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>; clocks = <&mstp2_clks R8A7793_CLK_SCIFB0>; clock-names = "fck"; @@ -680,7 +680,7 @@ scifb1: serial@e6c30000 { compatible = "renesas,scifb-r8a7793", "renesas,rcar-gen2-scifb", "renesas,scifb"; - reg = <0 0xe6c30000 0 64>; + reg = <0 0xe6c30000 0 0x100>; interrupts = <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>; clocks = <&mstp2_clks R8A7793_CLK_SCIFB1>; clock-names = "fck"; @@ -694,7 +694,7 @@ scifb2: serial@e6ce0000 { compatible = "renesas,scifb-r8a7793", "renesas,rcar-gen2-scifb", "renesas,scifb"; - reg = <0 0xe6ce0000 0 64>; + reg = <0 0xe6ce0000 0 0x100>; interrupts = <GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH>; clocks = <&mstp2_clks R8A7793_CLK_SCIFB2>; clock-names = "fck"; @@ -852,6 +852,33 @@ status = "disabled"; }; + vin0: video@e6ef0000 { + compatible = "renesas,vin-r8a7793", "renesas,rcar-gen2-vin"; + reg = <0 0xe6ef0000 0 0x1000>; + interrupts = <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&mstp8_clks R8A7793_CLK_VIN0>; + power-domains = <&sysc R8A7793_PD_ALWAYS_ON>; + status = "disabled"; + }; + + vin1: video@e6ef1000 { + compatible = "renesas,vin-r8a7793", "renesas,rcar-gen2-vin"; + reg = <0 0xe6ef1000 0 0x1000>; + interrupts = <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&mstp8_clks R8A7793_CLK_VIN1>; + power-domains = <&sysc R8A7793_PD_ALWAYS_ON>; + status = "disabled"; + }; + + vin2: video@e6ef2000 { + compatible = "renesas,vin-r8a7793", "renesas,rcar-gen2-vin"; + reg = <0 0xe6ef2000 0 0x1000>; + interrupts = <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&mstp8_clks R8A7793_CLK_VIN2>; + power-domains = <&sysc R8A7793_PD_ALWAYS_ON>; + status = "disabled"; + }; + qspi: spi@e6b10000 { compatible = "renesas,qspi-r8a7793", "renesas,qspi"; reg = <0 0xe6b10000 0 0x2c>; diff --git a/arch/arm/boot/dts/r8a7794-alt.dts b/arch/arm/boot/dts/r8a7794-alt.dts index 8d1b35afaf82..325d3f972c57 100644 --- a/arch/arm/boot/dts/r8a7794-alt.dts +++ b/arch/arm/boot/dts/r8a7794-alt.dts @@ -207,11 +207,25 @@ sdhi0_pins: sd0 { groups = "sdhi0_data4", "sdhi0_ctrl"; function = "sdhi0"; + power-source = <3300>; + }; + + sdhi0_pins_uhs: sd0_uhs { + groups = "sdhi0_data4", "sdhi0_ctrl"; + function = "sdhi0"; + power-source = <1800>; }; sdhi1_pins: sd1 { groups = "sdhi1_data4", "sdhi1_ctrl"; function = "sdhi1"; + power-source = <3300>; + }; + + sdhi1_pins_uhs: sd1_uhs { + groups = "sdhi1_data4", "sdhi1_ctrl"; + function = "sdhi1"; + power-source = <1800>; }; }; @@ -255,23 +269,27 @@ &sdhi0 { pinctrl-0 = <&sdhi0_pins>; - pinctrl-names = "default"; + pinctrl-1 = <&sdhi0_pins_uhs>; + pinctrl-names = "default", "state_uhs"; vmmc-supply = <&vcc_sdhi0>; vqmmc-supply = <&vccq_sdhi0>; cd-gpios = <&gpio6 6 GPIO_ACTIVE_LOW>; wp-gpios = <&gpio6 7 GPIO_ACTIVE_LOW>; + sd-uhs-sdr50; status = "okay"; }; &sdhi1 { pinctrl-0 = <&sdhi1_pins>; - pinctrl-names = "default"; + pinctrl-1 = <&sdhi1_pins_uhs>; + pinctrl-names = "default", "state_uhs"; vmmc-supply = <&vcc_sdhi1>; vqmmc-supply = <&vccq_sdhi1>; cd-gpios = <&gpio6 14 GPIO_ACTIVE_LOW>; wp-gpios = <&gpio6 15 GPIO_ACTIVE_LOW>; + sd-uhs-sdr50; status = "okay"; }; diff --git a/arch/arm/boot/dts/r8a7794.dtsi b/arch/arm/boot/dts/r8a7794.dtsi index 9365580a194f..01816ac775a8 100644 --- a/arch/arm/boot/dts/r8a7794.dtsi +++ b/arch/arm/boot/dts/r8a7794.dtsi @@ -411,7 +411,7 @@ scifb0: serial@e6c20000 { compatible = "renesas,scifb-r8a7794", "renesas,rcar-gen2-scifb", "renesas,scifb"; - reg = <0 0xe6c20000 0 64>; + reg = <0 0xe6c20000 0 0x100>; interrupts = <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>; clocks = <&mstp2_clks R8A7794_CLK_SCIFB0>; clock-names = "fck"; @@ -425,7 +425,7 @@ scifb1: serial@e6c30000 { compatible = "renesas,scifb-r8a7794", "renesas,rcar-gen2-scifb", "renesas,scifb"; - reg = <0 0xe6c30000 0 64>; + reg = <0 0xe6c30000 0 0x100>; interrupts = <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>; clocks = <&mstp2_clks R8A7794_CLK_SCIFB1>; clock-names = "fck"; @@ -439,7 +439,7 @@ scifb2: serial@e6ce0000 { compatible = "renesas,scifb-r8a7794", "renesas,rcar-gen2-scifb", "renesas,scifb"; - reg = <0 0xe6ce0000 0 64>; + reg = <0 0xe6ce0000 0 0x100>; interrupts = <GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH>; clocks = <&mstp2_clks R8A7794_CLK_SCIFB2>; clock-names = "fck"; @@ -731,6 +731,7 @@ dmas = <&dmac0 0xcd>, <&dmac0 0xce>, <&dmac1 0xcd>, <&dmac1 0xce>; dma-names = "tx", "rx", "tx", "rx"; + max-frequency = <195000000>; power-domains = <&sysc R8A7794_PD_ALWAYS_ON>; status = "disabled"; }; @@ -743,6 +744,7 @@ dmas = <&dmac0 0xc1>, <&dmac0 0xc2>, <&dmac1 0xc1>, <&dmac1 0xc2>; dma-names = "tx", "rx", "tx", "rx"; + max-frequency = <97500000>; power-domains = <&sysc R8A7794_PD_ALWAYS_ON>; status = "disabled"; }; @@ -755,6 +757,7 @@ dmas = <&dmac0 0xd3>, <&dmac0 0xd4>, <&dmac1 0xd3>, <&dmac1 0xd4>; dma-names = "tx", "rx", "tx", "rx"; + max-frequency = <97500000>; power-domains = <&sysc R8A7794_PD_ALWAYS_ON>; status = "disabled"; }; @@ -1025,8 +1028,7 @@ clocks = <&extal_clk &usb_extal_clk>; #clock-cells = <1>; clock-output-names = "main", "pll0", "pll1", "pll3", - "lb", "qspi", "sdh", "sd0", "z", - "rcan"; + "lb", "qspi", "sdh", "sd0", "rcan"; #power-domain-cells = <0>; }; /* Variable factor clocks */ @@ -1488,62 +1490,62 @@ status = "disabled"; rcar_sound,dvc { - dvc0: dvc@0 { + dvc0: dvc-0 { dmas = <&audma0 0xbc>; dma-names = "tx"; }; - dvc1: dvc@1 { + dvc1: dvc-1 { dmas = <&audma0 0xbe>; dma-names = "tx"; }; }; rcar_sound,mix { - mix0: mix@0 { }; - mix1: mix@1 { }; + mix0: mix-0 { }; + mix1: mix-1 { }; }; rcar_sound,ctu { - ctu00: ctu@0 { }; - ctu01: ctu@1 { }; - ctu02: ctu@2 { }; - ctu03: ctu@3 { }; - ctu10: ctu@4 { }; - ctu11: ctu@5 { }; - ctu12: ctu@6 { }; - ctu13: ctu@7 { }; + ctu00: ctu-0 { }; + ctu01: ctu-1 { }; + ctu02: ctu-2 { }; + ctu03: ctu-3 { }; + ctu10: ctu-4 { }; + ctu11: ctu-5 { }; + ctu12: ctu-6 { }; + ctu13: ctu-7 { }; }; rcar_sound,src { - src@0 { + src-0 { status = "disabled"; }; - src1: src@1 { + src1: src-1 { interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>; dmas = <&audma0 0x87>, <&audma0 0x9c>; dma-names = "rx", "tx"; }; - src2: src@2 { + src2: src-2 { interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>; dmas = <&audma0 0x89>, <&audma0 0x9e>; dma-names = "rx", "tx"; }; - src3: src@3 { + src3: src-3 { interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>; dmas = <&audma0 0x8b>, <&audma0 0xa0>; dma-names = "rx", "tx"; }; - src4: src@4 { + src4: src-4 { interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>; dmas = <&audma0 0x8d>, <&audma0 0xb0>; dma-names = "rx", "tx"; }; - src5: src@5 { + src5: src-5 { interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>; dmas = <&audma0 0x8f>, <&audma0 0xb2>; dma-names = "rx", "tx"; }; - src6: src@6 { + src6: src-6 { interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>; dmas = <&audma0 0x91>, <&audma0 0xb4>; dma-names = "rx", "tx"; @@ -1551,61 +1553,61 @@ }; rcar_sound,ssi { - ssi0: ssi@0 { + ssi0: ssi-0 { interrupts = <GIC_SPI 370 IRQ_TYPE_LEVEL_HIGH>; dmas = <&audma0 0x01>, <&audma0 0x02>, <&audma0 0x15>, <&audma0 0x16>; dma-names = "rx", "tx", "rxu", "txu"; }; - ssi1: ssi@1 { + ssi1: ssi-1 { interrupts = <GIC_SPI 371 IRQ_TYPE_LEVEL_HIGH>; dmas = <&audma0 0x03>, <&audma0 0x04>, <&audma0 0x49>, <&audma0 0x4a>; dma-names = "rx", "tx", "rxu", "txu"; }; - ssi2: ssi@2 { + ssi2: ssi-2 { interrupts = <GIC_SPI 372 IRQ_TYPE_LEVEL_HIGH>; dmas = <&audma0 0x05>, <&audma0 0x06>, <&audma0 0x63>, <&audma0 0x64>; dma-names = "rx", "tx", "rxu", "txu"; }; - ssi3: ssi@3 { + ssi3: ssi-3 { interrupts = <GIC_SPI 373 IRQ_TYPE_LEVEL_HIGH>; dmas = <&audma0 0x07>, <&audma0 0x08>, <&audma0 0x6f>, <&audma0 0x70>; dma-names = "rx", "tx", "rxu", "txu"; }; - ssi4: ssi@4 { + ssi4: ssi-4 { interrupts = <GIC_SPI 374 IRQ_TYPE_LEVEL_HIGH>; dmas = <&audma0 0x09>, <&audma0 0x0a>, <&audma0 0x71>, <&audma0 0x72>; dma-names = "rx", "tx", "rxu", "txu"; }; - ssi5: ssi@5 { + ssi5: ssi-5 { interrupts = <GIC_SPI 375 IRQ_TYPE_LEVEL_HIGH>; dmas = <&audma0 0x0b>, <&audma0 0x0c>, <&audma0 0x73>, <&audma0 0x74>; dma-names = "rx", "tx", "rxu", "txu"; }; - ssi6: ssi@6 { + ssi6: ssi-6 { interrupts = <GIC_SPI 376 IRQ_TYPE_LEVEL_HIGH>; dmas = <&audma0 0x0d>, <&audma0 0x0e>, <&audma0 0x75>, <&audma0 0x76>; dma-names = "rx", "tx", "rxu", "txu"; }; - ssi7: ssi@7 { + ssi7: ssi-7 { interrupts = <GIC_SPI 377 IRQ_TYPE_LEVEL_HIGH>; dmas = <&audma0 0x0f>, <&audma0 0x10>, <&audma0 0x79>, <&audma0 0x7a>; dma-names = "rx", "tx", "rxu", "txu"; }; - ssi8: ssi@8 { + ssi8: ssi-8 { interrupts = <GIC_SPI 378 IRQ_TYPE_LEVEL_HIGH>; dmas = <&audma0 0x11>, <&audma0 0x12>, <&audma0 0x7b>, <&audma0 0x7c>; dma-names = "rx", "tx", "rxu", "txu"; }; - ssi9: ssi@9 { + ssi9: ssi-9 { interrupts = <GIC_SPI 379 IRQ_TYPE_LEVEL_HIGH>; dmas = <&audma0 0x13>, <&audma0 0x14>, <&audma0 0x7d>, <&audma0 0x7e>; diff --git a/arch/arm/boot/dts/rk3036-evb.dts b/arch/arm/boot/dts/rk3036-evb.dts index 8db9e9b197a2..2f5f15524fba 100644 --- a/arch/arm/boot/dts/rk3036-evb.dts +++ b/arch/arm/boot/dts/rk3036-evb.dts @@ -46,7 +46,7 @@ model = "Rockchip RK3036 Evaluation board"; compatible = "rockchip,rk3036-evb", "rockchip,rk3036"; - memory { + memory@60000000 { device_type = "memory"; reg = <0x60000000 0x40000000>; }; diff --git a/arch/arm/boot/dts/rk3036-kylin.dts b/arch/arm/boot/dts/rk3036-kylin.dts index 1df1557a46c3..3de958ec29c0 100644 --- a/arch/arm/boot/dts/rk3036-kylin.dts +++ b/arch/arm/boot/dts/rk3036-kylin.dts @@ -46,7 +46,7 @@ model = "Rockchip RK3036 KylinBoard"; compatible = "rockchip,rk3036-kylin", "rockchip,rk3036"; - memory { + memory@60000000 { device_type = "memory"; reg = <0x60000000 0x20000000>; }; diff --git a/arch/arm/boot/dts/rk3036.dtsi b/arch/arm/boot/dts/rk3036.dtsi index a935523a1eb8..3279c996a300 100644 --- a/arch/arm/boot/dts/rk3036.dtsi +++ b/arch/arm/boot/dts/rk3036.dtsi @@ -44,9 +44,11 @@ #include <dt-bindings/pinctrl/rockchip.h> #include <dt-bindings/clock/rk3036-cru.h> #include <dt-bindings/soc/rockchip,boot-mode.h> -#include "skeleton.dtsi" / { + #address-cells = <1>; + #size-cells = <1>; + compatible = "rockchip,rk3036"; interrupt-parent = <&gic>; @@ -244,7 +246,7 @@ compatible = "rockchip,rk3036-dw-mshc", "rockchip,rk3288-dw-mshc"; reg = <0x10214000 0x4000>; clock-frequency = <37500000>; - clock-freq-min-max = <400000 37500000>; + max-frequency = <37500000>; clocks = <&cru HCLK_SDMMC>, <&cru SCLK_SDMMC>; clock-names = "biu", "ciu"; fifo-depth = <0x100>; @@ -255,7 +257,7 @@ sdio: dwmmc@10218000 { compatible = "rockchip,rk3036-dw-mshc", "rockchip,rk3288-dw-mshc"; reg = <0x10218000 0x4000>; - clock-freq-min-max = <400000 37500000>; + max-frequency = <37500000>; clocks = <&cru HCLK_SDIO>, <&cru SCLK_SDIO>, <&cru SCLK_SDIO_DRV>, <&cru SCLK_SDIO_SAMPLE>; clock-names = "biu", "ciu", "ciu_drv", "ciu_sample"; @@ -271,7 +273,7 @@ bus-width = <8>; cap-mmc-highspeed; clock-frequency = <37500000>; - clock-freq-min-max = <400000 37500000>; + max-frequency = <37500000>; clocks = <&cru HCLK_EMMC>, <&cru SCLK_EMMC>, <&cru SCLK_EMMC_DRV>, <&cru SCLK_EMMC_SAMPLE>; clock-names = "biu", "ciu", "ciu_drv", "ciu_sample"; diff --git a/arch/arm/boot/dts/rk3066a-bqcurie2.dts b/arch/arm/boot/dts/rk3066a-bqcurie2.dts index bc674ee206ec..c0d8b5446ba7 100644 --- a/arch/arm/boot/dts/rk3066a-bqcurie2.dts +++ b/arch/arm/boot/dts/rk3066a-bqcurie2.dts @@ -49,7 +49,7 @@ model = "bq Curie 2"; compatible = "mundoreader,bq-curie2", "rockchip,rk3066a"; - memory { + memory@60000000 { device_type = "memory"; reg = <0x60000000 0x40000000>; }; diff --git a/arch/arm/boot/dts/rk3066a-marsboard.dts b/arch/arm/boot/dts/rk3066a-marsboard.dts index a2b763e949b4..0a54c4beff8d 100644 --- a/arch/arm/boot/dts/rk3066a-marsboard.dts +++ b/arch/arm/boot/dts/rk3066a-marsboard.dts @@ -47,7 +47,7 @@ model = "MarsBoard RK3066"; compatible = "haoyu,marsboard-rk3066", "rockchip,rk3066a"; - memory { + memory@60000000 { device_type = "memory"; reg = <0x60000000 0x40000000>; }; diff --git a/arch/arm/boot/dts/rk3066a-mk808.dts b/arch/arm/boot/dts/rk3066a-mk808.dts new file mode 100644 index 000000000000..658eb7ddeaf5 --- /dev/null +++ b/arch/arm/boot/dts/rk3066a-mk808.dts @@ -0,0 +1,195 @@ +/* + * Copyright (c) 2016 PaweÅ‚ Jarosz <paweljarosz3691@gmail.com> + * + * This file is dual-licensed: you can use it either under the terms + * of the GPL or the X11 license, at your option. Note that this dual + * licensing only applies to this file, and not this project as a + * whole. + * + * a) This file is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of the + * License, or (at your option) any later version. + * + * This file is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * Or, alternatively, + * + * b) Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, + * copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following + * conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + */ + +/dts-v1/; +#include "rk3066a.dtsi" + +/ { + model = "Rikomagic MK808"; + compatible = "rikomagic,mk808", "rockchip,rk3066a"; + + chosen { + stdout-path = "serial2:115200n8"; + }; + + memory@60000000 { + reg = <0x60000000 0x40000000>; + device_type = "memory"; + }; + + gpio-leds { + compatible = "gpio-leds"; + + blue { + label = "mk808:blue:power"; + gpios = <&gpio0 3 GPIO_ACTIVE_HIGH>; + default-state = "off"; + linux,default-trigger = "default-on"; + }; + }; + + vcc_io: vcc-io { + compatible = "regulator-fixed"; + regulator-name = "vcc_io"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + }; + + vcc_host: usb-host-regulator { + compatible = "regulator-fixed"; + enable-active-high; + gpio = <&gpio0 6 GPIO_ACTIVE_HIGH>; + pinctrl-0 = <&host_drv>; + pinctrl-names = "default"; + regulator-always-on; + regulator-name = "host-pwr"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + startup-delay-us = <100000>; + vin-supply = <&vcc_io>; + }; + + vcc_otg: usb-otg-regulator { + compatible = "regulator-fixed"; + enable-active-high; + gpio = <&gpio0 5 GPIO_ACTIVE_HIGH>; + pinctrl-0 = <&otg_drv>; + pinctrl-names = "default"; + regulator-always-on; + regulator-name = "vcc_otg"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + startup-delay-us = <100000>; + vin-supply = <&vcc_io>; + }; + + vcc_sd: sdmmc-regulator { + compatible = "regulator-fixed"; + gpio = <&gpio3 7 GPIO_ACTIVE_LOW>; + pinctrl-0 = <&sdmmc_pwr>; + pinctrl-names = "default"; + regulator-name = "vcc_sd"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + startup-delay-us = <100000>; + vin-supply = <&vcc_io>; + }; + + vcc_wifi: sdio-regulator { + compatible = "regulator-fixed"; + enable-active-high; + gpio = <&gpio3 24 GPIO_ACTIVE_HIGH>; + pinctrl-0 = <&wifi_pwr>; + pinctrl-names = "default"; + regulator-name = "vcc_wifi"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + startup-delay-us = <100000>; + vin-supply = <&vcc_io>; + }; +}; + +&mmc0 { + bus-width = <4>; + cap-mmc-highspeed; + cap-sd-highspeed; + num-slots = <1>; + vmmc-supply = <&vcc_sd>; + status = "okay"; +}; + +&mmc1 { + bus-width = <4>; + disable-wp; + non-removable; + num-slots = <1>; + pinctrl-0 = <&sd1_clk &sd1_cmd &sd1_bus4>; + pinctrl-names = "default"; + vmmc-supply = <&vcc_wifi>; + status = "okay"; +}; + +&pinctrl { + usb-host { + host_drv: host-drv { + rockchip,pins = <RK_GPIO0 6 RK_FUNC_GPIO &pcfg_pull_default>; + }; + }; + + usb-otg { + otg_drv: otg-drv { + rockchip,pins = <RK_GPIO0 5 RK_FUNC_GPIO &pcfg_pull_default>; + }; + }; + + sdmmc { + sdmmc_pwr: sdmmc-pwr { + rockchip,pins = <RK_GPIO3 7 RK_FUNC_GPIO &pcfg_pull_default>; + }; + }; + + sdio { + wifi_pwr: wifi-pwr { + rockchip,pins = <RK_GPIO3 24 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; +}; + +&uart2 { + status = "okay"; +}; + +&usb_host { + status = "okay"; +}; + +&usb_otg { + status = "okay"; +}; + +&usbphy { + status = "okay"; +}; + +&wdt { + status = "okay"; +}; diff --git a/arch/arm/boot/dts/rk3066a-rayeager.dts b/arch/arm/boot/dts/rk3066a-rayeager.dts index 6e7f2187a0e3..82465b644443 100644 --- a/arch/arm/boot/dts/rk3066a-rayeager.dts +++ b/arch/arm/boot/dts/rk3066a-rayeager.dts @@ -48,7 +48,7 @@ model = "Rayeager PX2"; compatible = "chipspark,rayeager-px2", "rockchip,rk3066a"; - memory { + memory@60000000 { device_type = "memory"; reg = <0x60000000 0x40000000>; }; diff --git a/arch/arm/boot/dts/rk3066a.dtsi b/arch/arm/boot/dts/rk3066a.dtsi index 0d0dae3a1694..fc8dcc72b16f 100644 --- a/arch/arm/boot/dts/rk3066a.dtsi +++ b/arch/arm/boot/dts/rk3066a.dtsi @@ -151,6 +151,14 @@ #clock-cells = <1>; #reset-cells = <1>; + assigned-clocks = <&cru PLL_CPLL>, <&cru PLL_GPLL>, + <&cru ACLK_CPU>, <&cru HCLK_CPU>, + <&cru PCLK_CPU>, <&cru ACLK_PERI>, + <&cru HCLK_PERI>, <&cru PCLK_PERI>; + assigned-clock-rates = <400000000>, <594000000>, + <300000000>, <150000000>, + <75000000>, <300000000>, + <150000000>, <75000000>; }; timer@2000e000 { @@ -162,7 +170,7 @@ }; efuse: efuse@20010000 { - compatible = "rockchip,rockchip-efuse"; + compatible = "rockchip,rk3066a-efuse"; reg = <0x20010000 0x4000>; #address-cells = <1>; #size-cells = <1>; @@ -628,6 +636,8 @@ }; &mmc0 { + clock-frequency = <50000000>; + max-frequency = <50000000>; pinctrl-names = "default"; pinctrl-0 = <&sd0_clk &sd0_cmd &sd0_cd &sd0_bus4>; }; diff --git a/arch/arm/boot/dts/rk3188-px3-evb.dts b/arch/arm/boot/dts/rk3188-px3-evb.dts new file mode 100644 index 000000000000..df727bafd6dc --- /dev/null +++ b/arch/arm/boot/dts/rk3188-px3-evb.dts @@ -0,0 +1,328 @@ +/* + * Copyright (c) 2016 Andy Yan <andy.yan@rock-chips.com> + * + * This file is dual-licensed: you can use it either under the terms + * of the GPL or the X11 license, at your option. Note that this dual + * licensing only applies to this file, and not this project as a + * whole. + * + * a) This file is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of the + * License, or (at your option) any later version. + * + * This file is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * Or, alternatively, + * + * b) Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, + * copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following + * conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + */ + +/dts-v1/; +#include <dt-bindings/input/input.h> +#include "rk3188.dtsi" + +/ { + model = "Rockchip PX3-EVB"; + compatible = "rockchip,px3-evb", "rockchip,px3", "rockchip,rk3188"; + + chosen { + stdout-path = "serial2:115200n8"; + }; + + memory@60000000 { + reg = <0x60000000 0x80000000>; + device_type = "memory"; + }; + + gpio-keys { + compatible = "gpio-keys"; + autorepeat; + + power { + gpios = <&gpio0 4 GPIO_ACTIVE_LOW>; + linux,code = <KEY_POWER>; + label = "GPIO Key Power"; + linux,input-type = <1>; + wakeup-source; + debounce-interval = <100>; + }; + }; + + vcc_sys: vsys-regulator { + compatible = "regulator-fixed"; + regulator-name = "vsys"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + regulator-boot-on; + }; +}; + +&cpu0 { + cpu0-supply = <&vdd_cpu>; +}; + +&emmc { + bus-width = <8>; + cap-mmc-highspeed; + disable-wp; + non-removable; + num-slots = <1>; + pinctrl-names = "default"; + pinctrl-0 = <&emmc_clk>, <&emmc_cmd>, <&emmc_rst>; + status = "okay"; +}; + +&i2c0 { + status = "okay"; + + accelerometer@18 { + compatible = "bosch,bma250"; + reg = <0x18>; + interrupt-parent = <&gpio0>; + interrupts = <15 IRQ_TYPE_LEVEL_LOW>; + }; +}; + +&i2c1 { + status = "okay"; + clock-frequency = <400000>; + + rk808: pmic@1c { + compatible = "rockchip,rk818"; + reg = <0x1c>; + interrupt-parent = <&gpio0>; + interrupts = <11 IRQ_TYPE_LEVEL_LOW>; + rockchip,system-power-controller; + wakeup-source; + #clock-cells = <1>; + clock-output-names = "xin32k", "rk808-clkout2"; + + vcc1-supply = <&vcc_sys>; + vcc2-supply = <&vcc_sys>; + vcc3-supply = <&vcc_sys>; + vcc4-supply = <&vcc_sys>; + vcc6-supply = <&vcc_sys>; + vcc7-supply = <&vcc_sys>; + vcc8-supply = <&vcc_io>; + vcc9-supply = <&vcc_io>; + + regulators { + vdd_cpu: DCDC_REG1 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <750000>; + regulator-max-microvolt = <1350000>; + regulator-name = "vdd_arm"; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdd_gpu: DCDC_REG2 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <850000>; + regulator-max-microvolt = <1250000>; + regulator-name = "vdd_gpu"; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <1000000>; + }; + }; + + vcc_ddr: DCDC_REG3 { + regulator-always-on; + regulator-boot-on; + regulator-name = "vcc_ddr"; + regulator-state-mem { + regulator-on-in-suspend; + }; + }; + + vcc_io: DCDC_REG4 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-name = "vcc_io"; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <3300000>; + }; + }; + + vcc_cif: LDO_REG1 { + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-name = "vcc_cif"; + }; + + vcc_jetta33: LDO_REG2 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-name = "vcc_jetta33"; + }; + + vdd_10: LDO_REG3 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <1000000>; + regulator-name = "vdd_10"; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <1000000>; + }; + }; + + lvds_12: LDO_REG4 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-name = "lvds_12"; + }; + + lvds_25: LDO_REG5 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + regulator-name = "lvds_25"; + }; + + cif_18: LDO_REG6 { + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <1000000>; + regulator-name = "cif_18"; + }; + + vcc_sd: LDO_REG7 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + regulator-name = "vcc_sd"; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <3300000>; + }; + }; + + wl_18: LDO_REG8 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + regulator-name = "wl_18"; + }; + + lcd_33: SWITCH_REG1 { + regulator-name = "lcd_33"; + }; + }; + }; + +}; + +&i2c2 { + gsl1680: touchscreen@40 { + compatible = "silead,gsl1680"; + reg = <0x40>; + interrupt-parent = <&gpio1>; + interrupts = <15 IRQ_TYPE_EDGE_FALLING>; + power-gpios = <&gpio0 14 GPIO_ACTIVE_HIGH>; + touchscreen-size-x = <800>; + touchscreen-size-y = <1280>; + silead,max-fingers = <5>; + }; +}; + +&mmc0 { + num-slots = <1>; + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&sd0_clk>, <&sd0_cmd>, <&sd0_cd>, <&sd0_bus4>; + vmmc-supply = <&vcc_sd>; + + bus-width = <4>; + cap-mmc-highspeed; + cap-sd-highspeed; + disable-wp; +}; + +&pinctrl { + pcfg_output_low: pcfg-output-low { + output-low; + }; + + usb { + host_vbus_drv: host-vbus-drv { + rockchip,pins = <0 3 RK_FUNC_GPIO &pcfg_pull_none>; + }; + otg_vbus_drv: otg-vbus-drv { + rockchip,pins = <2 31 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; +}; + +&pwm1 { + status = "okay"; +}; + +&pwm2 { + status = "okay"; +}; + +&pwm3 { + status = "okay"; +}; + +&uart0 { + status = "okay"; +}; + +&uart1 { + status = "okay"; +}; + +&uart2 { + status = "okay"; +}; + +&uart3 { + status = "okay"; +}; + +&usbphy { + status = "okay"; +}; + +&usb_host { + status = "okay"; +}; + +&usb_otg { + status = "okay"; +}; + +&wdt { + status = "okay"; +}; diff --git a/arch/arm/boot/dts/rk3188-radxarock.dts b/arch/arm/boot/dts/rk3188-radxarock.dts index 1da46d138029..5e8a235ed02d 100644 --- a/arch/arm/boot/dts/rk3188-radxarock.dts +++ b/arch/arm/boot/dts/rk3188-radxarock.dts @@ -48,7 +48,7 @@ model = "Radxa Rock"; compatible = "radxa,rock", "rockchip,rk3188"; - memory { + memory@60000000 { device_type = "memory"; reg = <0x60000000 0x80000000>; }; diff --git a/arch/arm/boot/dts/rk3188.dtsi b/arch/arm/boot/dts/rk3188.dtsi index 31f81b265cef..869e189331ec 100644 --- a/arch/arm/boot/dts/rk3188.dtsi +++ b/arch/arm/boot/dts/rk3188.dtsi @@ -147,7 +147,7 @@ }; efuse: efuse@20010000 { - compatible = "rockchip,rockchip-efuse"; + compatible = "rockchip,rk3188-efuse"; reg = <0x20010000 0x4000>; #address-cells = <1>; #size-cells = <1>; diff --git a/arch/arm/boot/dts/rk3228-evb.dts b/arch/arm/boot/dts/rk3228-evb.dts index 904668e2e666..58834330a5ba 100644 --- a/arch/arm/boot/dts/rk3228-evb.dts +++ b/arch/arm/boot/dts/rk3228-evb.dts @@ -46,7 +46,7 @@ model = "Rockchip RK3228 Evaluation board"; compatible = "rockchip,rk3228-evb", "rockchip,rk3228"; - memory { + memory@60000000 { device_type = "memory"; reg = <0x60000000 0x40000000>; }; diff --git a/arch/arm/boot/dts/rk3229-evb.dts b/arch/arm/boot/dts/rk3229-evb.dts index b6a12035a6bb..dcdd0cee619e 100644 --- a/arch/arm/boot/dts/rk3229-evb.dts +++ b/arch/arm/boot/dts/rk3229-evb.dts @@ -46,7 +46,7 @@ model = "Rockchip RK3229 Evaluation board"; compatible = "rockchip,rk3229-evb", "rockchip,rk3229"; - memory { + memory@60000000 { device_type = "memory"; reg = <0x60000000 0x40000000>; }; diff --git a/arch/arm/boot/dts/rk322x.dtsi b/arch/arm/boot/dts/rk322x.dtsi index 9e6bf0e311bb..9d3aee5abc15 100644 --- a/arch/arm/boot/dts/rk322x.dtsi +++ b/arch/arm/boot/dts/rk322x.dtsi @@ -44,9 +44,11 @@ #include <dt-bindings/pinctrl/rockchip.h> #include <dt-bindings/clock/rk3228-cru.h> #include <dt-bindings/thermal/thermal.h> -#include "skeleton.dtsi" / { + #address-cells = <1>; + #size-cells = <1>; + interrupt-parent = <&gic>; aliases { @@ -402,7 +404,7 @@ reg = <0x30020000 0x4000>; interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>; clock-frequency = <37500000>; - clock-freq-min-max = <400000 37500000>; + max-frequency = <37500000>; clocks = <&cru HCLK_EMMC>, <&cru SCLK_EMMC>, <&cru SCLK_EMMC_DRV>, <&cru SCLK_EMMC_SAMPLE>; clock-names = "biu", "ciu", "ciu_drv", "ciu_sample"; diff --git a/arch/arm/boot/dts/rk3288-evb.dtsi b/arch/arm/boot/dts/rk3288-evb.dtsi index d59208b5eb6c..bf7ccfad3260 100644 --- a/arch/arm/boot/dts/rk3288-evb.dtsi +++ b/arch/arm/boot/dts/rk3288-evb.dtsi @@ -43,7 +43,7 @@ #include "rk3288.dtsi" / { - memory { + memory@0 { device_type = "memory"; reg = <0x0 0x80000000>; }; diff --git a/arch/arm/boot/dts/rk3288-fennec.dts b/arch/arm/boot/dts/rk3288-fennec.dts index 2e3c34135ed8..805c0d26770b 100644 --- a/arch/arm/boot/dts/rk3288-fennec.dts +++ b/arch/arm/boot/dts/rk3288-fennec.dts @@ -46,7 +46,7 @@ model = "Rockchip RK3288 Fennec Board"; compatible = "rockchip,rk3288-fennec", "rockchip,rk3288"; - memory { + memory@0 { reg = <0x0 0x80000000>; device_type = "memory"; }; diff --git a/arch/arm/boot/dts/rk3288-firefly-reload-core.dtsi b/arch/arm/boot/dts/rk3288-firefly-reload-core.dtsi index ec418c99de95..d242588bae0d 100644 --- a/arch/arm/boot/dts/rk3288-firefly-reload-core.dtsi +++ b/arch/arm/boot/dts/rk3288-firefly-reload-core.dtsi @@ -45,7 +45,7 @@ #include "rk3288.dtsi" / { - memory { + memory@0 { device_type = "memory"; reg = <0 0x80000000>; }; diff --git a/arch/arm/boot/dts/rk3288-firefly.dtsi b/arch/arm/boot/dts/rk3288-firefly.dtsi index 114c90fb65e2..44935af1fb0e 100644 --- a/arch/arm/boot/dts/rk3288-firefly.dtsi +++ b/arch/arm/boot/dts/rk3288-firefly.dtsi @@ -44,7 +44,7 @@ #include "rk3288.dtsi" / { - memory { + memory@0 { device_type = "memory"; reg = <0 0x80000000>; }; diff --git a/arch/arm/boot/dts/rk3288-miqi.dts b/arch/arm/boot/dts/rk3288-miqi.dts index 24488421f0f0..441d450fd151 100644 --- a/arch/arm/boot/dts/rk3288-miqi.dts +++ b/arch/arm/boot/dts/rk3288-miqi.dts @@ -52,7 +52,7 @@ stdout-path = "serial2:115200n8"; }; - memory { + memory@0 { device_type = "memory"; reg = <0 0x80000000>; }; diff --git a/arch/arm/boot/dts/rk3288-popmetal.dts b/arch/arm/boot/dts/rk3288-popmetal.dts index 56dd377d5658..bc6d10054f6a 100644 --- a/arch/arm/boot/dts/rk3288-popmetal.dts +++ b/arch/arm/boot/dts/rk3288-popmetal.dts @@ -48,7 +48,7 @@ model = "PopMetal-RK3288"; compatible = "chipspark,popmetal-rk3288", "rockchip,rk3288"; - memory{ + memory@0 { device_type = "memory"; reg = <0 0x80000000>; }; @@ -68,7 +68,7 @@ pinctrl-0 = <&pwrbtn>; power { - gpios = <&gpio0 5 GPIO_ACTIVE_LOW>; + gpios = <&gpio0 RK_PA5 GPIO_ACTIVE_LOW>; linux,code = <KEY_POWER>; label = "GPIO Key Power"; linux,input-type = <1>; @@ -79,7 +79,7 @@ ir: ir-receiver { compatible = "gpio-ir-receiver"; - gpios = <&gpio0 6 GPIO_ACTIVE_LOW>; + gpios = <&gpio0 RK_PA6 GPIO_ACTIVE_LOW>; pinctrl-names = "default"; pinctrl-0 = <&ir_int>; }; @@ -94,7 +94,7 @@ vcc_sd: sdmmc-regulator { compatible = "regulator-fixed"; - gpio = <&gpio7 11 GPIO_ACTIVE_LOW>; + gpio = <&gpio7 RK_PB3 GPIO_ACTIVE_LOW>; pinctrl-names = "default"; pinctrl-0 = <&sdmmc_pwr>; regulator-name = "vcc_sd"; @@ -128,7 +128,7 @@ vcc28_dvp: vcc28-dvp-regulator { compatible = "regulator-fixed"; enable-active-high; - gpio = <&gpio0 17 GPIO_ACTIVE_HIGH>; + gpio = <&gpio0 RK_PC1 GPIO_ACTIVE_HIGH>; pinctrl-names = "default"; pinctrl-0 = <&dvp_pwr>; regulator-name = "vcc28_dvp"; @@ -147,6 +147,8 @@ bus-width = <8>; cap-mmc-highspeed; disable-wp; + mmc-ddr-1_8v; + mmc-hs200-1_8v; non-removable; num-slots = <1>; pinctrl-names = "default"; @@ -165,6 +167,10 @@ num-slots = <1>; pinctrl-names = "default"; pinctrl-0 = <&sdmmc_clk &sdmmc_cmd &sdmmc_cd &sdmmc_bus4>; + sd-uhs-sdr12; + sd-uhs-sdr25; + sd-uhs-sdr50; + sd-uhs-sdr104; vmmc-supply = <&vcc_sd>; vqmmc-supply = <&vccio_sd>; status = "okay"; @@ -174,7 +180,7 @@ phy-supply = <&vcc_lan>; phy-mode = "rgmii"; clock_in_out = "input"; - snps,reset-gpio = <&gpio4 7 0>; + snps,reset-gpio = <&gpio4 RK_PB0 0>; snps,reset-active-low; snps,reset-delays-us = <0 10000 1000000>; assigned-clocks = <&cru SCLK_MAC>; @@ -280,7 +286,7 @@ vccio_sd: LDO_REG2 { regulator-always-on; regulator-boot-on; - regulator-min-microvolt = <3300000>; + regulator-min-microvolt = <1800000>; regulator-max-microvolt = <3300000>; regulator-name = "vccio_sd"; regulator-state-mem { @@ -443,43 +449,43 @@ &pinctrl { ak8963 { comp_int: comp-int { - rockchip,pins = <8 1 RK_FUNC_GPIO &pcfg_pull_up>; + rockchip,pins = <8 RK_PA1 RK_FUNC_GPIO &pcfg_pull_up>; }; }; buttons { pwrbtn: pwrbtn { - rockchip,pins = <0 5 RK_FUNC_GPIO &pcfg_pull_up>; + rockchip,pins = <0 RK_PA5 RK_FUNC_GPIO &pcfg_pull_up>; }; }; dvp { dvp_pwr: dvp-pwr { - rockchip,pins = <0 17 RK_FUNC_GPIO &pcfg_pull_none>; + rockchip,pins = <0 RK_PC1 RK_FUNC_GPIO &pcfg_pull_none>; }; }; ir { ir_int: ir-int { - rockchip,pins = <0 6 RK_FUNC_GPIO &pcfg_pull_up>; + rockchip,pins = <0 RK_PA6 RK_FUNC_GPIO &pcfg_pull_up>; }; }; mma8452 { gsensor_int: gsensor-int { - rockchip,pins = <8 0 RK_FUNC_GPIO &pcfg_pull_up>; + rockchip,pins = <8 RK_PA0 RK_FUNC_GPIO &pcfg_pull_up>; }; }; pmic { pmic_int: pmic-int { - rockchip,pins = <RK_GPIO0 4 RK_FUNC_GPIO &pcfg_pull_up>; + rockchip,pins = <0 RK_PA4 RK_FUNC_GPIO &pcfg_pull_up>; }; }; sdmmc { sdmmc_pwr: sdmmc-pwr { - rockchip,pins = <7 11 RK_FUNC_GPIO &pcfg_pull_none>; + rockchip,pins = <7 RK_PB3 RK_FUNC_GPIO &pcfg_pull_none>; }; }; }; diff --git a/arch/arm/boot/dts/rk3288-r89.dts b/arch/arm/boot/dts/rk3288-r89.dts index 4b8a8adb243c..04faa72dbd95 100644 --- a/arch/arm/boot/dts/rk3288-r89.dts +++ b/arch/arm/boot/dts/rk3288-r89.dts @@ -48,7 +48,7 @@ / { compatible = "netxeon,r89", "rockchip,rk3288"; - memory { + memory@0 { device_type = "memory"; reg = <0x0 0x80000000>; }; diff --git a/arch/arm/boot/dts/rk3288-rock2-som.dtsi b/arch/arm/boot/dts/rk3288-rock2-som.dtsi index bb1f01e037ba..b25ba806d5ee 100644 --- a/arch/arm/boot/dts/rk3288-rock2-som.dtsi +++ b/arch/arm/boot/dts/rk3288-rock2-som.dtsi @@ -42,7 +42,7 @@ #include "rk3288.dtsi" / { - memory { + memory@0 { reg = <0x0 0x80000000>; device_type = "memory"; }; diff --git a/arch/arm/boot/dts/rk3288-veyron.dtsi b/arch/arm/boot/dts/rk3288-veyron.dtsi index 3dd2cca48c11..2251d28e9d2a 100644 --- a/arch/arm/boot/dts/rk3288-veyron.dtsi +++ b/arch/arm/boot/dts/rk3288-veyron.dtsi @@ -47,7 +47,7 @@ #include "rk3288.dtsi" / { - memory { + memory@0 { device_type = "memory"; reg = <0x0 0x80000000>; }; diff --git a/arch/arm/boot/dts/rk3288.dtsi b/arch/arm/boot/dts/rk3288.dtsi index 17ec2e2d7a60..73590e47f4fb 100644 --- a/arch/arm/boot/dts/rk3288.dtsi +++ b/arch/arm/boot/dts/rk3288.dtsi @@ -46,9 +46,11 @@ #include <dt-bindings/thermal/thermal.h> #include <dt-bindings/power/rk3288-power.h> #include <dt-bindings/soc/rockchip,boot-mode.h> -#include "skeleton.dtsi" / { + #address-cells = <1>; + #size-cells = <1>; + compatible = "rockchip,rk3288"; interrupt-parent = <&gic>; @@ -227,7 +229,7 @@ sdmmc: dwmmc@ff0c0000 { compatible = "rockchip,rk3288-dw-mshc"; - clock-freq-min-max = <400000 150000000>; + max-frequency = <150000000>; clocks = <&cru HCLK_SDMMC>, <&cru SCLK_SDMMC>, <&cru SCLK_SDMMC_DRV>, <&cru SCLK_SDMMC_SAMPLE>; clock-names = "biu", "ciu", "ciu-drive", "ciu-sample"; @@ -239,7 +241,7 @@ sdio0: dwmmc@ff0d0000 { compatible = "rockchip,rk3288-dw-mshc"; - clock-freq-min-max = <400000 150000000>; + max-frequency = <150000000>; clocks = <&cru HCLK_SDIO0>, <&cru SCLK_SDIO0>, <&cru SCLK_SDIO0_DRV>, <&cru SCLK_SDIO0_SAMPLE>; clock-names = "biu", "ciu", "ciu-drive", "ciu-sample"; @@ -251,7 +253,7 @@ sdio1: dwmmc@ff0e0000 { compatible = "rockchip,rk3288-dw-mshc"; - clock-freq-min-max = <400000 150000000>; + max-frequency = <150000000>; clocks = <&cru HCLK_SDIO1>, <&cru SCLK_SDIO1>, <&cru SCLK_SDIO1_DRV>, <&cru SCLK_SDIO1_SAMPLE>; clock-names = "biu", "ciu", "ciu-drive", "ciu-sample"; @@ -263,7 +265,7 @@ emmc: dwmmc@ff0f0000 { compatible = "rockchip,rk3288-dw-mshc"; - clock-freq-min-max = <400000 150000000>; + max-frequency = <150000000>; clocks = <&cru HCLK_EMMC>, <&cru SCLK_EMMC>, <&cru SCLK_EMMC_DRV>, <&cru SCLK_EMMC_SAMPLE>; clock-names = "biu", "ciu", "ciu-drive", "ciu-sample"; @@ -1116,7 +1118,7 @@ }; efuse: efuse@ffb40000 { - compatible = "rockchip,rockchip-efuse"; + compatible = "rockchip,rk3288-efuse"; reg = <0xffb40000 0x20>; #address-cells = <1>; #size-cells = <1>; diff --git a/arch/arm/boot/dts/rk3xxx.dtsi b/arch/arm/boot/dts/rk3xxx.dtsi index e15beb3c671e..0394312f392d 100644 --- a/arch/arm/boot/dts/rk3xxx.dtsi +++ b/arch/arm/boot/dts/rk3xxx.dtsi @@ -44,9 +44,11 @@ #include <dt-bindings/interrupt-controller/irq.h> #include <dt-bindings/interrupt-controller/arm-gic.h> #include <dt-bindings/soc/rockchip,boot-mode.h> -#include "skeleton.dtsi" / { + #address-cells = <1>; + #size-cells = <1>; + interrupt-parent = <&gic>; aliases { diff --git a/arch/arm/boot/dts/sama5d2.dtsi b/arch/arm/boot/dts/sama5d2.dtsi index 7173ec9059a1..ceb9783ff7e1 100644 --- a/arch/arm/boot/dts/sama5d2.dtsi +++ b/arch/arm/boot/dts/sama5d2.dtsi @@ -735,6 +735,11 @@ atmel,clk-output-range = <0 83000000>; }; + securam_clk: securam_clk { + #clock-cells = <0>; + reg = <51>; + }; + i2s0_clk: i2s0_clk { #clock-cells = <0>; reg = <54>; @@ -1030,6 +1035,7 @@ #address-cells = <1>; #size-cells = <0>; clocks = <&twi0_clk>; + atmel,fifo-size = <16>; status = "disabled"; }; @@ -1058,6 +1064,15 @@ status = "disabled"; }; + securam: sram@f8044000 { + compatible = "atmel,sama5d2-securam", "mmio-sram"; + reg = <0xf8044000 0x1420>; + clocks = <&securam_clk>; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0xf8044000 0x1420>; + }; + rstc@f8048000 { compatible = "atmel,sama5d3-rstc"; reg = <0xf8048000 0x10>; @@ -1088,30 +1103,12 @@ status = "disabled"; }; - sckc@f8048050 { - compatible = "atmel,at91sam9x5-sckc"; + clk32k: sckc@f8048050 { + compatible = "atmel,sama5d4-sckc"; reg = <0xf8048050 0x4>; - slow_rc_osc: slow_rc_osc { - compatible = "atmel,at91sam9x5-clk-slow-rc-osc"; - #clock-cells = <0>; - clock-frequency = <32768>; - clock-accuracy = <250000000>; - atmel,startup-time-usec = <75>; - }; - - slow_osc: slow_osc { - compatible = "atmel,at91sam9x5-clk-slow-osc"; - #clock-cells = <0>; - clocks = <&slow_xtal>; - atmel,startup-time-usec = <1200000>; - }; - - clk32k: slowck { - compatible = "atmel,at91sam9x5-clk-slow"; - #clock-cells = <0>; - clocks = <&slow_rc_osc &slow_osc>; - }; + clocks = <&slow_xtal>; + #clock-cells = <0>; }; rtc@f80480b0 { @@ -1231,6 +1228,7 @@ #address-cells = <1>; #size-cells = <0>; clocks = <&twi1_clk>; + atmel,fifo-size = <16>; status = "disabled"; }; @@ -1260,6 +1258,11 @@ clocks = <&pioA_clk>; }; + secumod@fc040000 { + compatible = "atmel,sama5d2-secumod", "syscon"; + reg = <0xfc040000 0x100>; + }; + tdes@fc044000 { compatible = "atmel,at91sam9g46-tdes"; reg = <0xfc044000 0x100>; diff --git a/arch/arm/boot/dts/sama5d3.dtsi b/arch/arm/boot/dts/sama5d3.dtsi index 4c84d333fc7e..b06448ba6649 100644 --- a/arch/arm/boot/dts/sama5d3.dtsi +++ b/arch/arm/boot/dts/sama5d3.dtsi @@ -549,8 +549,8 @@ dbgu { pinctrl_dbgu: dbgu-0 { atmel,pins = - <AT91_PIOB 30 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB30 periph A */ - AT91_PIOB 31 AT91_PERIPH_A AT91_PINCTRL_PULL_UP>; /* PB31 periph A with pullup */ + <AT91_PIOB 30 AT91_PERIPH_A AT91_PINCTRL_PULL_UP + AT91_PIOB 31 AT91_PERIPH_A AT91_PINCTRL_NONE>; }; }; diff --git a/arch/arm/boot/dts/sama5d4.dtsi b/arch/arm/boot/dts/sama5d4.dtsi index 65e725fb5679..4f60c1b7b137 100644 --- a/arch/arm/boot/dts/sama5d4.dtsi +++ b/arch/arm/boot/dts/sama5d4.dtsi @@ -1314,30 +1314,11 @@ status = "disabled"; }; - sckc@fc068650 { - compatible = "atmel,at91sam9x5-sckc"; + clk32k: sckc@fc068650 { + compatible = "atmel,sama5d4-sckc"; reg = <0xfc068650 0x4>; - - slow_rc_osc: slow_rc_osc { - compatible = "atmel,at91sam9x5-clk-slow-rc-osc"; - #clock-cells = <0>; - clock-frequency = <32768>; - clock-accuracy = <250000000>; - atmel,startup-time-usec = <75>; - }; - - slow_osc: slow_osc { - compatible = "atmel,at91sam9x5-clk-slow-osc"; - #clock-cells = <0>; - clocks = <&slow_xtal>; - atmel,startup-time-usec = <1200000>; - }; - - clk32k: slowck { - compatible = "atmel,at91sam9x5-clk-slow"; - #clock-cells = <0>; - clocks = <&slow_rc_osc &slow_osc>; - }; + #clock-cells = <0>; + clocks = <&slow_xtal>; }; rtc@fc0686b0 { @@ -1461,8 +1442,8 @@ dbgu { pinctrl_dbgu: dbgu-0 { atmel,pins = - <AT91_PIOB 24 AT91_PERIPH_A AT91_PINCTRL_NONE>, /* conflicts with D14 and TDI */ - <AT91_PIOB 25 AT91_PERIPH_A AT91_PINCTRL_PULL_UP>; /* conflicts with D15 and TDO */ + <AT91_PIOB 24 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* conflicts with D14 and TDI */ + AT91_PIOB 25 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* conflicts with D15 and TDO */ }; }; diff --git a/arch/arm/boot/dts/sh73a0.dtsi b/arch/arm/boot/dts/sh73a0.dtsi index 032fe2f14b16..e1267590b575 100644 --- a/arch/arm/boot/dts/sh73a0.dtsi +++ b/arch/arm/boot/dts/sh73a0.dtsi @@ -8,8 +8,6 @@ * kind, whether express or implied. */ -/include/ "skeleton.dtsi" - #include <dt-bindings/clock/sh73a0-clock.h> #include <dt-bindings/interrupt-controller/arm-gic.h> #include <dt-bindings/interrupt-controller/irq.h> @@ -17,6 +15,8 @@ / { compatible = "renesas,sh73a0"; interrupt-parent = <&gic>; + #address-cells = <1>; + #size-cells = <1>; cpus { #address-cells = <1>; diff --git a/arch/arm/boot/dts/socfpga.dtsi b/arch/arm/boot/dts/socfpga.dtsi index 9f48141270b8..27c1d46127cf 100644 --- a/arch/arm/boot/dts/socfpga.dtsi +++ b/arch/arm/boot/dts/socfpga.dtsi @@ -686,6 +686,7 @@ arm,data-latency = <2 1 1>; prefetch-data = <1>; prefetch-instr = <1>; + arm,shared-override; }; mmc: dwmmc0@ff704000 { @@ -700,11 +701,38 @@ status = "disabled"; }; + nand0: nand@ff900000 { + #address-cells = <0x1>; + #size-cells = <0x1>; + compatible = "denali,denali-nand-dt"; + reg = <0xff900000 0x100000>, + <0xffb80000 0x10000>; + reg-names = "nand_data", "denali_reg"; + interrupts = <0x0 0x90 0x4>; + dma-mask = <0xffffffff>; + clocks = <&nand_clk>; + status = "disabled"; + }; + ocram: sram@ffff0000 { compatible = "mmio-sram"; reg = <0xffff0000 0x10000>; }; + qspi: spi@ff705000 { + compatible = "cdns,qspi-nor"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0xff705000 0x1000>, + <0xffa00000 0x1000>; + interrupts = <0 151 4>; + cdns,fifo-depth = <128>; + cdns,fifo-width = <4>; + cdns,trigger-address = <0x00000000>; + clocks = <&qspi_clk>; + status = "disabled"; + }; + rst: rstmgr@ffd05000 { #reset-cells = <1>; compatible = "altr,rst-mgr"; diff --git a/arch/arm/boot/dts/socfpga_arria10.dtsi b/arch/arm/boot/dts/socfpga_arria10.dtsi index f520cbff5e1c..551c636a4f01 100644 --- a/arch/arm/boot/dts/socfpga_arria10.dtsi +++ b/arch/arm/boot/dts/socfpga_arria10.dtsi @@ -562,6 +562,21 @@ status = "disabled"; }; + spi1: spi@ffda5000 { + compatible = "snps,dw-apb-ssi"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0xffda5000 0x100>; + interrupts = <0 102 4>; + num-chipselect = <4>; + bus-num = <0>; + /*32bit_access;*/ + tx-dma-channel = <&pdma 16>; + rx-dma-channel = <&pdma 17>; + clocks = <&spi_m_clk>; + status = "disabled"; + }; + sdr: sdr@ffc25000 { compatible = "syscon"; reg = <0xffcfb100 0x80>; @@ -573,6 +588,9 @@ interrupts = <0 18 IRQ_TYPE_LEVEL_HIGH>; cache-unified; cache-level = <2>; + prefetch-data = <1>; + prefetch-instr = <1>; + arm,shared-override; }; mmc: dwmmc0@ff808000 { @@ -657,6 +675,20 @@ }; }; + qspi: spi@ff809000 { + compatible = "cdns,qspi-nor"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0xff809000 0x100>, + <0xffa00000 0x100000>; + interrupts = <0 100 IRQ_TYPE_LEVEL_HIGH>; + cdns,fifo-depth = <128>; + cdns,fifo-width = <4>; + cdns,trigger-address = <0x00000000>; + clocks = <&qspi_clk>; + status = "disabled"; + }; + rst: rstmgr@ffd05000 { #reset-cells = <1>; compatible = "altr,rst-mgr"; diff --git a/arch/arm/boot/dts/socfpga_arria10_socdk.dtsi b/arch/arm/boot/dts/socfpga_arria10_socdk.dtsi index 8e3a4adc389f..eb00ae37f316 100644 --- a/arch/arm/boot/dts/socfpga_arria10_socdk.dtsi +++ b/arch/arm/boot/dts/socfpga_arria10_socdk.dtsi @@ -36,6 +36,30 @@ reg = <0x0 0x40000000>; /* 1GB */ }; + a10leds { + compatible = "gpio-leds"; + + a10sr_led0 { + label = "a10sr-led0"; + gpios = <&a10sr_gpio 0 1>; + }; + + a10sr_led1 { + label = "a10sr-led1"; + gpios = <&a10sr_gpio 1 1>; + }; + + a10sr_led2 { + label = "a10sr-led2"; + gpios = <&a10sr_gpio 2 1>; + }; + + a10sr_led3 { + label = "a10sr-led3"; + gpios = <&a10sr_gpio 3 1>; + }; + }; + soc { clkmgr@ffd04000 { clocks { @@ -75,6 +99,31 @@ status = "okay"; }; +&gpio1 { + status = "okay"; +}; + +&spi1 { + status = "okay"; + + resource-manager@0 { + compatible = "altr,a10sr"; + reg = <0>; + spi-max-frequency = <100000>; + /* low-level active IRQ at GPIO1_5 */ + interrupt-parent = <&portb>; + interrupts = <5 IRQ_TYPE_LEVEL_LOW>; + interrupt-controller; + #interrupt-cells = <2>; + + a10sr_gpio: gpio-controller { + compatible = "altr,a10sr-gpio"; + gpio-controller; + #gpio-cells = <2>; + }; + }; +}; + &i2c1 { speed-mode = <0>; status = "okay"; diff --git a/arch/arm/boot/dts/socfpga_arria10_socdk_qspi.dts b/arch/arm/boot/dts/socfpga_arria10_socdk_qspi.dts new file mode 100644 index 000000000000..beb2fc6b9eb6 --- /dev/null +++ b/arch/arm/boot/dts/socfpga_arria10_socdk_qspi.dts @@ -0,0 +1,49 @@ +/* + * Copyright (C) 2016 Intel. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License along with + * this program. If not, see <http://www.gnu.org/licenses/>. + */ + +/dts-v1/; +#include "socfpga_arria10_socdk.dtsi" + +&qspi { + status = "okay"; + + flash0: n25q00@0 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "n25q00aa"; + reg = <0>; + spi-max-frequency = <100000000>; + + m25p,fast-read; + cdns,page-size = <256>; + cdns,block-size = <16>; + cdns,read-delay = <4>; + cdns,tshsl-ns = <50>; + cdns,tsd2d-ns = <50>; + cdns,tchsh-ns = <4>; + cdns,tslch-ns = <4>; + + partition@qspi-boot { + label = "Boot and fpga data"; + reg = <0x0 0x2720000>; + }; + + partition@qspi-rootfs { + label = "Root Filesystem - JFFS2"; + reg = <0x2720000 0x58E0000>; + }; + }; +}; diff --git a/arch/arm/boot/dts/socfpga_arria5_socdk.dts b/arch/arm/boot/dts/socfpga_arria5_socdk.dts index 3c8867862b0d..f739ead074a2 100644 --- a/arch/arm/boot/dts/socfpga_arria5_socdk.dts +++ b/arch/arm/boot/dts/socfpga_arria5_socdk.dts @@ -82,6 +82,39 @@ status = "okay"; }; +&qspi { + status = "okay"; + + flash: flash@0 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "n25q256a"; + reg = <0>; + spi-max-frequency = <100000000>; + + m25p,fast-read; + cdns,page-size = <256>; + cdns,block-size = <16>; + cdns,read-delay = <4>; + cdns,tshsl-ns = <50>; + cdns,tsd2d-ns = <50>; + cdns,tchsh-ns = <4>; + cdns,tslch-ns = <4>; + + partition@qspi-boot { + /* 8MB for raw data. */ + label = "Flash 0 Raw Data"; + reg = <0x0 0x800000>; + }; + + partition@qspi-rootfs { + /* 120MB for jffs2 data. */ + label = "Flash 0 jffs2 Filesystem"; + reg = <0x800000 0x7800000>; + }; + }; +}; + &usb1 { status = "okay"; }; diff --git a/arch/arm/boot/dts/socfpga_cyclone5_de0_sockit.dts b/arch/arm/boot/dts/socfpga_cyclone5_de0_sockit.dts index afea3645ada4..5ecd2ef405e3 100644 --- a/arch/arm/boot/dts/socfpga_cyclone5_de0_sockit.dts +++ b/arch/arm/boot/dts/socfpga_cyclone5_de0_sockit.dts @@ -18,7 +18,7 @@ / { model = "Terasic DE-0(Atlas)"; - compatible = "altr,socfpga-cyclone5", "altr,socfpga"; + compatible = "terasic,de0-atlas", "altr,socfpga-cyclone5", "altr,socfpga"; chosen { bootargs = "earlyprintk"; diff --git a/arch/arm/boot/dts/socfpga_cyclone5_mcv.dtsi b/arch/arm/boot/dts/socfpga_cyclone5_mcv.dtsi index f86f9c060d7a..6ad3b1eb9b86 100644 --- a/arch/arm/boot/dts/socfpga_cyclone5_mcv.dtsi +++ b/arch/arm/boot/dts/socfpga_cyclone5_mcv.dtsi @@ -18,7 +18,7 @@ #include "socfpga_cyclone5.dtsi" / { - model = "DENX MCV"; + model = "Aries/DENX MCV"; compatible = "altr,socfpga-cyclone5", "altr,socfpga"; memory { diff --git a/arch/arm/boot/dts/socfpga_cyclone5_mcvevk.dts b/arch/arm/boot/dts/socfpga_cyclone5_mcvevk.dts index 7186a29b8b86..e5a98e5696ca 100644 --- a/arch/arm/boot/dts/socfpga_cyclone5_mcvevk.dts +++ b/arch/arm/boot/dts/socfpga_cyclone5_mcvevk.dts @@ -18,8 +18,8 @@ #include "socfpga_cyclone5_mcv.dtsi" / { - model = "DENX MCV EVK"; - compatible = "altr,socfpga-cyclone5", "altr,socfpga"; + model = "Aries/DENX MCV EVK"; + compatible = "denx,mcvevk", "altr,socfpga-cyclone5", "altr,socfpga"; aliases { ethernet0 = &gmac0; diff --git a/arch/arm/boot/dts/socfpga_cyclone5_socdk.dts b/arch/arm/boot/dts/socfpga_cyclone5_socdk.dts index 15e43f43f244..6306d008f01b 100644 --- a/arch/arm/boot/dts/socfpga_cyclone5_socdk.dts +++ b/arch/arm/boot/dts/socfpga_cyclone5_socdk.dts @@ -19,7 +19,7 @@ / { model = "Altera SOCFPGA Cyclone V SoC Development Kit"; - compatible = "altr,socfpga-cyclone5", "altr,socfpga"; + compatible = "altr,socfpga-cyclone5-socdk", "altr,socfpga-cyclone5", "altr,socfpga"; chosen { bootargs = "earlyprintk"; @@ -87,6 +87,39 @@ status = "okay"; }; +&qspi { + status = "okay"; + + flash0: n25q00@0 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "n25q00"; + reg = <0>; /* chip select */ + spi-max-frequency = <100000000>; + + m25p,fast-read; + cdns,page-size = <256>; + cdns,block-size = <16>; + cdns,read-delay = <4>; + cdns,tshsl-ns = <50>; + cdns,tsd2d-ns = <50>; + cdns,tchsh-ns = <4>; + cdns,tslch-ns = <4>; + + partition@qspi-boot { + /* 8MB for raw data. */ + label = "Flash 0 Raw Data"; + reg = <0x0 0x800000>; + }; + + partition@qspi-rootfs { + /* 120MB for jffs2 data. */ + label = "Flash 0 jffs2 Filesystem"; + reg = <0x800000 0x7800000>; + }; + }; +}; + &usb1 { status = "okay"; }; diff --git a/arch/arm/boot/dts/socfpga_cyclone5_sockit.dts b/arch/arm/boot/dts/socfpga_cyclone5_sockit.dts index 02e22f554ef0..a0c90b3bdfd1 100644 --- a/arch/arm/boot/dts/socfpga_cyclone5_sockit.dts +++ b/arch/arm/boot/dts/socfpga_cyclone5_sockit.dts @@ -19,7 +19,7 @@ / { model = "Terasic SoCkit"; - compatible = "altr,socfpga-cyclone5", "altr,socfpga"; + compatible = "terasic,socfpga-cyclone5-sockit", "altr,socfpga-cyclone5", "altr,socfpga"; chosen { bootargs = "earlyprintk"; @@ -175,6 +175,27 @@ status = "okay"; }; +&qspi { + status = "okay"; + + flash: flash@0 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "n25q00"; + reg = <0>; + spi-max-frequency = <100000000>; + + m25p,fast-read; + cdns,page-size = <256>; + cdns,block-size = <16>; + cdns,read-delay = <4>; + cdns,tshsl-ns = <50>; + cdns,tsd2d-ns = <50>; + cdns,tchsh-ns = <4>; + cdns,tslch-ns = <4>; + }; +}; + &usb1 { status = "okay"; }; diff --git a/arch/arm/boot/dts/socfpga_cyclone5_socrates.dts b/arch/arm/boot/dts/socfpga_cyclone5_socrates.dts index d79853775061..c3d52f27b21e 100644 --- a/arch/arm/boot/dts/socfpga_cyclone5_socrates.dts +++ b/arch/arm/boot/dts/socfpga_cyclone5_socrates.dts @@ -80,3 +80,22 @@ &mmc { status = "okay"; }; + +&qspi { + status = "okay"; + + flash: flash@0 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "n25q256a"; + reg = <0>; + spi-max-frequency = <100000000>; + m25p,fast-read; + cdns,read-delay = <4>; + cdns,tshsl-ns = <50>; + cdns,tsd2d-ns = <50>; + cdns,tchsh-ns = <4>; + cdns,tslch-ns = <4>; + status = "okay"; + }; +}; diff --git a/arch/arm/boot/dts/socfpga_cyclone5_sodia.dts b/arch/arm/boot/dts/socfpga_cyclone5_sodia.dts new file mode 100644 index 000000000000..5b7e3c27e6e9 --- /dev/null +++ b/arch/arm/boot/dts/socfpga_cyclone5_sodia.dts @@ -0,0 +1,123 @@ +/* + * Copyright (C) 2016 Nobuhiro Iwamatsu <iwamatsu@nigauri.org> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see <http://www.gnu.org/licenses/>. + */ + +#include "socfpga_cyclone5.dtsi" +#include <dt-bindings/gpio/gpio.h> +#include <dt-bindings/input/input.h> + +/ { + model = "Altera SOCFPGA Cyclone V SoC Macnica Sodia board"; + compatible = "macnica,sodia", "altr,socfpga-cyclone5", "altr,socfpga"; + + chosen { + bootargs = "earlyprintk"; + stdout-path = "serial0:115200n8"; + }; + + memory { + name = "memory"; + device_type = "memory"; + reg = <0x0 0x40000000>; + }; + + aliases { + ethernet0 = &gmac1; + }; + + regulator_3_3v: 3-3-v-regulator { + compatible = "regulator-fixed"; + regulator-name = "3.3V"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + }; + + leds: gpio-leds { + compatible = "gpio-leds"; + + hps_led0 { + label = "hps:green:led0"; + gpios = <&portb 12 GPIO_ACTIVE_LOW>; + }; + + hps_led1 { + label = "hps:green:led1"; + gpios = <&portb 13 GPIO_ACTIVE_LOW>; + }; + + hps_led2 { + label = "hps:green:led2"; + gpios = <&portb 14 GPIO_ACTIVE_LOW>; + }; + + hps_led3 { + label = "hps:green:led3"; + gpios = <&portb 15 GPIO_ACTIVE_LOW>; + }; + }; +}; + +&gmac1 { + status = "okay"; + phy-mode = "rgmii"; + phy = <&phy0>; + + mdio0 { + #address-cells = <1>; + #size-cells = <0>; + phy0: ethernet-phy@0 { + reg = <0>; + rxd0-skew-ps = <0>; + rxd1-skew-ps = <0>; + rxd2-skew-ps = <0>; + rxd3-skew-ps = <0>; + rxdv-skew-ps = <0>; + rxc-skew-ps = <3000>; + txen-skew-ps = <0>; + txc-skew-ps = <3000>; + }; + }; +}; + +&gpio1 { + status = "okay"; +}; + +&i2c0 { + status = "okay"; + + eeprom@51 { + compatible = "atmel,24c32"; + reg = <0x51>; + pagesize = <32>; + }; + + rtc@68 { + compatible = "dallas,ds1339"; + reg = <0x68>; + }; +}; + +&mmc0 { + cd-gpios = <&portb 18 0>; + vmmc-supply = <®ulator_3_3v>; + vqmmc-supply = <®ulator_3_3v>; + status = "okay"; +}; + +&usb1 { + status = "okay"; +}; diff --git a/arch/arm/boot/dts/socfpga_cyclone5_vining_fpga.dts b/arch/arm/boot/dts/socfpga_cyclone5_vining_fpga.dts index b844473601d2..363ee62457fe 100644 --- a/arch/arm/boot/dts/socfpga_cyclone5_vining_fpga.dts +++ b/arch/arm/boot/dts/socfpga_cyclone5_vining_fpga.dts @@ -51,7 +51,7 @@ / { model = "samtec VIN|ING FPGA"; - compatible = "altr,socfpga-cyclone5", "altr,socfpga"; + compatible = "samtec,vining", "altr,socfpga-cyclone5", "altr,socfpga"; chosen { bootargs = "console=ttyS0,115200"; diff --git a/arch/arm/boot/dts/ste-snowball.dts b/arch/arm/boot/dts/ste-snowball.dts index b3df1c60d465..386eee6de232 100644 --- a/arch/arm/boot/dts/ste-snowball.dts +++ b/arch/arm/boot/dts/ste-snowball.dts @@ -239,14 +239,25 @@ arm,primecell-periphid = <0x10480180>; max-frequency = <100000000>; bus-width = <4>; + cap-sd-highspeed; cap-mmc-highspeed; + sd-uhs-sdr12; + sd-uhs-sdr25; + /* All direction control is used */ + st,sig-dir-cmd; + st,sig-dir-dat0; + st,sig-dir-dat2; + st,sig-dir-dat31; + st,sig-pin-fbclk; + full-pwr-cycle; vmmc-supply = <&ab8500_ldo_aux3_reg>; vqmmc-supply = <&vmmci>; pinctrl-names = "default", "sleep"; pinctrl-0 = <&sdi0_default_mode>; pinctrl-1 = <&sdi0_sleep_mode>; - cd-gpios = <&gpio6 26 GPIO_ACTIVE_LOW>; // 218 + /* GPIO218 MMC_CD */ + cd-gpios = <&gpio6 26 GPIO_ACTIVE_LOW>; status = "okay"; }; @@ -549,7 +560,7 @@ /* VMMCI level-shifter enable */ snowball_cfg3 { pins = "GPIO217_AH12"; - ste,config = <&gpio_out_lo>; + ste,config = <&gpio_out_hi>; }; /* VMMCI level-shifter voltage select */ snowball_cfg4 { diff --git a/arch/arm/boot/dts/stih407-clock.dtsi b/arch/arm/boot/dts/stih407-clock.dtsi index 13029c03d7c6..34c119a66f14 100644 --- a/arch/arm/boot/dts/stih407-clock.dtsi +++ b/arch/arm/boot/dts/stih407-clock.dtsi @@ -101,6 +101,7 @@ clocks = <&clk_sysin>; clock-output-names = "clk-s-a0-pll-ofd-0"; + clock-critical = <0>; /* clk-s-a0-pll-ofd-0 */ }; clk_s_a0_flexgen: clk-s-a0-flexgen { @@ -112,6 +113,7 @@ <&clk_sysin>; clock-output-names = "clk-ic-lmi0"; + clock-critical = <CLK_IC_LMI0>; }; }; @@ -126,6 +128,7 @@ "clk-s-c0-fs0-ch1", "clk-s-c0-fs0-ch2", "clk-s-c0-fs0-ch3"; + clock-critical = <0>; /* clk-s-c0-fs0-ch0 */ }; clk_s_c0: clockgen-c@09103000 { @@ -139,6 +142,7 @@ clocks = <&clk_sysin>; clock-output-names = "clk-s-c0-pll0-odf-0"; + clock-critical = <0>; /* clk-s-c0-pll0-odf-0 */ }; clk_s_c0_pll1: clk-s-c0-pll1 { @@ -194,6 +198,12 @@ "clk-main-disp", "clk-aux-disp", "clk-compo-dvp"; + clock-critical = <CLK_PROC_STFE>, + <CLK_ICN_CPU>, + <CLK_TX_ICN_DMU>, + <CLK_EXT2F_A9>, + <CLK_ICN_LMI>, + <CLK_ICN_SBC>; }; }; diff --git a/arch/arm/boot/dts/stih407-family.dtsi b/arch/arm/boot/dts/stih407-family.dtsi index 91096a49efa9..d29960b6c47b 100644 --- a/arch/arm/boot/dts/stih407-family.dtsi +++ b/arch/arm/boot/dts/stih407-family.dtsi @@ -900,7 +900,7 @@ }; sti_uni_player0: sti-uni-player@8d80000 { - compatible = "st,sti-uni-player"; + compatible = "st,stih407-uni-player-hdmi"; #sound-dai-cells = <0>; st,syscfg = <&syscfg_core>; clocks = <&clk_s_d0_flexgen CLK_PCM_0>; @@ -910,17 +910,13 @@ reg = <0x8d80000 0x158>; interrupts = <GIC_SPI 84 IRQ_TYPE_NONE>; dmas = <&fdma0 2 0 1>; - dai-name = "Uni Player #0 (HDMI)"; dma-names = "tx"; - st,uniperiph-id = <0>; - st,version = <5>; - st,mode = "HDMI"; status = "disabled"; }; sti_uni_player1: sti-uni-player@8d81000 { - compatible = "st,sti-uni-player"; + compatible = "st,stih407-uni-player-pcm-out"; #sound-dai-cells = <0>; st,syscfg = <&syscfg_core>; clocks = <&clk_s_d0_flexgen CLK_PCM_1>; @@ -930,17 +926,13 @@ reg = <0x8d81000 0x158>; interrupts = <GIC_SPI 85 IRQ_TYPE_NONE>; dmas = <&fdma0 3 0 1>; - dai-name = "Uni Player #1 (PIO)"; dma-names = "tx"; - st,uniperiph-id = <1>; - st,version = <5>; - st,mode = "PCM"; status = "disabled"; }; sti_uni_player2: sti-uni-player@8d82000 { - compatible = "st,sti-uni-player"; + compatible = "st,stih407-uni-player-dac"; #sound-dai-cells = <0>; st,syscfg = <&syscfg_core>; clocks = <&clk_s_d0_flexgen CLK_PCM_2>; @@ -950,17 +942,13 @@ reg = <0x8d82000 0x158>; interrupts = <GIC_SPI 86 IRQ_TYPE_NONE>; dmas = <&fdma0 4 0 1>; - dai-name = "Uni Player #1 (DAC)"; dma-names = "tx"; - st,uniperiph-id = <2>; - st,version = <5>; - st,mode = "PCM"; status = "disabled"; }; sti_uni_player3: sti-uni-player@8d85000 { - compatible = "st,sti-uni-player"; + compatible = "st,stih407-uni-player-spdif"; #sound-dai-cells = <0>; st,syscfg = <&syscfg_core>; clocks = <&clk_s_d0_flexgen CLK_SPDIFF>; @@ -971,38 +959,30 @@ interrupts = <GIC_SPI 89 IRQ_TYPE_NONE>; dmas = <&fdma0 7 0 1>; dma-names = "tx"; - dai-name = "Uni Player #1 (PIO)"; - st,uniperiph-id = <3>; - st,version = <5>; - st,mode = "SPDIF"; status = "disabled"; }; sti_uni_reader0: sti-uni-reader@8d83000 { - compatible = "st,sti-uni-reader"; + compatible = "st,stih407-uni-reader-pcm_in"; #sound-dai-cells = <0>; st,syscfg = <&syscfg_core>; reg = <0x8d83000 0x158>; interrupts = <GIC_SPI 87 IRQ_TYPE_NONE>; dmas = <&fdma0 5 0 1>; dma-names = "rx"; - dai-name = "Uni Reader #0 (PCM IN)"; - st,version = <3>; status = "disabled"; }; sti_uni_reader1: sti-uni-reader@8d84000 { - compatible = "st,sti-uni-reader"; + compatible = "st,stih407-uni-reader-hdmi"; #sound-dai-cells = <0>; st,syscfg = <&syscfg_core>; reg = <0x8d84000 0x158>; interrupts = <GIC_SPI 88 IRQ_TYPE_NONE>; dmas = <&fdma0 6 0 1>; dma-names = "rx"; - dai-name = "Uni Reader #1 (HDMI RX)"; - st,version = <3>; status = "disabled"; }; diff --git a/arch/arm/boot/dts/stih407-pinctrl.dtsi b/arch/arm/boot/dts/stih407-pinctrl.dtsi index c325cc059ae4..daab16b5ae64 100644 --- a/arch/arm/boot/dts/stih407-pinctrl.dtsi +++ b/arch/arm/boot/dts/stih407-pinctrl.dtsi @@ -1157,7 +1157,7 @@ reg = <0x0923f080 0x4>; reg-names = "irqmux"; interrupts = <GIC_SPI 192 IRQ_TYPE_NONE>; - interrupts-names = "irqmux"; + interrupt-names = "irqmux"; ranges = <0 0x09230000 0x3000>; pio40: gpio@09230000 { diff --git a/arch/arm/boot/dts/stih407.dtsi b/arch/arm/boot/dts/stih407.dtsi index 291ffacbd2e0..fa149837df14 100644 --- a/arch/arm/boot/dts/stih407.dtsi +++ b/arch/arm/boot/dts/stih407.dtsi @@ -102,7 +102,7 @@ <&clk_s_d2_quadfs 0>; }; - sti-hdmi@8d04000 { + sti_hdmi: sti-hdmi@8d04000 { compatible = "st,stih407-hdmi"; reg = <0x8d04000 0x1000>; reg-names = "hdmi-reg"; diff --git a/arch/arm/boot/dts/stih410-b2260.dts b/arch/arm/boot/dts/stih410-b2260.dts index ef2ff2f518f6..d50242eabae8 100644 --- a/arch/arm/boot/dts/stih410-b2260.dts +++ b/arch/arm/boot/dts/stih410-b2260.dts @@ -165,6 +165,9 @@ status = "okay"; }; + sti_uni_player0: sti-uni-player@8d80000 { + status = "okay"; + }; /* SSC11 to HDMI */ hdmiddc: i2c@9541000 { /* HDMI V1.3a supports Standard mode only */ @@ -174,9 +177,22 @@ status = "okay"; }; - sti-display-subsystem { - sti_hdmi: sti-hdmi@8d04000 { - status = "okay"; + sound { + compatible = "simple-audio-card"; + simple-audio-card,name = "STI-B2260"; + status = "okay"; + + simple-audio-card,dai-link@0 { + /* DAC */ + format = "i2s"; + mclk-fs = <128>; + cpu { + sound-dai = <&sti_uni_player0>; + }; + + codec { + sound-dai = <&sti_hdmi>; + }; }; }; diff --git a/arch/arm/boot/dts/stih410-clock.dtsi b/arch/arm/boot/dts/stih410-clock.dtsi index 8598effd6c01..07c8ef9d77f6 100644 --- a/arch/arm/boot/dts/stih410-clock.dtsi +++ b/arch/arm/boot/dts/stih410-clock.dtsi @@ -208,7 +208,8 @@ "clk-clust-hades", "clk-hwpe-hades", "clk-fc-hades"; - clock-critical = <CLK_ICN_CPU>, + clock-critical = <CLK_PROC_STFE>, + <CLK_ICN_CPU>, <CLK_TX_ICN_DMU>, <CLK_EXT2F_A9>, <CLK_ICN_LMI>, diff --git a/arch/arm/boot/dts/stih410.dtsi b/arch/arm/boot/dts/stih410.dtsi index a3ef7341c051..281a12424cf6 100644 --- a/arch/arm/boot/dts/stih410.dtsi +++ b/arch/arm/boot/dts/stih410.dtsi @@ -193,7 +193,7 @@ <&clk_s_d2_quadfs 0>; }; - sti-hdmi@8d04000 { + sti_hdmi: sti-hdmi@8d04000 { compatible = "st,stih407-hdmi"; reg = <0x8d04000 0x1000>; reg-names = "hdmi-reg"; diff --git a/arch/arm/boot/dts/stih415-b2000.dts b/arch/arm/boot/dts/stih415-b2000.dts deleted file mode 100644 index bdfbd3765db2..000000000000 --- a/arch/arm/boot/dts/stih415-b2000.dts +++ /dev/null @@ -1,15 +0,0 @@ -/* - * Copyright (C) 2013 STMicroelectronics (R&D) Limited. - * Author: Srinivas Kandagatla <srinivas.kandagatla@st.com> - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * publishhed by the Free Software Foundation. - */ -/dts-v1/; -#include "stih415.dtsi" -#include "stih41x-b2000.dtsi" -/ { - model = "STiH415 B2000 Board"; - compatible = "st,stih415-b2000", "st,stih415"; -}; diff --git a/arch/arm/boot/dts/stih415-b2020.dts b/arch/arm/boot/dts/stih415-b2020.dts deleted file mode 100644 index 71903a87bd31..000000000000 --- a/arch/arm/boot/dts/stih415-b2020.dts +++ /dev/null @@ -1,15 +0,0 @@ -/* - * Copyright (C) 2013 STMicroelectronics (R&D) Limited. - * Author: Srinivas Kandagatla <srinivas.kandagatla@st.com> - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * publishhed by the Free Software Foundation. - */ -/dts-v1/; -#include "stih415.dtsi" -#include "stih41x-b2020.dtsi" -/ { - model = "STiH415 B2020 Board"; - compatible = "st,stih415-b2020", "st,stih415"; -}; diff --git a/arch/arm/boot/dts/stih415-clock.dtsi b/arch/arm/boot/dts/stih415-clock.dtsi deleted file mode 100644 index 3ee34514bc4b..000000000000 --- a/arch/arm/boot/dts/stih415-clock.dtsi +++ /dev/null @@ -1,533 +0,0 @@ -/* - * Copyright (C) 2013 STMicroelectronics (R&D) Limited - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - */ - -#include <dt-bindings/clock/stih415-clks.h> - -/ { - clocks { - #address-cells = <1>; - #size-cells = <1>; - ranges; - - /* - * Fixed 30MHz oscillator input to SoC - */ - clk_sysin: clk-sysin { - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-frequency = <30000000>; - }; - - /* - * ClockGenAs on SASG1 - */ - clockgen-a@fee62000 { - reg = <0xfee62000 0xb48>; - - clk_s_a0_pll: clk-s-a0-pll { - #clock-cells = <1>; - compatible = "st,clkgena-plls-c65"; - - clocks = <&clk_sysin>; - - clock-output-names = "clk-s-a0-pll0-hs", - "clk-s-a0-pll0-ls", - "clk-s-a0-pll1"; - }; - - clk_s_a0_osc_prediv: clk-s-a0-osc-prediv { - #clock-cells = <0>; - compatible = "st,clkgena-prediv-c65", - "st,clkgena-prediv"; - - clocks = <&clk_sysin>; - - clock-output-names = "clk-s-a0-osc-prediv"; - }; - - clk_s_a0_hs: clk-s-a0-hs { - #clock-cells = <1>; - compatible = "st,clkgena-divmux-c65-hs", - "st,clkgena-divmux"; - - clocks = <&clk_s_a0_osc_prediv>, - <&clk_s_a0_pll 0>, /* PLL0 HS */ - <&clk_s_a0_pll 2>; /* PLL1 */ - - clock-output-names = "clk-s-fdma-0", - "clk-s-fdma-1", - ""; /* clk-s-jit-sense */ - /* Fourth output unused */ - }; - - clk_s_a0_ls: clk-s-a0-ls { - #clock-cells = <1>; - compatible = "st,clkgena-divmux-c65-ls", - "st,clkgena-divmux"; - - clocks = <&clk_s_a0_osc_prediv>, - <&clk_s_a0_pll 1>, /* PLL0 LS */ - <&clk_s_a0_pll 2>; /* PLL1 */ - - clock-output-names = "clk-s-icn-reg-0", - "clk-s-icn-if-0", - "clk-s-icn-reg-lp-0", - "clk-s-emiss", - "clk-s-eth1-phy", - "clk-s-mii-ref-out"; - /* Remaining outputs unused */ - }; - }; - - clockgen-a@fee81000 { - reg = <0xfee81000 0xb48>; - - clk_s_a1_pll: clk-s-a1-pll { - #clock-cells = <1>; - compatible = "st,clkgena-plls-c65"; - - clocks = <&clk_sysin>; - - clock-output-names = "clk-s-a1-pll0-hs", - "clk-s-a1-pll0-ls", - "clk-s-a1-pll1"; - }; - - clk_s_a1_osc_prediv: clk-s-a1-osc-prediv { - #clock-cells = <0>; - compatible = "st,clkgena-prediv-c65", - "st,clkgena-prediv"; - - clocks = <&clk_sysin>; - - clock-output-names = "clk-s-a1-osc-prediv"; - }; - - clk_s_a1_hs: clk-s-a1-hs { - #clock-cells = <1>; - compatible = "st,clkgena-divmux-c65-hs", - "st,clkgena-divmux"; - - clocks = <&clk_s_a1_osc_prediv>, - <&clk_s_a1_pll 0>, /* PLL0 HS */ - <&clk_s_a1_pll 2>; /* PLL1 */ - - clock-output-names = "", /* Reserved */ - "", /* Reserved */ - "clk-s-stac-phy", - "clk-s-vtac-tx-phy"; - }; - - clk_s_a1_ls: clk-s-a1-ls { - #clock-cells = <1>; - compatible = "st,clkgena-divmux-c65-ls", - "st,clkgena-divmux"; - - clocks = <&clk_s_a1_osc_prediv>, - <&clk_s_a1_pll 1>, /* PLL0 LS */ - <&clk_s_a1_pll 2>; /* PLL1 */ - - clock-output-names = "clk-s-icn-if-2", - "clk-s-card-mmc", - "clk-s-icn-if-1", - "clk-s-gmac0-phy", - "clk-s-nand-ctrl", - "", /* Reserved */ - "clk-s-mii0-ref-out", - ""; /* clk-s-stac-sys */ - /* Remaining outputs unused */ - }; - }; - - /* - * ClockGenAs on MPE41 - */ - clockgen-a@fde12000 { - reg = <0xfde12000 0xb50>; - - clk_m_a0_pll0: clk-m-a0-pll0 { - #clock-cells = <1>; - compatible = "st,plls-c32-a1x-0", "st,clkgen-plls-c32"; - - clocks = <&clk_sysin>; - - clock-output-names = "clk-m-a0-pll0-phi0", - "clk-m-a0-pll0-phi1", - "clk-m-a0-pll0-phi2", - "clk-m-a0-pll0-phi3"; - }; - - clk_m_a0_pll1: clk-m-a0-pll1 { - #clock-cells = <1>; - compatible = "st,plls-c32-a1x-1", "st,clkgen-plls-c32"; - - clocks = <&clk_sysin>; - - clock-output-names = "clk-m-a0-pll1-phi0", - "clk-m-a0-pll1-phi1", - "clk-m-a0-pll1-phi2", - "clk-m-a0-pll1-phi3"; - }; - - clk_m_a0_osc_prediv: clk-m-a0-osc-prediv { - #clock-cells = <0>; - compatible = "st,clkgena-prediv-c32", - "st,clkgena-prediv"; - - clocks = <&clk_sysin>; - - clock-output-names = "clk-m-a0-osc-prediv"; - }; - - clk_m_a0_div0: clk-m-a0-div0 { - #clock-cells = <1>; - compatible = "st,clkgena-divmux-c32-odf0", - "st,clkgena-divmux"; - - clocks = <&clk_m_a0_osc_prediv>, - <&clk_m_a0_pll0 0>, /* PLL0 PHI0 */ - <&clk_m_a0_pll1 0>; /* PLL1 PHI0 */ - - clock-output-names = "clk-m-apb-pm", /* Unused */ - "", /* Unused */ - "", /* Unused */ - "", /* Unused */ - "clk-m-pp-dmu-0", - "clk-m-pp-dmu-1", - "clk-m-icm-disp", - ""; /* Unused */ - }; - - clk_m_a0_div1: clk-m-a0-div1 { - #clock-cells = <1>; - compatible = "st,clkgena-divmux-c32-odf1", - "st,clkgena-divmux"; - - clocks = <&clk_m_a0_osc_prediv>, - <&clk_m_a0_pll0 1>, /* PLL0 PHI1 */ - <&clk_m_a0_pll1 1>; /* PLL1 PHI1 */ - - clock-output-names = "", /* Unused */ - "", /* Unused */ - "clk-m-a9-ext2f", - "clk-m-st40rt", - "clk-m-st231-dmu-0", - "clk-m-st231-dmu-1", - "clk-m-st231-aud", - "clk-m-st231-gp-0"; - }; - - clk_m_a0_div2: clk-m-a0-div2 { - #clock-cells = <1>; - compatible = "st,clkgena-divmux-c32-odf2", - "st,clkgena-divmux"; - - clocks = <&clk_m_a0_osc_prediv>, - <&clk_m_a0_pll0 2>, /* PLL0 PHI2 */ - <&clk_m_a0_pll1 2>; /* PLL1 PHI2 */ - - clock-output-names = "clk-m-st231-gp-1", - "clk-m-icn-cpu", - "clk-m-icn-stac", - "clk-m-icn-dmu-0", - "clk-m-icn-dmu-1", - "", /* Unused */ - "", /* Unused */ - ""; /* Unused */ - }; - - clk_m_a0_div3: clk-m-a0-div3 { - #clock-cells = <1>; - compatible = "st,clkgena-divmux-c32-odf3", - "st,clkgena-divmux"; - - clocks = <&clk_m_a0_osc_prediv>, - <&clk_m_a0_pll0 3>, /* PLL0 PHI3 */ - <&clk_m_a0_pll1 3>; /* PLL1 PHI3 */ - - clock-output-names = "", /* Unused */ - "", /* Unused */ - "", /* Unused */ - "", /* Unused */ - "", /* Unused */ - "", /* Unused */ - "clk-m-icn-eram", - "clk-m-a9-trace"; - }; - }; - - clockgen-a@fd6db000 { - reg = <0xfd6db000 0xb50>; - - clk_m_a1_pll0: clk-m-a1-pll0 { - #clock-cells = <1>; - compatible = "st,plls-c32-a1x-0", "st,clkgen-plls-c32"; - - clocks = <&clk_sysin>; - - clock-output-names = "clk-m-a1-pll0-phi0", - "clk-m-a1-pll0-phi1", - "clk-m-a1-pll0-phi2", - "clk-m-a1-pll0-phi3"; - }; - - clk_m_a1_pll1: clk-m-a1-pll1 { - #clock-cells = <1>; - compatible = "st,plls-c32-a1x-1", "st,clkgen-plls-c32"; - - clocks = <&clk_sysin>; - - clock-output-names = "clk-m-a1-pll1-phi0", - "clk-m-a1-pll1-phi1", - "clk-m-a1-pll1-phi2", - "clk-m-a1-pll1-phi3"; - }; - - clk_m_a1_osc_prediv: clk-m-a1-osc-prediv { - #clock-cells = <0>; - compatible = "st,clkgena-prediv-c32", - "st,clkgena-prediv"; - - clocks = <&clk_sysin>; - - clock-output-names = "clk-m-a1-osc-prediv"; - }; - - clk_m_a1_div0: clk-m-a1-div0 { - #clock-cells = <1>; - compatible = "st,clkgena-divmux-c32-odf0", - "st,clkgena-divmux"; - - clocks = <&clk_m_a1_osc_prediv>, - <&clk_m_a1_pll0 0>, /* PLL0 PHI0 */ - <&clk_m_a1_pll1 0>; /* PLL1 PHI0 */ - - clock-output-names = "clk-m-fdma-12", - "clk-m-fdma-10", - "clk-m-fdma-11", - "clk-m-hva-lmi", - "clk-m-proc-sc", - "clk-m-tp", - "clk-m-icn-gpu", - "clk-m-icn-vdp-0"; - }; - - clk_m_a1_div1: clk-m-a1-div1 { - #clock-cells = <1>; - compatible = "st,clkgena-divmux-c32-odf1", - "st,clkgena-divmux"; - - clocks = <&clk_m_a1_osc_prediv>, - <&clk_m_a1_pll0 1>, /* PLL0 PHI1 */ - <&clk_m_a1_pll1 1>; /* PLL1 PHI1 */ - - clock-output-names = "clk-m-icn-vdp-1", - "clk-m-icn-vdp-2", - "clk-m-icn-vdp-3", - "clk-m-prv-t1-bus", - "clk-m-icn-vdp-4", - "clk-m-icn-reg-10", - "", /* Unused */ - ""; /* clk-m-icn-st231 */ - }; - - clk_m_a1_div2: clk-m-a1-div2 { - #clock-cells = <1>; - compatible = "st,clkgena-divmux-c32-odf2", - "st,clkgena-divmux"; - - clocks = <&clk_m_a1_osc_prediv>, - <&clk_m_a1_pll0 2>, /* PLL0 PHI2 */ - <&clk_m_a1_pll1 2>; /* PLL1 PHI2 */ - - clock-output-names = "clk-m-fvdp-proc-alt", - "", /* Unused */ - "", /* Unused */ - "", /* Unused */ - "", /* Unused */ - "", /* Unused */ - "", /* Unused */ - ""; /* Unused */ - }; - - clk_m_a1_div3: clk-m-a1-div3 { - #clock-cells = <1>; - compatible = "st,clkgena-divmux-c32-odf3", - "st,clkgena-divmux"; - - clocks = <&clk_m_a1_osc_prediv>, - <&clk_m_a1_pll0 3>, /* PLL0 PHI3 */ - <&clk_m_a1_pll1 3>; /* PLL1 PHI3 */ - - clock-output-names = "", /* Unused */ - "", /* Unused */ - "", /* Unused */ - "", /* Unused */ - "", /* Unused */ - "", /* Unused */ - "", /* Unused */ - ""; /* Unused */ - }; - }; - - clk_m_a9_ext2f_div2: clk-m-a9-ext2f-div2 { - #clock-cells = <0>; - compatible = "fixed-factor-clock"; - clocks = <&clk_m_a0_div1 2>; - clock-div = <2>; - clock-mult = <1>; - }; - - clockgen-a@fd345000 { - reg = <0xfd345000 0xb50>; - - clk_m_a2_pll0: clk-m-a2-pll0 { - #clock-cells = <1>; - compatible = "st,plls-c32-a1x-0", "st,clkgen-plls-c32"; - - clocks = <&clk_sysin>; - - clock-output-names = "clk-m-a2-pll0-phi0", - "clk-m-a2-pll0-phi1", - "clk-m-a2-pll0-phi2", - "clk-m-a2-pll0-phi3"; - }; - - clk_m_a2_pll1: clk-m-a2-pll1 { - #clock-cells = <1>; - compatible = "st,plls-c32-a1x-1", "st,clkgen-plls-c32"; - - clocks = <&clk_sysin>; - - clock-output-names = "clk-m-a2-pll1-phi0", - "clk-m-a2-pll1-phi1", - "clk-m-a2-pll1-phi2", - "clk-m-a2-pll1-phi3"; - }; - - clk_m_a2_osc_prediv: clk-m-a2-osc-prediv { - #clock-cells = <0>; - compatible = "st,clkgena-prediv-c32", - "st,clkgena-prediv"; - - clocks = <&clk_sysin>; - - clock-output-names = "clk-m-a2-osc-prediv"; - }; - - clk_m_a2_div0: clk-m-a2-div0 { - #clock-cells = <1>; - compatible = "st,clkgena-divmux-c32-odf0", - "st,clkgena-divmux"; - - clocks = <&clk_m_a2_osc_prediv>, - <&clk_m_a2_pll0 0>, /* PLL0 PHI0 */ - <&clk_m_a2_pll1 0>; /* PLL1 PHI0 */ - - clock-output-names = "clk-m-vtac-main-phy", - "clk-m-vtac-aux-phy", - "clk-m-stac-phy", - "clk-m-stac-sys", - "", /* clk-m-mpestac-pg */ - "", /* clk-m-mpestac-wc */ - "", /* clk-m-mpevtacaux-pg*/ - ""; /* clk-m-mpevtacmain-pg*/ - }; - - clk_m_a2_div1: clk-m-a2-div1 { - #clock-cells = <1>; - compatible = "st,clkgena-divmux-c32-odf1", - "st,clkgena-divmux"; - - clocks = <&clk_m_a2_osc_prediv>, - <&clk_m_a2_pll0 1>, /* PLL0 PHI1 */ - <&clk_m_a2_pll1 1>; /* PLL1 PHI1 */ - - clock-output-names = "", /* clk-m-mpevtacrx0-wc */ - "", /* clk-m-mpevtacrx1-wc */ - "clk-m-compo-main", - "clk-m-compo-aux", - "clk-m-bdisp-0", - "clk-m-bdisp-1", - "clk-m-icn-bdisp-0", - "clk-m-icn-bdisp-1"; - }; - - clk_m_a2_div2: clk-m-a2-div2 { - #clock-cells = <1>; - compatible = "st,clkgena-divmux-c32-odf2", - "st,clkgena-divmux"; - - clocks = <&clk_m_a2_osc_prediv>, - <&clk_m_a2_pll0 2>, /* PLL0 PHI2 */ - <&clk_m_a2_pll1 2>; /* PLL1 PHI2 */ - - clock-output-names = "", /* clk-m-icn-hqvdp0 */ - "", /* clk-m-icn-hqvdp1 */ - "clk-m-icn-compo", - "", /* clk-m-icn-vdpaux */ - "clk-m-icn-ts", - "clk-m-icn-reg-lp-10", - "clk-m-dcephy-impctrl", - ""; /* Unused */ - }; - - clk_m_a2_div3: clk-m-a2-div3 { - #clock-cells = <1>; - compatible = "st,clkgena-divmux-c32-odf3", - "st,clkgena-divmux"; - - clocks = <&clk_m_a2_osc_prediv>, - <&clk_m_a2_pll0 3>, /* PLL0 PHI3 */ - <&clk_m_a2_pll1 3>; /* PLL1 PHI3 */ - - clock-output-names = ""; /* Unused */ - /* Remaining outputs unused */ - }; - }; - - /* - * A9 PLL - */ - clockgen-a9@fdde00d8 { - reg = <0xfdde00d8 0x70>; - - clockgen_a9_pll: clockgen-a9-pll { - #clock-cells = <1>; - compatible = "st,stih415-plls-c32-a9", "st,clkgen-plls-c32"; - - clocks = <&clk_sysin>; - clock-output-names = "clockgen-a9-pll-odf"; - }; - }; - - /* - * ARM CPU related clocks - */ - clk_m_a9: clk-m-a9@fdde00d8 { - #clock-cells = <0>; - compatible = "st,stih415-clkgen-a9-mux", "st,clkgen-mux"; - reg = <0xfdde00d8 0x4>; - clocks = <&clockgen_a9_pll 0>, - <&clockgen_a9_pll 0>, - <&clk_m_a0_div1 2>, - <&clk_m_a9_ext2f_div2>; - }; - - /* - * ARM Peripheral clock for timers - */ - arm_periph_clk: clk-m-a9-periphs { - #clock-cells = <0>; - compatible = "fixed-factor-clock"; - clocks = <&clk_m_a9>; - clock-div = <2>; - clock-mult = <1>; - }; - }; -}; diff --git a/arch/arm/boot/dts/stih415-pinctrl.dtsi b/arch/arm/boot/dts/stih415-pinctrl.dtsi deleted file mode 100644 index bd028ce98b61..000000000000 --- a/arch/arm/boot/dts/stih415-pinctrl.dtsi +++ /dev/null @@ -1,545 +0,0 @@ -/* - * Copyright (C) 2013 STMicroelectronics (R&D) Limited. - * Author: Srinivas Kandagatla <srinivas.kandagatla@st.com> - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * publishhed by the Free Software Foundation. - */ -#include "st-pincfg.h" -#include <dt-bindings/interrupt-controller/arm-gic.h> -/ { - - aliases { - gpio0 = &pio0; - gpio1 = &pio1; - gpio2 = &pio2; - gpio3 = &pio3; - gpio4 = &pio4; - gpio5 = &pio5; - gpio6 = &pio6; - gpio7 = &pio7; - gpio8 = &pio8; - gpio9 = &pio9; - gpio10 = &pio10; - gpio11 = &pio11; - gpio12 = &pio12; - gpio13 = &pio13; - gpio14 = &pio14; - gpio15 = &pio15; - gpio16 = &pio16; - gpio17 = &pio17; - gpio18 = &pio18; - gpio19 = &pio100; - gpio20 = &pio101; - gpio21 = &pio102; - gpio22 = &pio103; - gpio23 = &pio104; - gpio24 = &pio105; - gpio25 = &pio106; - gpio26 = &pio107; - }; - - soc { - pin-controller-sbc { - #address-cells = <1>; - #size-cells = <1>; - compatible = "st,stih415-sbc-pinctrl"; - st,syscfg = <&syscfg_sbc>; - reg = <0xfe61f080 0x4>; - reg-names = "irqmux"; - interrupts = <GIC_SPI 180 IRQ_TYPE_LEVEL_HIGH>; - interrupt-names = "irqmux"; - ranges = <0 0xfe610000 0x5000>; - - pio0: gpio@fe610000 { - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - reg = <0 0x100>; - st,bank-name = "PIO0"; - }; - pio1: gpio@fe611000 { - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - reg = <0x1000 0x100>; - st,bank-name = "PIO1"; - }; - pio2: gpio@fe612000 { - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - reg = <0x2000 0x100>; - st,bank-name = "PIO2"; - }; - pio3: gpio@fe613000 { - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - reg = <0x3000 0x100>; - st,bank-name = "PIO3"; - }; - pio4: gpio@fe614000 { - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - reg = <0x4000 0x100>; - st,bank-name = "PIO4"; - }; - - sbc_serial1 { - pinctrl_sbc_serial1:sbc_serial1 { - st,pins { - tx = <&pio2 6 ALT3 OUT>; - rx = <&pio2 7 ALT3 IN>; - }; - }; - }; - - keyscan { - pinctrl_keyscan: keyscan { - st,pins { - keyin0 = <&pio0 2 ALT2 IN>; - keyin1 = <&pio0 3 ALT2 IN>; - keyin2 = <&pio0 4 ALT2 IN>; - keyin3 = <&pio2 6 ALT2 IN>; - - keyout0 = <&pio1 6 ALT2 OUT>; - keyout1 = <&pio1 7 ALT2 OUT>; - keyout2 = <&pio0 6 ALT2 OUT>; - keyout3 = <&pio2 7 ALT2 OUT>; - }; - }; - }; - - sbc_i2c0 { - pinctrl_sbc_i2c0_default: sbc_i2c0-default { - st,pins { - sda = <&pio4 6 ALT1 BIDIR>; - scl = <&pio4 5 ALT1 BIDIR>; - }; - }; - }; - - sbc_i2c1 { - pinctrl_sbc_i2c1_default: sbc_i2c1-default { - st,pins { - sda = <&pio3 2 ALT2 BIDIR>; - scl = <&pio3 1 ALT2 BIDIR>; - }; - }; - }; - - rc{ - pinctrl_ir: ir0 { - st,pins { - ir = <&pio4 0 ALT2 IN>; - }; - }; - }; - - gmac1 { - pinctrl_mii1: mii1 { - st,pins { - txd0 = <&pio0 0 ALT1 OUT SE_NICLK_IO 0 CLK_A>; - txd1 = <&pio0 1 ALT1 OUT SE_NICLK_IO 0 CLK_A>; - txd2 = <&pio0 2 ALT1 OUT SE_NICLK_IO 0 CLK_A>; - txd3 = <&pio0 3 ALT1 OUT SE_NICLK_IO 0 CLK_A>; - txer = <&pio0 4 ALT1 OUT SE_NICLK_IO 0 CLK_A>; - txen = <&pio0 5 ALT1 OUT SE_NICLK_IO 0 CLK_A>; - txclk = <&pio0 6 ALT1 IN NICLK 0 CLK_A>; - col = <&pio0 7 ALT1 IN BYPASS 1000>; - mdio = <&pio1 0 ALT1 OUT BYPASS 0>; - mdc = <&pio1 1 ALT1 OUT NICLK 0 CLK_A>; - crs = <&pio1 2 ALT1 IN BYPASS 1000>; - mdint = <&pio1 3 ALT1 IN BYPASS 0>; - rxd0 = <&pio1 4 ALT1 IN SE_NICLK_IO 0 CLK_A>; - rxd1 = <&pio1 5 ALT1 IN SE_NICLK_IO 0 CLK_A>; - rxd2 = <&pio1 6 ALT1 IN SE_NICLK_IO 0 CLK_A>; - rxd3 = <&pio1 7 ALT1 IN SE_NICLK_IO 0 CLK_A>; - rxdv = <&pio2 0 ALT1 IN SE_NICLK_IO 0 CLK_A>; - rx_er = <&pio2 1 ALT1 IN SE_NICLK_IO 0 CLK_A>; - rxclk = <&pio2 2 ALT1 IN NICLK 0 CLK_A>; - phyclk = <&pio2 3 ALT1 IN NICLK 1000 CLK_A>; - }; - }; - - pinctrl_rgmii1: rgmii1-0 { - st,pins { - txd0 = <&pio0 0 ALT1 OUT DE_IO 1000 CLK_A>; - txd1 = <&pio0 1 ALT1 OUT DE_IO 1000 CLK_A>; - txd2 = <&pio0 2 ALT1 OUT DE_IO 1000 CLK_A>; - txd3 = <&pio0 3 ALT1 OUT DE_IO 1000 CLK_A>; - txen = <&pio0 5 ALT1 OUT DE_IO 0 CLK_A>; - txclk = <&pio0 6 ALT1 IN NICLK 0 CLK_A>; - mdio = <&pio1 0 ALT1 OUT BYPASS 0>; - mdc = <&pio1 1 ALT1 OUT NICLK 0 CLK_A>; - rxd0 = <&pio1 4 ALT1 IN DE_IO 0 CLK_A>; - rxd1 = <&pio1 5 ALT1 IN DE_IO 0 CLK_A>; - rxd2 = <&pio1 6 ALT1 IN DE_IO 0 CLK_A>; - rxd3 = <&pio1 7 ALT1 IN DE_IO 0 CLK_A>; - - rxdv = <&pio2 0 ALT1 IN DE_IO 500 CLK_A>; - rxclk = <&pio2 2 ALT1 IN NICLK 0 CLK_A>; - phyclk = <&pio2 3 ALT4 OUT NICLK 0 CLK_B>; - - clk125= <&pio3 7 ALT4 IN NICLK 0 CLK_A>; - }; - }; - }; - }; - - pin-controller-front { - #address-cells = <1>; - #size-cells = <1>; - compatible = "st,stih415-front-pinctrl"; - st,syscfg = <&syscfg_front>; - reg = <0xfee0f080 0x4>; - reg-names = "irqmux"; - interrupts = <GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH>; - interrupt-names = "irqmux"; - ranges = <0 0xfee00000 0x8000>; - - pio5: gpio@fee00000 { - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - reg = <0 0x100>; - st,bank-name = "PIO5"; - }; - pio6: gpio@fee01000 { - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - reg = <0x1000 0x100>; - st,bank-name = "PIO6"; - }; - pio7: gpio@fee02000 { - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - reg = <0x2000 0x100>; - st,bank-name = "PIO7"; - }; - pio8: gpio@fee03000 { - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - reg = <0x3000 0x100>; - st,bank-name = "PIO8"; - }; - pio9: gpio@fee04000 { - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - reg = <0x4000 0x100>; - st,bank-name = "PIO9"; - }; - pio10: gpio@fee05000 { - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - reg = <0x5000 0x100>; - st,bank-name = "PIO10"; - }; - pio11: gpio@fee06000 { - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - reg = <0x6000 0x100>; - st,bank-name = "PIO11"; - }; - pio12: gpio@fee07000 { - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - reg = <0x7000 0x100>; - st,bank-name = "PIO12"; - }; - - i2c0 { - pinctrl_i2c0_default: i2c0-default { - st,pins { - sda = <&pio9 3 ALT1 BIDIR>; - scl = <&pio9 2 ALT1 BIDIR>; - }; - }; - }; - - i2c1 { - pinctrl_i2c1_default: i2c1-default { - st,pins { - sda = <&pio12 1 ALT1 BIDIR>; - scl = <&pio12 0 ALT1 BIDIR>; - }; - }; - }; - }; - - pin-controller-rear { - #address-cells = <1>; - #size-cells = <1>; - compatible = "st,stih415-rear-pinctrl"; - st,syscfg = <&syscfg_rear>; - reg = <0xfe82f080 0x4>; - reg-names = "irqmux"; - interrupts = <GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH>; - interrupt-names = "irqmux"; - ranges = <0 0xfe820000 0x8000>; - - pio13: gpio@fe820000 { - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - reg = <0 0x100>; - st,bank-name = "PIO13"; - }; - pio14: gpio@fe821000 { - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - reg = <0x1000 0x100>; - st,bank-name = "PIO14"; - }; - pio15: gpio@fe822000 { - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - reg = <0x2000 0x100>; - st,bank-name = "PIO15"; - }; - pio16: gpio@fe823000 { - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - reg = <0x3000 0x100>; - st,bank-name = "PIO16"; - }; - pio17: gpio@fe824000 { - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - reg = <0x4000 0x100>; - st,bank-name = "PIO17"; - }; - pio18: gpio@fe825000 { - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - reg = <0x5000 0x100>; - st,bank-name = "PIO18"; - }; - - serial2 { - pinctrl_serial2: serial2-0 { - st,pins { - tx = <&pio17 4 ALT2 OUT>; - rx = <&pio17 5 ALT2 IN>; - }; - }; - }; - - gmac0{ - pinctrl_mii0: mii0 { - st,pins { - mdint = <&pio13 6 ALT2 IN BYPASS 0>; - txen = <&pio13 7 ALT2 OUT SE_NICLK_IO 0 CLK_A>; - - txd0 = <&pio14 0 ALT2 OUT SE_NICLK_IO 0 CLK_A>; - txd1 = <&pio14 1 ALT2 OUT SE_NICLK_IO 0 CLK_A>; - txd2 = <&pio14 2 ALT2 OUT SE_NICLK_IO 0 CLK_B>; - txd3 = <&pio14 3 ALT2 OUT SE_NICLK_IO 0 CLK_B>; - - txclk = <&pio15 0 ALT2 IN NICLK 0 CLK_A>; - txer = <&pio15 1 ALT2 OUT SE_NICLK_IO 0 CLK_A>; - crs = <&pio15 2 ALT2 IN BYPASS 1000>; - col = <&pio15 3 ALT2 IN BYPASS 1000>; - mdio = <&pio15 4 ALT2 OUT BYPASS 3000>; - mdc = <&pio15 5 ALT2 OUT NICLK 0 CLK_B>; - - rxd0 = <&pio16 0 ALT2 IN SE_NICLK_IO 0 CLK_A>; - rxd1 = <&pio16 1 ALT2 IN SE_NICLK_IO 0 CLK_A>; - rxd2 = <&pio16 2 ALT2 IN SE_NICLK_IO 0 CLK_A>; - rxd3 = <&pio16 3 ALT2 IN SE_NICLK_IO 0 CLK_A>; - rxdv = <&pio15 6 ALT2 IN SE_NICLK_IO 0 CLK_A>; - rx_er = <&pio15 7 ALT2 IN SE_NICLK_IO 0 CLK_A>; - rxclk = <&pio17 0 ALT2 IN NICLK 0 CLK_A>; - phyclk = <&pio13 5 ALT2 OUT NICLK 1000 CLK_A>; - - }; - }; - - pinctrl_gmii0: gmii0 { - st,pins { - mdint = <&pio13 6 ALT2 IN BYPASS 0>; - mdio = <&pio15 4 ALT2 OUT BYPASS 3000>; - mdc = <&pio15 5 ALT2 OUT NICLK 0 CLK_B>; - txen = <&pio13 7 ALT2 OUT SE_NICLK_IO 3000 CLK_A>; - - txd0 = <&pio14 0 ALT2 OUT SE_NICLK_IO 3000 CLK_A>; - txd1 = <&pio14 1 ALT2 OUT SE_NICLK_IO 3000 CLK_A>; - txd2 = <&pio14 2 ALT2 OUT SE_NICLK_IO 3000 CLK_B>; - txd3 = <&pio14 3 ALT2 OUT SE_NICLK_IO 3000 CLK_B>; - txd4 = <&pio14 4 ALT2 OUT SE_NICLK_IO 3000 CLK_B>; - txd5 = <&pio14 5 ALT2 OUT SE_NICLK_IO 3000 CLK_B>; - txd6 = <&pio14 6 ALT2 OUT SE_NICLK_IO 3000 CLK_B>; - txd7 = <&pio14 7 ALT2 OUT SE_NICLK_IO 3000 CLK_B>; - - txclk = <&pio15 0 ALT2 IN NICLK 0 CLK_A>; - txer = <&pio15 1 ALT2 OUT SE_NICLK_IO 3000 CLK_A>; - crs = <&pio15 2 ALT2 IN BYPASS 1000>; - col = <&pio15 3 ALT2 IN BYPASS 1000>; - rxdv = <&pio15 6 ALT2 IN SE_NICLK_IO 1500 CLK_A>; - rx_er = <&pio15 7 ALT2 IN SE_NICLK_IO 1500 CLK_A>; - - rxd0 = <&pio16 0 ALT2 IN SE_NICLK_IO 1500 CLK_A>; - rxd1 = <&pio16 1 ALT2 IN SE_NICLK_IO 1500 CLK_A>; - rxd2 = <&pio16 2 ALT2 IN SE_NICLK_IO 1500 CLK_A>; - rxd3 = <&pio16 3 ALT2 IN SE_NICLK_IO 1500 CLK_A>; - rxd4 = <&pio16 4 ALT2 IN SE_NICLK_IO 1500 CLK_A>; - rxd5 = <&pio16 5 ALT2 IN SE_NICLK_IO 1500 CLK_A>; - rxd6 = <&pio16 6 ALT2 IN SE_NICLK_IO 1500 CLK_A>; - rxd7 = <&pio16 7 ALT2 IN SE_NICLK_IO 1500 CLK_A>; - - rxclk = <&pio17 0 ALT2 IN NICLK 0 CLK_A>; - clk125 = <&pio17 6 ALT1 IN NICLK 0 CLK_A>; - phyclk = <&pio13 5 ALT4 OUT NICLK 0 CLK_B>; - - - }; - }; - }; - - mmc0 { - pinctrl_mmc0: mmc0 { - st,pins { - mmcclk = <&pio13 4 ALT4 BIDIR_PU NICLK 0 CLK_B>; - data0 = <&pio14 4 ALT4 BIDIR_PU BYPASS 0>; - data1 = <&pio14 5 ALT4 BIDIR_PU BYPASS 0>; - data2 = <&pio14 6 ALT4 BIDIR_PU BYPASS 0>; - data3 = <&pio14 7 ALT4 BIDIR_PU BYPASS 0>; - cmd = <&pio15 1 ALT4 BIDIR_PU BYPASS 0>; - wp = <&pio15 3 ALT4 IN>; - data4 = <&pio16 4 ALT4 BIDIR_PU BYPASS 0>; - data5 = <&pio16 5 ALT4 BIDIR_PU BYPASS 0>; - data6 = <&pio16 6 ALT4 BIDIR_PU BYPASS 0>; - data7 = <&pio16 7 ALT4 BIDIR_PU BYPASS 0>; - pwr = <&pio17 1 ALT4 OUT>; - cd = <&pio17 2 ALT4 IN>; - led = <&pio17 3 ALT4 OUT>; - }; - }; - }; - }; - - pin-controller-left { - #address-cells = <1>; - #size-cells = <1>; - compatible = "st,stih415-left-pinctrl"; - st,syscfg = <&syscfg_left>; - reg = <0xfd6bf080 0x4>; - reg-names = "irqmux"; - interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>; - interrupt-names = "irqmux"; - ranges = <0 0xfd6b0000 0x3000>; - - pio100: gpio@fd6b0000 { - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - reg = <0 0x100>; - st,bank-name = "PIO100"; - }; - pio101: gpio@fd6b1000 { - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - reg = <0x1000 0x100>; - st,bank-name = "PIO101"; - }; - pio102: gpio@fd6b2000 { - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - reg = <0x2000 0x100>; - st,bank-name = "PIO102"; - }; - }; - - pin-controller-right { - #address-cells = <1>; - #size-cells = <1>; - compatible = "st,stih415-right-pinctrl"; - st,syscfg = <&syscfg_right>; - reg = <0xfd33f080 0x4>; - reg-names = "irqmux"; - interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>; - interrupt-names = "irqmux"; - ranges = <0 0xfd330000 0x5000>; - - pio103: gpio@fd330000 { - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - reg = <0 0x100>; - st,bank-name = "PIO103"; - }; - pio104: gpio@fd331000 { - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - reg = <0x1000 0x100>; - st,bank-name = "PIO104"; - }; - pio105: gpio@fd332000 { - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - reg = <0x2000 0x100>; - st,bank-name = "PIO105"; - }; - pio106: gpio@fd333000 { - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - reg = <0x3000 0x100>; - st,bank-name = "PIO106"; - }; - pio107: gpio@fd334000 { - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - reg = <0x4000 0x100>; - st,bank-name = "PIO107"; - }; - }; - }; -}; diff --git a/arch/arm/boot/dts/stih415.dtsi b/arch/arm/boot/dts/stih415.dtsi deleted file mode 100644 index 12427e651e5e..000000000000 --- a/arch/arm/boot/dts/stih415.dtsi +++ /dev/null @@ -1,234 +0,0 @@ -/* - * Copyright (C) 2013 STMicroelectronics (R&D) Limited. - * Author: Srinivas Kandagatla <srinivas.kandagatla@st.com> - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * publishhed by the Free Software Foundation. - */ -#include "stih41x.dtsi" -#include "stih415-clock.dtsi" -#include "stih415-pinctrl.dtsi" -#include <dt-bindings/interrupt-controller/arm-gic.h> -#include <dt-bindings/reset/stih415-resets.h> -/ { - - L2: cache-controller { - compatible = "arm,pl310-cache"; - reg = <0xfffe2000 0x1000>; - arm,data-latency = <3 2 2>; - arm,tag-latency = <1 1 1>; - cache-unified; - cache-level = <2>; - }; - - soc { - #address-cells = <1>; - #size-cells = <1>; - interrupt-parent = <&intc>; - ranges; - compatible = "simple-bus"; - - powerdown: powerdown-controller { - #reset-cells = <1>; - compatible = "st,stih415-powerdown"; - }; - - softreset: softreset-controller { - #reset-cells = <1>; - compatible = "st,stih415-softreset"; - }; - - syscfg_sbc: sbc-syscfg@fe600000{ - compatible = "st,stih415-sbc-syscfg", "syscon"; - reg = <0xfe600000 0xb4>; - }; - - syscfg_front: front-syscfg@fee10000{ - compatible = "st,stih415-front-syscfg", "syscon"; - reg = <0xfee10000 0x194>; - }; - - syscfg_rear: rear-syscfg@fe830000{ - compatible = "st,stih415-rear-syscfg", "syscon"; - reg = <0xfe830000 0x190>; - }; - - /* MPE syscfgs */ - syscfg_left: left-syscfg@fd690000{ - compatible = "st,stih415-left-syscfg", "syscon"; - reg = <0xfd690000 0x78>; - }; - - syscfg_right: right-syscfg@fd320000{ - compatible = "st,stih415-right-syscfg", "syscon"; - reg = <0xfd320000 0x180>; - }; - - syscfg_system: system-syscfg@fdde0000 { - compatible = "st,stih415-system-syscfg", "syscon"; - reg = <0xfdde0000 0x15c>; - }; - - syscfg_lpm: lpm-syscfg@fe4b5100{ - compatible = "st,stih415-lpm-syscfg", "syscon"; - reg = <0xfe4b5100 0x08>; - }; - - serial2: serial@fed32000 { - compatible = "st,asc"; - status = "disabled"; - reg = <0xfed32000 0x2c>; - interrupts = <0 197 0>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_serial2>; - clocks = <&clk_s_a0_ls CLK_ICN_REG>; - }; - - /* SBC comms block ASCs in SASG1 */ - sbc_serial1: serial@fe531000 { - compatible = "st,asc"; - status = "disabled"; - reg = <0xfe531000 0x2c>; - interrupts = <0 210 0>; - clocks = <&clk_sysin>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_sbc_serial1>; - }; - - i2c@fed40000 { - compatible = "st,comms-ssc4-i2c"; - reg = <0xfed40000 0x110>; - interrupts = <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&clk_s_a0_ls CLK_ICN_REG>; - clock-names = "ssc"; - clock-frequency = <400000>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c0_default>; - - status = "disabled"; - }; - - i2c@fed41000 { - compatible = "st,comms-ssc4-i2c"; - reg = <0xfed41000 0x110>; - interrupts = <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&clk_s_a0_ls CLK_ICN_REG>; - clock-names = "ssc"; - clock-frequency = <400000>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c1_default>; - - status = "disabled"; - }; - - i2c@fe540000 { - compatible = "st,comms-ssc4-i2c"; - reg = <0xfe540000 0x110>; - interrupts = <GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&clk_sysin>; - clock-names = "ssc"; - clock-frequency = <400000>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_sbc_i2c0_default>; - - status = "disabled"; - }; - - i2c@fe541000 { - compatible = "st,comms-ssc4-i2c"; - reg = <0xfe541000 0x110>; - interrupts = <GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&clk_sysin>; - clock-names = "ssc"; - clock-frequency = <400000>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_sbc_i2c1_default>; - - status = "disabled"; - }; - - ethernet0: dwmac@fe810000 { - device_type = "network"; - compatible = "st,stih415-dwmac", "snps,dwmac", "snps,dwmac-3.610"; - status = "disabled"; - - reg = <0xfe810000 0x8000>; - reg-names = "stmmaceth"; - - interrupts = <0 147 0>, <0 148 0>, <0 149 0>; - interrupt-names = "macirq", "eth_wake_irq", "eth_lpi"; - resets = <&softreset STIH415_ETH0_SOFTRESET>; - reset-names = "stmmaceth"; - - snps,pbl = <32>; - snps,mixed-burst; - snps,force_sf_dma_mode; - - st,syscon = <&syscfg_rear 0x148>; - - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_mii0>; - clock-names = "stmmaceth", "sti-ethclk"; - clocks = <&clk_s_a1_ls CLK_ICN_IF_2>, <&clk_s_a1_ls CLK_GMAC0_PHY>; - }; - - ethernet1: dwmac@fef08000 { - device_type = "network"; - compatible = "st,stih415-dwmac", "snps,dwmac", "snps,dwmac-3.610"; - status = "disabled"; - reg = <0xfef08000 0x8000>; - reg-names = "stmmaceth"; - interrupts = <0 150 0>, <0 151 0>, <0 152 0>; - interrupt-names = "macirq", "eth_wake_irq", "eth_lpi"; - - snps,pbl = <32>; - snps,mixed-burst; - snps,force_sf_dma_mode; - - st,syscon = <&syscfg_sbc 0x74>; - - resets = <&softreset STIH415_ETH1_SOFTRESET>; - reset-names = "stmmaceth"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_mii1>; - clock-names = "stmmaceth", "sti-ethclk"; - clocks = <&clk_s_a0_ls CLK_ICN_REG>, <&clk_s_a0_ls CLK_ETH1_PHY>; - }; - - rc: rc@fe518000 { - compatible = "st,comms-irb"; - reg = <0xfe518000 0x234>; - interrupts = <0 203 0>; - clocks = <&clk_sysin>; - rx-mode = "infrared"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_ir>; - resets = <&softreset STIH415_IRB_SOFTRESET>; - }; - - keyscan: keyscan@fe4b0000 { - compatible = "st,sti-keyscan"; - status = "disabled"; - reg = <0xfe4b0000 0x2000>; - interrupts = <GIC_SPI 212 IRQ_TYPE_NONE>; - clocks = <&clk_sysin>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_keyscan>; - resets = <&powerdown STIH415_KEYSCAN_POWERDOWN>, - <&softreset STIH415_KEYSCAN_SOFTRESET>; - }; - - mmc0: sdhci@fe81e000 { - compatible = "st,sdhci"; - status = "disabled"; - reg = <0xfe81e000 0x1000>; - interrupts = <GIC_SPI 145 IRQ_TYPE_NONE>; - interrupt-names = "mmcirq"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_mmc0>; - clock-names = "mmc"; - clocks = <&clk_s_a1_ls 1>; - }; - }; -}; diff --git a/arch/arm/boot/dts/stih416-b2000.dts b/arch/arm/boot/dts/stih416-b2000.dts deleted file mode 100644 index 488e80a5d69d..000000000000 --- a/arch/arm/boot/dts/stih416-b2000.dts +++ /dev/null @@ -1,15 +0,0 @@ -/* - * Copyright (C) 2013 STMicroelectronics (R&D) Limited. - * Author: Srinivas Kandagatla <srinivas.kandagatla@st.com> - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * publishhed by the Free Software Foundation. - */ -/dts-v1/; -#include "stih416.dtsi" -#include "stih41x-b2000.dtsi" -/ { - model = "STiH416 B2000"; - compatible = "st,stih416-b2000", "st,stih416"; -}; diff --git a/arch/arm/boot/dts/stih416-b2020.dts b/arch/arm/boot/dts/stih416-b2020.dts deleted file mode 100644 index 200a81844765..000000000000 --- a/arch/arm/boot/dts/stih416-b2020.dts +++ /dev/null @@ -1,37 +0,0 @@ -/* - * Copyright (C) 2013 STMicroelectronics (R&D) Limited. - * Author: Srinivas Kandagatla <srinivas.kandagatla@st.com> - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * publishhed by the Free Software Foundation. - */ -/dts-v1/; -#include "stih416.dtsi" -#include "stih41x-b2020.dtsi" -/ { - model = "STiH416 B2020"; - compatible = "st,stih416-b2020", "st,stih416"; - - soc { - mmc1: sdhci@fe81f000 { - status = "okay"; - bus-width = <8>; - non-removable; - }; - - miphy365x_phy: phy@fe382000 { - phy_port0: port@fe382000 { - st,sata-gen = <3>; - }; - - phy_port1: port@fe38a000 { - st,pcie-tx-pol-inv; - }; - }; - - sata0: sata@fe380000{ - status = "okay"; - }; - }; -}; diff --git a/arch/arm/boot/dts/stih416-b2020e.dts b/arch/arm/boot/dts/stih416-b2020e.dts deleted file mode 100644 index de320cd067de..000000000000 --- a/arch/arm/boot/dts/stih416-b2020e.dts +++ /dev/null @@ -1,65 +0,0 @@ -/* - * Copyright (C) 2014 STMicroelectronics (R&D) Limited. - * Author: Lee Jones <lee.jones@linaro.org> - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * publishhed by the Free Software Foundation. - */ -/dts-v1/; -#include "stih416.dtsi" -#include "stih41x-b2020.dtsi" -#include <dt-bindings/gpio/gpio.h> -/ { - model = "STiH416 B2020 REV-E"; - compatible = "st,stih416-b2020", "st,stih416"; - - soc { - leds { - compatible = "gpio-leds"; - red { - label = "Front Panel LED"; - gpios = <&pio4 1 GPIO_ACTIVE_HIGH>; - linux,default-trigger = "heartbeat"; - }; - green { - gpios = <&pio1 3 GPIO_ACTIVE_HIGH>; - default-state = "off"; - }; - }; - - ethernet1: dwmac@fef08000 { - snps,reset-gpio = <&pio0 7>; - }; - - mmc1: sdhci@fe81f000 { - status = "okay"; - bus-width = <8>; - non-removable; - }; - - miphy365x_phy: phy@fe382000 { - phy_port0: port@fe382000 { - st,sata-gen = <3>; - }; - - phy_port1: port@fe38a000 { - st,pcie-tx-pol-inv; - }; - }; - - sata0: sata@fe380000{ - status = "okay"; - }; - - /* SAS PWM Module */ - pwm0: pwm@fed10000 { - status = "okay"; - }; - - /* SBC PWM Module */ - pwm1: pwm@fe510000 { - status = "okay"; - }; - }; -}; diff --git a/arch/arm/boot/dts/stih416-clock.dtsi b/arch/arm/boot/dts/stih416-clock.dtsi deleted file mode 100644 index 5b4fb838cddb..000000000000 --- a/arch/arm/boot/dts/stih416-clock.dtsi +++ /dev/null @@ -1,756 +0,0 @@ -/* - * Copyright (C) 2013 STMicroelectronics R&D Limited - * <stlinux-devel@stlinux.com> - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - */ - -#include <dt-bindings/clock/stih416-clks.h> - -/ { - clocks { - #address-cells = <1>; - #size-cells = <1>; - ranges; - - /* - * Fixed 30MHz oscillator inputs to SoC - */ - clk_sysin: clk-sysin { - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-frequency = <30000000>; - }; - - /* - * ClockGenAs on SASG2 - */ - clockgen-a@fee62000 { - reg = <0xfee62000 0xb48>; - - clk_s_a0_pll: clk-s-a0-pll { - #clock-cells = <1>; - compatible = "st,clkgena-plls-c65"; - - clocks = <&clk_sysin>; - - clock-output-names = "clk-s-a0-pll0-hs", - "clk-s-a0-pll0-ls", - "clk-s-a0-pll1"; - }; - - clk_s_a0_osc_prediv: clk-s-a0-osc-prediv { - #clock-cells = <0>; - compatible = "st,clkgena-prediv-c65", - "st,clkgena-prediv"; - - clocks = <&clk_sysin>; - - clock-output-names = "clk-s-a0-osc-prediv"; - }; - - clk_s_a0_hs: clk-s-a0-hs { - #clock-cells = <1>; - compatible = "st,clkgena-divmux-c65-hs", - "st,clkgena-divmux"; - - clocks = <&clk_s_a0_osc_prediv>, - <&clk_s_a0_pll 0>, /* PLL0 HS */ - <&clk_s_a0_pll 2>; /* PLL1 */ - - clock-output-names = "clk-s-fdma-0", - "clk-s-fdma-1", - ""; /* clk-s-jit-sense */ - /* Fourth output unused */ - }; - - clk_s_a0_ls: clk-s-a0-ls { - #clock-cells = <1>; - compatible = "st,clkgena-divmux-c65-ls", - "st,clkgena-divmux"; - - clocks = <&clk_s_a0_osc_prediv>, - <&clk_s_a0_pll 1>, /* PLL0 LS */ - <&clk_s_a0_pll 2>; /* PLL1 */ - - clock-output-names = "clk-s-icn-reg-0", - "clk-s-icn-if-0", - "clk-s-icn-reg-lp-0", - "clk-s-emiss", - "clk-s-eth1-phy", - "clk-s-mii-ref-out"; - /* Remaining outputs unused */ - }; - }; - - clockgen-a@fee81000 { - reg = <0xfee81000 0xb48>; - - clk_s_a1_pll: clk-s-a1-pll { - #clock-cells = <1>; - compatible = "st,clkgena-plls-c65"; - - clocks = <&clk_sysin>; - - clock-output-names = "clk-s-a1-pll0-hs", - "clk-s-a1-pll0-ls", - "clk-s-a1-pll1"; - }; - - clk_s_a1_osc_prediv: clk-s-a1-osc-prediv { - #clock-cells = <0>; - compatible = "st,clkgena-prediv-c65", - "st,clkgena-prediv"; - - clocks = <&clk_sysin>; - - clock-output-names = "clk-s-a1-osc-prediv"; - }; - - clk_s_a1_hs: clk-s-a1-hs { - #clock-cells = <1>; - compatible = "st,clkgena-divmux-c65-hs", - "st,clkgena-divmux"; - - clocks = <&clk_s_a1_osc_prediv>, - <&clk_s_a1_pll 0>, /* PLL0 HS */ - <&clk_s_a1_pll 2>; /* PLL1 */ - - clock-output-names = "", /* Reserved */ - "", /* Reserved */ - "clk-s-stac-phy", - "clk-s-vtac-tx-phy"; - }; - - clk_s_a1_ls: clk-s-a1-ls { - #clock-cells = <1>; - compatible = "st,clkgena-divmux-c65-ls", - "st,clkgena-divmux"; - - clocks = <&clk_s_a1_osc_prediv>, - <&clk_s_a1_pll 1>, /* PLL0 LS */ - <&clk_s_a1_pll 2>; /* PLL1 */ - - clock-output-names = "clk-s-icn-if-2", - "clk-s-card-mmc-0", - "clk-s-icn-if-1", - "clk-s-gmac0-phy", - "clk-s-nand-ctrl", - "", /* Reserved */ - "clk-s-mii0-ref-out", - "clk-s-stac-sys", - "clk-s-card-mmc-1"; - /* Remaining outputs unused */ - }; - }; - - /* - * ClockGenAs on MPE42 - */ - clockgen-a@fde12000 { - reg = <0xfde12000 0xb50>; - - clk_m_a0_pll0: clk-m-a0-pll0 { - #clock-cells = <1>; - compatible = "st,plls-c32-a1x-0", "st,clkgen-plls-c32"; - - clocks = <&clk_sysin>; - - clock-output-names = "clk-m-a0-pll0-phi0", - "clk-m-a0-pll0-phi1", - "clk-m-a0-pll0-phi2", - "clk-m-a0-pll0-phi3"; - }; - - clk_m_a0_pll1: clk-m-a0-pll1 { - #clock-cells = <1>; - compatible = "st,plls-c32-a1x-1", "st,clkgen-plls-c32"; - - clocks = <&clk_sysin>; - - clock-output-names = "clk-m-a0-pll1-phi0", - "clk-m-a0-pll1-phi1", - "clk-m-a0-pll1-phi2", - "clk-m-a0-pll1-phi3"; - }; - - clk_m_a0_osc_prediv: clk-m-a0-osc-prediv { - #clock-cells = <0>; - compatible = "st,clkgena-prediv-c32", - "st,clkgena-prediv"; - - clocks = <&clk_sysin>; - - clock-output-names = "clk-m-a0-osc-prediv"; - }; - - clk_m_a0_div0: clk-m-a0-div0 { - #clock-cells = <1>; - compatible = "st,clkgena-divmux-c32-odf0", - "st,clkgena-divmux"; - - clocks = <&clk_m_a0_osc_prediv>, - <&clk_m_a0_pll0 0>, /* PLL0 PHI0 */ - <&clk_m_a0_pll1 0>; /* PLL1 PHI0 */ - - clock-output-names = "", /* Unused */ - "", /* Unused */ - "clk-m-fdma-12", - "", /* Unused */ - "clk-m-pp-dmu-0", - "clk-m-pp-dmu-1", - "clk-m-icm-lmi", - "clk-m-vid-dmu-0"; - }; - - clk_m_a0_div1: clk-m-a0-div1 { - #clock-cells = <1>; - compatible = "st,clkgena-divmux-c32-odf1", - "st,clkgena-divmux"; - - clocks = <&clk_m_a0_osc_prediv>, - <&clk_m_a0_pll0 1>, /* PLL0 PHI1 */ - <&clk_m_a0_pll1 1>; /* PLL1 PHI1 */ - - clock-output-names = "clk-m-vid-dmu-1", - "", /* Unused */ - "clk-m-a9-ext2f", - "clk-m-st40rt", - "clk-m-st231-dmu-0", - "clk-m-st231-dmu-1", - "clk-m-st231-aud", - "clk-m-st231-gp-0"; - }; - - clk_m_a0_div2: clk-m-a0-div2 { - #clock-cells = <1>; - compatible = "st,clkgena-divmux-c32-odf2", - "st,clkgena-divmux"; - - clocks = <&clk_m_a0_osc_prediv>, - <&clk_m_a0_pll0 2>, /* PLL0 PHI2 */ - <&clk_m_a0_pll1 2>; /* PLL1 PHI2 */ - - clock-output-names = "clk-m-st231-gp-1", - "clk-m-icn-cpu", - "clk-m-icn-stac", - "clk-m-tx-icn-dmu-0", - "clk-m-tx-icn-dmu-1", - "clk-m-tx-icn-ts", - "clk-m-icn-vdp-0", - "clk-m-icn-vdp-1"; - }; - - clk_m_a0_div3: clk-m-a0-div3 { - #clock-cells = <1>; - compatible = "st,clkgena-divmux-c32-odf3", - "st,clkgena-divmux"; - - clocks = <&clk_m_a0_osc_prediv>, - <&clk_m_a0_pll0 3>, /* PLL0 PHI3 */ - <&clk_m_a0_pll1 3>; /* PLL1 PHI3 */ - - clock-output-names = "", /* Unused */ - "", /* Unused */ - "", /* Unused */ - "", /* Unused */ - "clk-m-icn-vp8", - "", /* Unused */ - "clk-m-icn-reg-11", - "clk-m-a9-trace"; - }; - }; - - clockgen-a@fd6db000 { - reg = <0xfd6db000 0xb50>; - - clk_m_a1_pll0: clk-m-a1-pll0 { - #clock-cells = <1>; - compatible = "st,plls-c32-a1x-0", "st,clkgen-plls-c32"; - - clocks = <&clk_sysin>; - - clock-output-names = "clk-m-a1-pll0-phi0", - "clk-m-a1-pll0-phi1", - "clk-m-a1-pll0-phi2", - "clk-m-a1-pll0-phi3"; - }; - - clk_m_a1_pll1: clk-m-a1-pll1 { - #clock-cells = <1>; - compatible = "st,plls-c32-a1x-1", "st,clkgen-plls-c32"; - - clocks = <&clk_sysin>; - - clock-output-names = "clk-m-a1-pll1-phi0", - "clk-m-a1-pll1-phi1", - "clk-m-a1-pll1-phi2", - "clk-m-a1-pll1-phi3"; - }; - - clk_m_a1_osc_prediv: clk-m-a1-osc-prediv { - #clock-cells = <0>; - compatible = "st,clkgena-prediv-c32", - "st,clkgena-prediv"; - - clocks = <&clk_sysin>; - - clock-output-names = "clk-m-a1-osc-prediv"; - }; - - clk_m_a1_div0: clk-m-a1-div0 { - #clock-cells = <1>; - compatible = "st,clkgena-divmux-c32-odf0", - "st,clkgena-divmux"; - - clocks = <&clk_m_a1_osc_prediv>, - <&clk_m_a1_pll0 0>, /* PLL0 PHI0 */ - <&clk_m_a1_pll1 0>; /* PLL1 PHI0 */ - - clock-output-names = "", /* Unused */ - "clk-m-fdma-10", - "clk-m-fdma-11", - "clk-m-hva-alt", - "clk-m-proc-sc", - "clk-m-tp", - "clk-m-rx-icn-dmu-0", - "clk-m-rx-icn-dmu-1"; - }; - - clk_m_a1_div1: clk-m-a1-div1 { - #clock-cells = <1>; - compatible = "st,clkgena-divmux-c32-odf1", - "st,clkgena-divmux"; - - clocks = <&clk_m_a1_osc_prediv>, - <&clk_m_a1_pll0 1>, /* PLL0 PHI1 */ - <&clk_m_a1_pll1 1>; /* PLL1 PHI1 */ - - clock-output-names = "clk-m-rx-icn-ts", - "clk-m-rx-icn-vdp-0", - "", /* Unused */ - "clk-m-prv-t1-bus", - "clk-m-icn-reg-12", - "clk-m-icn-reg-10", - "", /* Unused */ - "clk-m-icn-st231"; - }; - - clk_m_a1_div2: clk-m-a1-div2 { - #clock-cells = <1>; - compatible = "st,clkgena-divmux-c32-odf2", - "st,clkgena-divmux"; - - clocks = <&clk_m_a1_osc_prediv>, - <&clk_m_a1_pll0 2>, /* PLL0 PHI2 */ - <&clk_m_a1_pll1 2>; /* PLL1 PHI2 */ - - clock-output-names = "clk-m-fvdp-proc-alt", - "clk-m-icn-reg-13", - "clk-m-tx-icn-gpu", - "clk-m-rx-icn-gpu", - "", /* Unused */ - "", /* Unused */ - "", /* clk-m-apb-pm-12 */ - ""; /* Unused */ - }; - - clk_m_a1_div3: clk-m-a1-div3 { - #clock-cells = <1>; - compatible = "st,clkgena-divmux-c32-odf3", - "st,clkgena-divmux"; - - clocks = <&clk_m_a1_osc_prediv>, - <&clk_m_a1_pll0 3>, /* PLL0 PHI3 */ - <&clk_m_a1_pll1 3>; /* PLL1 PHI3 */ - - clock-output-names = "", /* Unused */ - "", /* Unused */ - "", /* Unused */ - "", /* Unused */ - "", /* Unused */ - "", /* Unused */ - "", /* Unused */ - ""; /* clk-m-gpu-alt */ - }; - }; - - clk_m_a9_ext2f_div2: clk-m-a9-ext2f-div2 { - #clock-cells = <0>; - compatible = "fixed-factor-clock"; - clocks = <&clk_m_a0_div1 2>; - clock-div = <2>; - clock-mult = <1>; - }; - - clockgen-a@fd345000 { - reg = <0xfd345000 0xb50>; - - clk_m_a2_pll0: clk-m-a2-pll0 { - #clock-cells = <1>; - compatible = "st,plls-c32-a1x-0", "st,clkgen-plls-c32"; - - clocks = <&clk_sysin>; - - clock-output-names = "clk-m-a2-pll0-phi0", - "clk-m-a2-pll0-phi1", - "clk-m-a2-pll0-phi2", - "clk-m-a2-pll0-phi3"; - }; - - clk_m_a2_pll1: clk-m-a2-pll1 { - #clock-cells = <1>; - compatible = "st,plls-c32-a1x-1", "st,clkgen-plls-c32"; - - clocks = <&clk_sysin>; - - clock-output-names = "clk-m-a2-pll1-phi0", - "clk-m-a2-pll1-phi1", - "clk-m-a2-pll1-phi2", - "clk-m-a2-pll1-phi3"; - }; - - clk_m_a2_osc_prediv: clk-m-a2-osc-prediv { - #clock-cells = <0>; - compatible = "st,clkgena-prediv-c32", - "st,clkgena-prediv"; - - clocks = <&clk_sysin>; - - clock-output-names = "clk-m-a2-osc-prediv"; - }; - - clk_m_a2_div0: clk-m-a2-div0 { - #clock-cells = <1>; - compatible = "st,clkgena-divmux-c32-odf0", - "st,clkgena-divmux"; - - clocks = <&clk_m_a2_osc_prediv>, - <&clk_m_a2_pll0 0>, /* PLL0 PHI0 */ - <&clk_m_a2_pll1 0>; /* PLL1 PHI0 */ - - clock-output-names = "clk-m-vtac-main-phy", - "clk-m-vtac-aux-phy", - "clk-m-stac-phy", - "clk-m-stac-sys", - "", /* clk-m-mpestac-pg */ - "", /* clk-m-mpestac-wc */ - "", /* clk-m-mpevtacaux-pg*/ - ""; /* clk-m-mpevtacmain-pg*/ - }; - - clk_m_a2_div1: clk-m-a2-div1 { - #clock-cells = <1>; - compatible = "st,clkgena-divmux-c32-odf1", - "st,clkgena-divmux"; - - clocks = <&clk_m_a2_osc_prediv>, - <&clk_m_a2_pll0 1>, /* PLL0 PHI1 */ - <&clk_m_a2_pll1 1>; /* PLL1 PHI1 */ - - clock-output-names = "", /* clk-m-mpevtacrx0-wc */ - "", /* clk-m-mpevtacrx1-wc */ - "clk-m-compo-main", - "clk-m-compo-aux", - "clk-m-bdisp-0", - "clk-m-bdisp-1", - "clk-m-icn-bdisp", - "clk-m-icn-compo"; - }; - - clk_m_a2_div2: clk-m-a2-div2 { - #clock-cells = <1>; - compatible = "st,clkgena-divmux-c32-odf2", - "st,clkgena-divmux"; - - clocks = <&clk_m_a2_osc_prediv>, - <&clk_m_a2_pll0 2>, /* PLL0 PHI2 */ - <&clk_m_a2_pll1 2>; /* PLL1 PHI2 */ - - clock-output-names = "clk-m-icn-vdp-2", - "", /* Unused */ - "clk-m-icn-reg-14", - "clk-m-mdtp", - "clk-m-jpegdec", - "", /* Unused */ - "clk-m-dcephy-impctrl", - ""; /* Unused */ - }; - - clk_m_a2_div3: clk-m-a2-div3 { - #clock-cells = <1>; - compatible = "st,clkgena-divmux-c32-odf3", - "st,clkgena-divmux"; - - clocks = <&clk_m_a2_osc_prediv>, - <&clk_m_a2_pll0 3>, /* PLL0 PHI3 */ - <&clk_m_a2_pll1 3>; /* PLL1 PHI3 */ - - clock-output-names = "", /* Unused */ - ""; /* clk-m-apb-pm-11 */ - /* Remaining outputs unused */ - }; - }; - - /* - * A9 PLL - */ - clockgen-a9@fdde08b0 { - reg = <0xfdde08b0 0x70>; - - clockgen_a9_pll: clockgen-a9-pll { - #clock-cells = <1>; - compatible = "st,stih416-plls-c32-a9", "st,clkgen-plls-c32"; - - clocks = <&clk_sysin>; - clock-output-names = "clockgen-a9-pll-odf"; - }; - }; - - /* - * ARM CPU related clocks - */ - clk_m_a9: clk-m-a9@fdde08ac { - #clock-cells = <0>; - compatible = "st,stih416-clkgen-a9-mux", "st,clkgen-mux"; - reg = <0xfdde08ac 0x4>; - clocks = <&clockgen_a9_pll 0>, - <&clockgen_a9_pll 0>, - <&clk_m_a0_div1 2>, - <&clk_m_a9_ext2f_div2>; - }; - - /* - * ARM Peripheral clock for timers - */ - arm_periph_clk: clk-m-a9-periphs { - #clock-cells = <0>; - compatible = "fixed-factor-clock"; - clocks = <&clk_m_a9>; - clock-div = <2>; - clock-mult = <1>; - }; - - /* - * Frequency synthesizers on the SASG2 - */ - clockgen_b0: clockgen-b0@fee108b4 { - #clock-cells = <1>; - compatible = "st,stih416-quadfs216", "st,quadfs"; - reg = <0xfee108b4 0x44>; - - clocks = <&clk_sysin>; - clock-output-names = "clk-s-usb48", - "clk-s-dss", - "clk-s-stfe-frc-2", - "clk-s-thsens-scard"; - }; - - clockgen_b1: clockgen-b1@fe8308c4 { - #clock-cells = <1>; - compatible = "st,stih416-quadfs216", "st,quadfs"; - reg = <0xfe8308c4 0x44>; - - clocks = <&clk_sysin>; - clock-output-names = "clk-s-pcm-0", - "clk-s-pcm-1", - "clk-s-pcm-2", - "clk-s-pcm-3"; - }; - - clockgen_c: clockgen-c@fe8307d0 { - #clock-cells = <1>; - compatible = "st,stih416-quadfs432", "st,quadfs"; - reg = <0xfe8307d0 0x44>; - - clocks = <&clk_sysin>; - clock-output-names = "clk-s-c-fs0-ch0", - "clk-s-c-vcc-sd", - "clk-s-c-fs0-ch2"; - }; - - clk_s_vcc_hd: clk-s-vcc-hd@fe8308b8 { - #clock-cells = <0>; - compatible = "st,stih416-clkgenc-vcc-hd", "st,clkgen-mux"; - reg = <0xfe8308b8 0x4>; /* SYSCFG2558 */ - - clocks = <&clk_sysin>, - <&clockgen_c 0>; - }; - - /* - * Add a dummy clock for the HDMI PHY for the VCC input mux - */ - clk_s_tmds_fromphy: clk-s-tmds-fromphy { - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-frequency = <0>; - }; - - clockgen_c_vcc: clockgen-c-vcc@fe8308ac { - #clock-cells = <1>; - compatible = "st,stih416-clkgenc", "st,clkgen-vcc"; - reg = <0xfe8308ac 0xc>; /* SYSCFG2555,2556,2557 */ - - clocks = <&clk_s_vcc_hd>, - <&clockgen_c 1>, - <&clk_s_tmds_fromphy>, - <&clockgen_c 2>; - - clock-output-names = "clk-s-pix-hdmi", - "clk-s-pix-dvo", - "clk-s-out-dvo", - "clk-s-pix-hd", - "clk-s-hddac", - "clk-s-denc", - "clk-s-sddac", - "clk-s-pix-main", - "clk-s-pix-aux", - "clk-s-stfe-frc-0", - "clk-s-ref-mcru", - "clk-s-slave-mcru", - "clk-s-tmds-hdmi", - "clk-s-hdmi-reject-pll", - "clk-s-thsens"; - }; - - clockgen_d: clockgen-d@fee107e0 { - #clock-cells = <1>; - compatible = "st,stih416-quadfs216", "st,quadfs"; - reg = <0xfee107e0 0x44>; - - clocks = <&clk_sysin>; - clock-output-names = "clk-s-ccsc", - "clk-s-stfe-frc-1", - "clk-s-tsout-1", - "clk-s-mchi"; - }; - - /* - * Frequency synthesizers on the MPE42 - */ - clockgen_e: clockgen-e@fd3208bc { - #clock-cells = <1>; - compatible = "st,stih416-quadfs660-E", "st,quadfs"; - reg = <0xfd3208bc 0xb0>; - - clocks = <&clk_sysin>; - clock-output-names = "clk-m-pix-mdtp-0", - "clk-m-pix-mdtp-1", - "clk-m-pix-mdtp-2", - "clk-m-mpelpc"; - }; - - clockgen_f: clockgen-f@fd320878 { - #clock-cells = <1>; - compatible = "st,stih416-quadfs660-F", "st,quadfs"; - reg = <0xfd320878 0xf0>; - - clocks = <&clk_sysin>; - clock-output-names = "clk-m-main-vidfs", - "clk-m-hva-fs", - "clk-m-fvdp-vcpu", - "clk-m-fvdp-proc-fs"; - }; - - clk_m_fvdp_proc: clk-m-fvdp-proc@fd320910 { - #clock-cells = <0>; - compatible = "st,stih416-clkgenf-vcc-fvdp", "st,clkgen-mux"; - reg = <0xfd320910 0x4>; /* SYSCFG8580 */ - - clocks = <&clk_m_a1_div2 0>, - <&clockgen_f 3>; - }; - - clk_m_hva: clk-m-hva@fd690868 { - #clock-cells = <0>; - compatible = "st,stih416-clkgenf-vcc-hva", "st,clkgen-mux"; - reg = <0xfd690868 0x4>; /* SYSCFG9538 */ - - clocks = <&clockgen_f 1>, - <&clk_m_a1_div0 3>; - }; - - clk_m_f_vcc_hd: clk-m-f-vcc-hd@fd32086c { - #clock-cells = <0>; - compatible = "st,stih416-clkgenf-vcc-hd", "st,clkgen-mux"; - reg = <0xfd32086c 0x4>; /* SYSCFG8539 */ - - clocks = <&clockgen_c_vcc 7>, - <&clockgen_f 0>; - }; - - clk_m_f_vcc_sd: clk-m-f-vcc-sd@fd32086c { - #clock-cells = <0>; - compatible = "st,stih416-clkgenf-vcc-sd", "st,clkgen-mux"; - reg = <0xfd32086c 0x4>; /* SYSCFG8539 */ - - clocks = <&clockgen_c_vcc 8>, - <&clockgen_f 1>; - }; - - /* - * Add a dummy clock for the HDMIRx external signal clock - */ - clk_m_pix_hdmirx_sas: clk-m-pix-hdmirx-sas { - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-frequency = <0>; - }; - - clockgen_f_vcc: clockgen-f-vcc@fd32086c { - #clock-cells = <1>; - compatible = "st,stih416-clkgenf", "st,clkgen-vcc"; - reg = <0xfd32086c 0xc>; /* SYSCFG8539,8540,8541 */ - - clocks = <&clk_m_f_vcc_hd>, - <&clk_m_f_vcc_sd>, - <&clockgen_f 0>, - <&clk_m_pix_hdmirx_sas>; - - clock-output-names = "clk-m-pix-main-pipe", - "clk-m-pix-aux-pipe", - "clk-m-pix-main-cru", - "clk-m-pix-aux-cru", - "clk-m-xfer-be-compo", - "clk-m-xfer-pip-compo", - "clk-m-xfer-aux-compo", - "clk-m-vsens", - "clk-m-pix-hdmirx-0", - "clk-m-pix-hdmirx-1"; - }; - - /* - * DDR PLL - */ - clockgen-ddr@0xfdde07d8 { - reg = <0xfdde07d8 0x110>; - - clockgen_ddr_pll: clockgen-ddr-pll { - #clock-cells = <1>; - compatible = "st,stih416-plls-c32-ddr", "st,clkgen-plls-c32"; - - clocks = <&clk_sysin>; - clock-output-names = "clockgen-ddr0", - "clockgen-ddr1"; - }; - }; - - /* - * GPU PLL - */ - clockgen-gpu@fd68ff00 { - reg = <0xfd68ff00 0x910>; - - clockgen_gpu_pll: clockgen-gpu-pll { - #clock-cells = <1>; - compatible = "st,stih416-gpu-pll-c32", "st,clkgengpu-pll-c32"; - - clocks = <&clk_sysin>; - clock-output-names = "clockgen-gpu-pll"; - }; - }; - }; -}; diff --git a/arch/arm/boot/dts/stih416-pinctrl.dtsi b/arch/arm/boot/dts/stih416-pinctrl.dtsi deleted file mode 100644 index 9c97f7e651a0..000000000000 --- a/arch/arm/boot/dts/stih416-pinctrl.dtsi +++ /dev/null @@ -1,692 +0,0 @@ - -/* - * Copyright (C) 2013 STMicroelectronics Limited. - * Author: Srinivas Kandagatla <srinivas.kandagatla@st.com> - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * publishhed by the Free Software Foundation. - */ -#include "st-pincfg.h" -#include <dt-bindings/interrupt-controller/arm-gic.h> -/ { - - aliases { - gpio0 = &pio0; - gpio1 = &pio1; - gpio2 = &pio2; - gpio3 = &pio3; - gpio4 = &pio4; - gpio5 = &pio40; - gpio6 = &pio5; - gpio7 = &pio6; - gpio8 = &pio7; - gpio9 = &pio8; - gpio10 = &pio9; - gpio11 = &pio10; - gpio12 = &pio11; - gpio13 = &pio12; - gpio14 = &pio30; - gpio15 = &pio31; - gpio16 = &pio13; - gpio17 = &pio14; - gpio18 = &pio15; - gpio19 = &pio16; - gpio20 = &pio17; - gpio21 = &pio18; - gpio22 = &pio100; - gpio23 = &pio101; - gpio24 = &pio102; - gpio25 = &pio103; - gpio26 = &pio104; - gpio27 = &pio105; - gpio28 = &pio106; - gpio29 = &pio107; - }; - - soc { - pin-controller-sbc { - #address-cells = <1>; - #size-cells = <1>; - compatible = "st,stih416-sbc-pinctrl"; - st,syscfg = <&syscfg_sbc>; - reg = <0xfe61f080 0x4>; - reg-names = "irqmux"; - interrupts = <GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH>; - interrupt-names = "irqmux"; - ranges = <0 0xfe610000 0x6000>; - - pio0: gpio@fe610000 { - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - reg = <0 0x100>; - st,bank-name = "PIO0"; - }; - pio1: gpio@fe611000 { - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - reg = <0x1000 0x100>; - st,bank-name = "PIO1"; - }; - pio2: gpio@fe612000 { - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - reg = <0x2000 0x100>; - st,bank-name = "PIO2"; - }; - pio3: gpio@fe613000 { - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - reg = <0x3000 0x100>; - st,bank-name = "PIO3"; - }; - pio4: gpio@fe614000 { - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - reg = <0x4000 0x100>; - st,bank-name = "PIO4"; - }; - pio40: gpio@fe615000 { - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - reg = <0x5000 0x100>; - st,bank-name = "PIO40"; - st,retime-pin-mask = <0x7f>; - }; - - rc{ - pinctrl_ir: ir0 { - st,pins { - ir = <&pio4 0 ALT2 IN>; - }; - }; - }; - sbc_serial1 { - pinctrl_sbc_serial1: sbc_serial1 { - st,pins { - tx = <&pio2 6 ALT3 OUT>; - rx = <&pio2 7 ALT3 IN>; - }; - }; - }; - - keyscan { - pinctrl_keyscan: keyscan { - st,pins { - keyin0 = <&pio0 2 ALT2 IN>; - keyin1 = <&pio0 3 ALT2 IN>; - keyin2 = <&pio0 4 ALT2 IN>; - keyin3 = <&pio2 6 ALT2 IN>; - - keyout0 = <&pio1 6 ALT2 OUT>; - keyout1 = <&pio1 7 ALT2 OUT>; - keyout2 = <&pio0 6 ALT2 OUT>; - keyout3 = <&pio2 7 ALT2 OUT>; - }; - }; - }; - - sbc_i2c0 { - pinctrl_sbc_i2c0_default: sbc_i2c0-default { - st,pins { - sda = <&pio4 6 ALT1 BIDIR>; - scl = <&pio4 5 ALT1 BIDIR>; - }; - }; - }; - - usb { - pinctrl_usb3: usb3 { - st,pins { - oc-detect = <&pio40 0 ALT1 IN>; - pwr-enable = <&pio40 1 ALT1 OUT>; - }; - }; - }; - - sbc_i2c1 { - pinctrl_sbc_i2c1_default: sbc_i2c1-default { - st,pins { - sda = <&pio3 2 ALT2 BIDIR>; - scl = <&pio3 1 ALT2 BIDIR>; - }; - }; - }; - - gmac1 { - pinctrl_mii1: mii1 { - st,pins { - txd0 = <&pio0 0 ALT1 OUT SE_NICLK_IO 0 CLK_A>; - txd1 = <&pio0 1 ALT1 OUT SE_NICLK_IO 0 CLK_A>; - txd2 = <&pio0 2 ALT1 OUT SE_NICLK_IO 0 CLK_A>; - txd3 = <&pio0 3 ALT1 OUT SE_NICLK_IO 0 CLK_A>; - txer = <&pio0 4 ALT1 OUT SE_NICLK_IO 0 CLK_A>; - txen = <&pio0 5 ALT1 OUT SE_NICLK_IO 0 CLK_A>; - txclk = <&pio0 6 ALT1 IN NICLK 0 CLK_A>; - col = <&pio0 7 ALT1 IN BYPASS 1000>; - - mdio = <&pio1 0 ALT1 OUT BYPASS 1500>; - mdc = <&pio1 1 ALT1 OUT NICLK 0 CLK_A>; - crs = <&pio1 2 ALT1 IN BYPASS 1000>; - mdint = <&pio1 3 ALT1 IN BYPASS 0>; - rxd0 = <&pio1 4 ALT1 IN SE_NICLK_IO 0 CLK_A>; - rxd1 = <&pio1 5 ALT1 IN SE_NICLK_IO 0 CLK_A>; - rxd2 = <&pio1 6 ALT1 IN SE_NICLK_IO 0 CLK_A>; - rxd3 = <&pio1 7 ALT1 IN SE_NICLK_IO 0 CLK_A>; - - rxdv = <&pio2 0 ALT1 IN SE_NICLK_IO 0 CLK_A>; - rx_er = <&pio2 1 ALT1 IN SE_NICLK_IO 0 CLK_A>; - rxclk = <&pio2 2 ALT1 IN NICLK 0 CLK_A>; - phyclk = <&pio2 3 ALT1 OUT NICLK 0 CLK_A>; - }; - }; - pinctrl_rgmii1: rgmii1-0 { - st,pins { - txd0 = <&pio0 0 ALT1 OUT DE_IO 500 CLK_A>; - txd1 = <&pio0 1 ALT1 OUT DE_IO 500 CLK_A>; - txd2 = <&pio0 2 ALT1 OUT DE_IO 500 CLK_A>; - txd3 = <&pio0 3 ALT1 OUT DE_IO 500 CLK_A>; - txen = <&pio0 5 ALT1 OUT DE_IO 0 CLK_A>; - txclk = <&pio0 6 ALT1 IN NICLK 0 CLK_A>; - - mdio = <&pio1 0 ALT1 OUT BYPASS 0>; - mdc = <&pio1 1 ALT1 OUT NICLK 0 CLK_A>; - rxd0 = <&pio1 4 ALT1 IN DE_IO 500 CLK_A>; - rxd1 = <&pio1 5 ALT1 IN DE_IO 500 CLK_A>; - rxd2 = <&pio1 6 ALT1 IN DE_IO 500 CLK_A>; - rxd3 = <&pio1 7 ALT1 IN DE_IO 500 CLK_A>; - - rxdv = <&pio2 0 ALT1 IN DE_IO 500 CLK_A>; - rxclk = <&pio2 2 ALT1 IN NICLK 0 CLK_A>; - phyclk = <&pio2 3 ALT4 OUT NICLK 0 CLK_B>; - - clk125= <&pio3 7 ALT4 IN NICLK 0 CLK_A>; - }; - }; - }; - - pwm1 { - pinctrl_pwm1_chan0_default: pwm1-0-default { - st,pins { - pwm-out = <&pio3 0 ALT1 OUT>; - pwm-capturein = <&pio3 2 ALT1 IN>; - - }; - }; - pinctrl_pwm1_chan1_default: pwm1-1-default { - st,pins { - pwm-out = <&pio4 4 ALT1 OUT>; - pwm-capturein = <&pio4 3 ALT1 IN>; - }; - }; - pinctrl_pwm1_chan2_default: pwm1-2-default { - st,pins { - pwm-out = <&pio4 6 ALT3 OUT>; - }; - }; - pinctrl_pwm1_chan3_default: pwm1-3-default { - st,pins { - pwm-out = <&pio4 7 ALT3 OUT>; - }; - }; - }; - }; - - pin-controller-front { - #address-cells = <1>; - #size-cells = <1>; - compatible = "st,stih416-front-pinctrl"; - st,syscfg = <&syscfg_front>; - reg = <0xfee0f080 0x4>; - reg-names = "irqmux"; - interrupts = <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>; - interrupt-names = "irqmux"; - ranges = <0 0xfee00000 0x10000>; - - pio5: gpio@fee00000 { - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - reg = <0 0x100>; - st,bank-name = "PIO5"; - }; - pio6: gpio@fee01000 { - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - reg = <0x1000 0x100>; - st,bank-name = "PIO6"; - }; - pio7: gpio@fee02000 { - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - reg = <0x2000 0x100>; - st,bank-name = "PIO7"; - }; - pio8: gpio@fee03000 { - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - reg = <0x3000 0x100>; - st,bank-name = "PIO8"; - }; - pio9: gpio@fee04000 { - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - reg = <0x4000 0x100>; - st,bank-name = "PIO9"; - }; - pio10: gpio@fee05000 { - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - reg = <0x5000 0x100>; - st,bank-name = "PIO10"; - }; - pio11: gpio@fee06000 { - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - reg = <0x6000 0x100>; - st,bank-name = "PIO11"; - }; - pio12: gpio@fee07000 { - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - reg = <0x7000 0x100>; - st,bank-name = "PIO12"; - }; - pio30: gpio@fee08000 { - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - reg = <0x8000 0x100>; - st,bank-name = "PIO30"; - }; - pio31: gpio@fee09000 { - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - reg = <0x9000 0x100>; - st,bank-name = "PIO31"; - }; - - pwm0 { - pinctrl_pwm0_chan0_default: pwm0-0-default { - st,pins { - pwm-out = <&pio9 7 ALT2 OUT>; - pwm-capturein = <&pio9 6 ALT2 IN>; - }; - }; - }; - - serial2-oe { - pinctrl_serial2_oe: serial2-1 { - st,pins { - output-enable = <&pio11 3 ALT2 OUT>; - }; - }; - }; - - i2c0 { - pinctrl_i2c0_default: i2c0-default { - st,pins { - sda = <&pio9 3 ALT1 BIDIR>; - scl = <&pio9 2 ALT1 BIDIR>; - }; - }; - }; - - usb { - pinctrl_usb0: usb0 { - st,pins { - oc-detect = <&pio9 4 ALT1 IN>; - pwr-enable = <&pio9 5 ALT1 OUT>; - }; - }; - }; - - - i2c1 { - pinctrl_i2c1_default: i2c1-default { - st,pins { - sda = <&pio12 1 ALT1 BIDIR>; - scl = <&pio12 0 ALT1 BIDIR>; - }; - }; - }; - - fsm { - pinctrl_fsm: fsm { - st,pins { - spi-fsm-clk = <&pio12 2 ALT1 OUT>; - spi-fsm-cs = <&pio12 3 ALT1 OUT>; - spi-fsm-mosi = <&pio12 4 ALT1 OUT>; - spi-fsm-miso = <&pio12 5 ALT1 IN>; - spi-fsm-hol = <&pio12 6 ALT1 OUT>; - spi-fsm-wp = <&pio12 7 ALT1 OUT>; - }; - }; - }; - }; - - pin-controller-rear { - #address-cells = <1>; - #size-cells = <1>; - compatible = "st,stih416-rear-pinctrl"; - st,syscfg = <&syscfg_rear>; - reg = <0xfe82f080 0x4>; - reg-names = "irqmux"; - interrupts = <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>; - interrupt-names = "irqmux"; - ranges = <0 0xfe820000 0x6000>; - - pio13: gpio@fe820000 { - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - reg = <0 0x100>; - st,bank-name = "PIO13"; - }; - pio14: gpio@fe821000 { - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - reg = <0x1000 0x100>; - st,bank-name = "PIO14"; - }; - pio15: gpio@fe822000 { - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - reg = <0x2000 0x100>; - st,bank-name = "PIO15"; - }; - pio16: gpio@fe823000 { - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - reg = <0x3000 0x100>; - st,bank-name = "PIO16"; - }; - pio17: gpio@fe824000 { - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - reg = <0x4000 0x100>; - st,bank-name = "PIO17"; - }; - pio18: gpio@fe825000 { - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - reg = <0x5000 0x100>; - st,bank-name = "PIO18"; - st,retime-pin-mask = <0xf>; - }; - - serial2 { - pinctrl_serial2: serial2-0 { - st,pins { - tx = <&pio17 4 ALT2 OUT>; - rx = <&pio17 5 ALT2 IN>; - }; - }; - }; - - gmac0 { - pinctrl_mii0: mii0 { - st,pins { - mdint = <&pio13 6 ALT2 IN BYPASS 0>; - txen = <&pio13 7 ALT2 OUT SE_NICLK_IO 0 CLK_A>; - txd0 = <&pio14 0 ALT2 OUT SE_NICLK_IO 0 CLK_A>; - txd1 = <&pio14 1 ALT2 OUT SE_NICLK_IO 0 CLK_A>; - txd2 = <&pio14 2 ALT2 OUT SE_NICLK_IO 0 CLK_B>; - txd3 = <&pio14 3 ALT2 OUT SE_NICLK_IO 0 CLK_B>; - - txclk = <&pio15 0 ALT2 IN NICLK 0 CLK_A>; - txer = <&pio15 1 ALT2 OUT SE_NICLK_IO 0 CLK_A>; - crs = <&pio15 2 ALT2 IN BYPASS 1000>; - col = <&pio15 3 ALT2 IN BYPASS 1000>; - mdio= <&pio15 4 ALT2 OUT BYPASS 1500>; - mdc = <&pio15 5 ALT2 OUT NICLK 0 CLK_B>; - - rxd0 = <&pio16 0 ALT2 IN SE_NICLK_IO 0 CLK_A>; - rxd1 = <&pio16 1 ALT2 IN SE_NICLK_IO 0 CLK_A>; - rxd2 = <&pio16 2 ALT2 IN SE_NICLK_IO 0 CLK_A>; - rxd3 = <&pio16 3 ALT2 IN SE_NICLK_IO 0 CLK_A>; - rxdv = <&pio15 6 ALT2 IN SE_NICLK_IO 0 CLK_A>; - rx_er = <&pio15 7 ALT2 IN SE_NICLK_IO 0 CLK_A>; - rxclk = <&pio17 0 ALT2 IN NICLK 0 CLK_A>; - phyclk = <&pio13 5 ALT2 OUT NICLK 0 CLK_B>; - }; - }; - - pinctrl_gmii0: gmii0 { - st,pins { - }; - }; - pinctrl_rgmii0: rgmii0 { - st,pins { - phyclk = <&pio13 5 ALT4 OUT NICLK 0 CLK_B>; - txen = <&pio13 7 ALT2 OUT DE_IO 0 CLK_A>; - txd0 = <&pio14 0 ALT2 OUT DE_IO 500 CLK_A>; - txd1 = <&pio14 1 ALT2 OUT DE_IO 500 CLK_A>; - txd2 = <&pio14 2 ALT2 OUT DE_IO 500 CLK_B>; - txd3 = <&pio14 3 ALT2 OUT DE_IO 500 CLK_B>; - txclk = <&pio15 0 ALT2 IN NICLK 0 CLK_A>; - - mdio = <&pio15 4 ALT2 OUT BYPASS 0>; - mdc = <&pio15 5 ALT2 OUT NICLK 0 CLK_B>; - - rxdv = <&pio15 6 ALT2 IN DE_IO 500 CLK_A>; - rxd0 =<&pio16 0 ALT2 IN DE_IO 500 CLK_A>; - rxd1 =<&pio16 1 ALT2 IN DE_IO 500 CLK_A>; - rxd2 =<&pio16 2 ALT2 IN DE_IO 500 CLK_A>; - rxd3 =<&pio16 3 ALT2 IN DE_IO 500 CLK_A>; - rxclk =<&pio17 0 ALT2 IN NICLK 0 CLK_A>; - - clk125=<&pio17 6 ALT1 IN NICLK 0 CLK_A>; - }; - }; - }; - - mmc0 { - pinctrl_mmc0: mmc0 { - st,pins { - mmcclk = <&pio13 4 ALT4 BIDIR_PU NICLK 0 CLK_B>; - data0 = <&pio14 4 ALT4 BIDIR_PU BYPASS 0>; - data1 = <&pio14 5 ALT4 BIDIR_PU BYPASS 0>; - data2 = <&pio14 6 ALT4 BIDIR_PU BYPASS 0>; - data3 = <&pio14 7 ALT4 BIDIR_PU BYPASS 0>; - cmd = <&pio15 1 ALT4 BIDIR_PU BYPASS 0>; - wp = <&pio15 3 ALT4 IN>; - data4 = <&pio16 4 ALT4 BIDIR_PU BYPASS 0>; - data5 = <&pio16 5 ALT4 BIDIR_PU BYPASS 0>; - data6 = <&pio16 6 ALT4 BIDIR_PU BYPASS 0>; - data7 = <&pio16 7 ALT4 BIDIR_PU BYPASS 0>; - pwr = <&pio17 1 ALT4 OUT>; - cd = <&pio17 2 ALT4 IN>; - led = <&pio17 3 ALT4 OUT>; - }; - }; - }; - mmc1 { - pinctrl_mmc1: mmc1 { - st,pins { - mmcclk = <&pio15 0 ALT3 BIDIR_PU NICLK 0 CLK_B>; - data0 = <&pio13 7 ALT3 BIDIR_PU BYPASS 0>; - data1 = <&pio14 1 ALT3 BIDIR_PU BYPASS 0>; - data2 = <&pio14 2 ALT3 BIDIR_PU BYPASS 0>; - data3 = <&pio14 3 ALT3 BIDIR_PU BYPASS 0>; - cmd = <&pio15 4 ALT3 BIDIR_PU BYPASS 0>; - data4 = <&pio15 6 ALT3 BIDIR_PU BYPASS 0>; - data5 = <&pio15 7 ALT3 BIDIR_PU BYPASS 0>; - data6 = <&pio16 0 ALT3 BIDIR_PU BYPASS 0>; - data7 = <&pio16 1 ALT3 BIDIR_PU BYPASS 0>; - pwr = <&pio16 2 ALT3 OUT>; - nreset = <&pio13 6 ALT3 OUT>; - }; - }; - }; - - usb { - pinctrl_usb1: usb1 { - st,pins { - oc-detect = <&pio18 0 ALT1 IN>; - pwr-enable = <&pio18 1 ALT1 OUT>; - }; - }; - pinctrl_usb2: usb2 { - st,pins { - oc-detect = <&pio18 2 ALT1 IN>; - pwr-enable = <&pio18 3 ALT1 OUT>; - }; - }; - }; - - pwm0 { - pinctrl_pwm0_chan1_default: pwm0-1-default { - st,pins { - pwm-out = <&pio13 2 ALT2 OUT>; - pwm-capturein = <&pio13 1 ALT2 IN>; - }; - }; - pinctrl_pwm0_chan2_default: pwm0-2-default { - st,pins { - pwm-out = <&pio15 2 ALT4 OUT>; - }; - }; - pinctrl_pwm0_chan3_default: pwm0-3-default { - st,pins { - pwm-out = <&pio17 4 ALT1 OUT>; - }; - }; - }; - - }; - - pin-controller-fvdp-fe { - #address-cells = <1>; - #size-cells = <1>; - compatible = "st,stih416-fvdp-fe-pinctrl"; - st,syscfg = <&syscfg_fvdp_fe>; - reg = <0xfd6bf080 0x4>; - reg-names = "irqmux"; - interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>; - interrupt-names = "irqmux"; - ranges = <0 0xfd6b0000 0x3000>; - - pio100: gpio@fd6b0000 { - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - reg = <0 0x100>; - st,bank-name = "PIO100"; - }; - pio101: gpio@fd6b1000 { - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - reg = <0x1000 0x100>; - st,bank-name = "PIO101"; - }; - pio102: gpio@fd6b2000 { - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - reg = <0x2000 0x100>; - st,bank-name = "PIO102"; - }; - }; - - pin-controller-fvdp-lite { - #address-cells = <1>; - #size-cells = <1>; - compatible = "st,stih416-fvdp-lite-pinctrl"; - st,syscfg = <&syscfg_fvdp_lite>; - reg = <0xfd33f080 0x4>; - reg-names = "irqmux"; - interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>; - interrupt-names = "irqmux"; - ranges = <0 0xfd330000 0x5000>; - - pio103: gpio@fd330000 { - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - reg = <0 0x100>; - st,bank-name = "PIO103"; - }; - pio104: gpio@fd331000 { - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - reg = <0x1000 0x100>; - st,bank-name = "PIO104"; - }; - pio105: gpio@fd332000 { - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - reg = <0x2000 0x100>; - st,bank-name = "PIO105"; - }; - pio106: gpio@fd333000 { - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - reg = <0x3000 0x100>; - st,bank-name = "PIO106"; - }; - - pio107: gpio@fd334000 { - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - reg = <0x4000 0x100>; - st,bank-name = "PIO107"; - st,retime-pin-mask = <0xf>; - }; - }; - }; -}; diff --git a/arch/arm/boot/dts/stih416.dtsi b/arch/arm/boot/dts/stih416.dtsi deleted file mode 100644 index fe1f9cf770e4..000000000000 --- a/arch/arm/boot/dts/stih416.dtsi +++ /dev/null @@ -1,517 +0,0 @@ -/* - * Copyright (C) 2012 STMicroelectronics Limited. - * Author: Srinivas Kandagatla <srinivas.kandagatla@st.com> - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * publishhed by the Free Software Foundation. - */ -#include "stih41x.dtsi" -#include "stih416-clock.dtsi" -#include "stih416-pinctrl.dtsi" - -#include <dt-bindings/phy/phy.h> -#include <dt-bindings/interrupt-controller/arm-gic.h> -#include <dt-bindings/reset/stih416-resets.h> -#include <dt-bindings/interrupt-controller/irq-st.h> -/ { - L2: cache-controller { - compatible = "arm,pl310-cache"; - reg = <0xfffe2000 0x1000>; - arm,data-latency = <3 3 3>; - arm,tag-latency = <2 2 2>; - cache-unified; - cache-level = <2>; - }; - - arm-pmu { - compatible = "arm,cortex-a9-pmu"; - interrupt-parent = <&intc>; - interrupts = <GIC_PPI 15 IRQ_TYPE_LEVEL_HIGH>; - }; - - soc { - #address-cells = <1>; - #size-cells = <1>; - interrupt-parent = <&intc>; - ranges; - compatible = "simple-bus"; - - restart { - compatible = "st,stih416-restart"; - st,syscfg = <&syscfg_sbc>; - status = "okay"; - }; - - powerdown: powerdown-controller { - #reset-cells = <1>; - compatible = "st,stih416-powerdown"; - }; - - softreset: softreset-controller { - #reset-cells = <1>; - compatible = "st,stih416-softreset"; - }; - - syscfg_sbc:sbc-syscfg@fe600000{ - compatible = "st,stih416-sbc-syscfg", "syscon"; - reg = <0xfe600000 0x1000>; - }; - - syscfg_front:front-syscfg@fee10000{ - compatible = "st,stih416-front-syscfg", "syscon"; - reg = <0xfee10000 0x1000>; - }; - - syscfg_rear:rear-syscfg@fe830000{ - compatible = "st,stih416-rear-syscfg", "syscon"; - reg = <0xfe830000 0x1000>; - }; - - /* MPE */ - syscfg_fvdp_fe:fvdp-fe-syscfg@fddf0000{ - compatible = "st,stih416-fvdp-fe-syscfg", "syscon"; - reg = <0xfddf0000 0x1000>; - }; - - syscfg_fvdp_lite:fvdp-lite-syscfg@fd6a0000{ - compatible = "st,stih416-fvdp-lite-syscfg", "syscon"; - reg = <0xfd6a0000 0x1000>; - }; - - syscfg_cpu:cpu-syscfg@fdde0000{ - compatible = "st,stih416-cpu-syscfg", "syscon"; - reg = <0xfdde0000 0x1000>; - }; - - syscfg_compo:compo-syscfg@fd320000{ - compatible = "st,stih416-compo-syscfg", "syscon"; - reg = <0xfd320000 0x1000>; - }; - - syscfg_transport:transport-syscfg@fd690000{ - compatible = "st,stih416-transport-syscfg", "syscon"; - reg = <0xfd690000 0x1000>; - }; - - syscfg_lpm:lpm-syscfg@fe4b5100{ - compatible = "st,stih416-lpm-syscfg", "syscon"; - reg = <0xfe4b5100 0x8>; - }; - - irq-syscfg { - compatible = "st,stih416-irq-syscfg"; - st,syscfg = <&syscfg_cpu>; - st,irq-device = <ST_IRQ_SYSCFG_PMU_0>, - <ST_IRQ_SYSCFG_PMU_1>; - st,fiq-device = <ST_IRQ_SYSCFG_DISABLED>, - <ST_IRQ_SYSCFG_DISABLED>; - }; - - serial2: serial@fed32000{ - compatible = "st,asc"; - status = "disabled"; - reg = <0xfed32000 0x2c>; - interrupts = <0 197 0>; - clocks = <&clk_s_a0_ls CLK_ICN_REG>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_serial2 &pinctrl_serial2_oe>; - }; - - /* SBC_UART1 */ - sbc_serial1: serial@fe531000 { - compatible = "st,asc"; - status = "disabled"; - reg = <0xfe531000 0x2c>; - interrupts = <0 210 0>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_sbc_serial1>; - clocks = <&clk_sysin>; - }; - - i2c@fed40000 { - compatible = "st,comms-ssc4-i2c"; - reg = <0xfed40000 0x110>; - interrupts = <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&clk_s_a0_ls CLK_ICN_REG>; - clock-names = "ssc"; - clock-frequency = <400000>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c0_default>; - - status = "disabled"; - }; - - i2c@fed41000 { - compatible = "st,comms-ssc4-i2c"; - reg = <0xfed41000 0x110>; - interrupts = <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&clk_s_a0_ls CLK_ICN_REG>; - clock-names = "ssc"; - clock-frequency = <400000>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c1_default>; - - status = "disabled"; - }; - - i2c@fe540000 { - compatible = "st,comms-ssc4-i2c"; - reg = <0xfe540000 0x110>; - interrupts = <GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&clk_sysin>; - clock-names = "ssc"; - clock-frequency = <400000>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_sbc_i2c0_default>; - - status = "disabled"; - }; - - i2c@fe541000 { - compatible = "st,comms-ssc4-i2c"; - reg = <0xfe541000 0x110>; - interrupts = <GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&clk_sysin>; - clock-names = "ssc"; - clock-frequency = <400000>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_sbc_i2c1_default>; - - status = "disabled"; - }; - - ethernet0: dwmac@fe810000 { - device_type = "network"; - compatible = "st,stih416-dwmac", "snps,dwmac", "snps,dwmac-3.710"; - status = "disabled"; - reg = <0xfe810000 0x8000>; - reg-names = "stmmaceth"; - - interrupts = <0 133 0>, <0 134 0>, <0 135 0>; - interrupt-names = "macirq", "eth_wake_irq", "eth_lpi"; - - snps,pbl = <32>; - snps,mixed-burst; - - st,syscon = <&syscfg_rear 0x8bc>; - resets = <&softreset STIH416_ETH0_SOFTRESET>; - reset-names = "stmmaceth"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_mii0>; - clock-names = "stmmaceth", "sti-ethclk"; - clocks = <&clk_s_a1_ls CLK_ICN_IF_2>, <&clk_s_a1_ls CLK_GMAC0_PHY>; - }; - - ethernet1: dwmac@fef08000 { - device_type = "network"; - compatible = "st,stih416-dwmac", "snps,dwmac", "snps,dwmac-3.710"; - status = "disabled"; - reg = <0xfef08000 0x8000>; - reg-names = "stmmaceth"; - interrupts = <0 136 0>, <0 137 0>, <0 138 0>; - interrupt-names = "macirq", "eth_wake_irq", "eth_lpi"; - - snps,pbl = <32>; - snps,mixed-burst; - - st,syscon = <&syscfg_sbc 0x7f0>; - - resets = <&softreset STIH416_ETH1_SOFTRESET>; - reset-names = "stmmaceth"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_mii1>; - clock-names = "stmmaceth", "sti-ethclk"; - clocks = <&clk_s_a0_ls CLK_ICN_REG>, <&clk_s_a0_ls CLK_ETH1_PHY>; - }; - - rc: rc@fe518000 { - compatible = "st,comms-irb"; - reg = <0xfe518000 0x234>; - interrupts = <0 203 0>; - rx-mode = "infrared"; - clocks = <&clk_sysin>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_ir>; - resets = <&softreset STIH416_IRB_SOFTRESET>; - }; - - /* FSM */ - spifsm: spifsm@fe902000 { - compatible = "st,spi-fsm"; - reg = <0xfe902000 0x1000>; - pinctrl-0 = <&pinctrl_fsm>; - - st,syscfg = <&syscfg_rear>; - st,boot-device-reg = <0x958>; - st,boot-device-spi = <0x1a>; - - status = "disabled"; - }; - - keyscan: keyscan@fe4b0000 { - compatible = "st,sti-keyscan"; - status = "disabled"; - reg = <0xfe4b0000 0x2000>; - interrupts = <GIC_SPI 212 IRQ_TYPE_NONE>; - clocks = <&clk_sysin>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_keyscan>; - resets = <&powerdown STIH416_KEYSCAN_POWERDOWN>, - <&softreset STIH416_KEYSCAN_SOFTRESET>; - }; - - temp0 { - compatible = "st,stih416-sas-thermal"; - clock-names = "thermal"; - clocks = <&clockgen_c_vcc 14>; - - status = "okay"; - }; - - temp1@fdfe8000 { - compatible = "st,stih416-mpe-thermal"; - reg = <0xfdfe8000 0x10>; - clocks = <&clockgen_e 3>; - clock-names = "thermal"; - interrupts = <GIC_SPI 23 IRQ_TYPE_EDGE_RISING>; - - status = "okay"; - }; - - mmc0: sdhci@fe81e000 { - compatible = "st,sdhci"; - status = "disabled"; - reg = <0xfe81e000 0x1000>; - interrupts = <GIC_SPI 127 IRQ_TYPE_NONE>; - interrupt-names = "mmcirq"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_mmc0>; - clock-names = "mmc"; - clocks = <&clk_s_a1_ls 1>; - }; - - mmc1: sdhci@fe81f000 { - compatible = "st,sdhci"; - status = "disabled"; - reg = <0xfe81f000 0x1000>; - interrupts = <GIC_SPI 128 IRQ_TYPE_NONE>; - interrupt-names = "mmcirq"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_mmc1>; - clock-names = "mmc"; - clocks = <&clk_s_a1_ls 8>; - }; - - miphy365x_phy: phy@fe382000 { - compatible = "st,miphy365x-phy"; - st,syscfg = <&syscfg_rear 0x824 0x828>; - #address-cells = <1>; - #size-cells = <1>; - ranges; - - phy_port0: port@fe382000 { - #phy-cells = <1>; - reg = <0xfe382000 0x100>, <0xfe394000 0x100>; - reg-names = "sata", "pcie"; - }; - - phy_port1: port@fe38a000 { - #phy-cells = <1>; - reg = <0xfe38a000 0x100>, <0xfe804000 0x100>; - reg-names = "sata", "pcie"; - }; - }; - - sata0: sata@fe380000 { - compatible = "st,sti-ahci"; - reg = <0xfe380000 0x1000>; - interrupts = <GIC_SPI 157 IRQ_TYPE_NONE>; - interrupt-names = "hostc"; - phys = <&phy_port0 PHY_TYPE_SATA>; - phy-names = "sata-phy"; - resets = <&powerdown STIH416_SATA0_POWERDOWN>, - <&softreset STIH416_SATA0_SOFTRESET>; - reset-names = "pwr-dwn", "sw-rst"; - clock-names = "ahci_clk"; - clocks = <&clk_s_a0_ls CLK_ICN_REG>; - - status = "disabled"; - }; - - usb2_phy: phy@0 { - compatible = "st,stih416-usb-phy"; - #phy-cells = <0>; - st,syscfg = <&syscfg_rear>; - clocks = <&clk_sysin>; - clock-names = "osc_phy"; - }; - - ehci0: usb@fe1ffe00 { - compatible = "st,st-ehci-300x"; - reg = <0xfe1ffe00 0x100>; - interrupts = <GIC_SPI 148 IRQ_TYPE_NONE>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usb0>; - clocks = <&clk_s_a1_ls 0>, - <&clockgen_b0 0>; - clock-names = "ic", "clk48"; - phys = <&usb2_phy>; - phy-names = "usb"; - resets = <&powerdown STIH416_USB0_POWERDOWN>, - <&softreset STIH416_USB0_SOFTRESET>; - reset-names = "power", "softreset"; - }; - - ohci0: usb@fe1ffc00 { - compatible = "st,st-ohci-300x"; - reg = <0xfe1ffc00 0x100>; - interrupts = <GIC_SPI 149 IRQ_TYPE_NONE>; - clocks = <&clk_s_a1_ls 0>, - <&clockgen_b0 0>; - clock-names = "ic", "clk48"; - phys = <&usb2_phy>; - phy-names = "usb"; - status = "okay"; - resets = <&powerdown STIH416_USB0_POWERDOWN>, - <&softreset STIH416_USB0_SOFTRESET>; - reset-names = "power", "softreset"; - }; - - ehci1: usb@fe203e00 { - compatible = "st,st-ehci-300x"; - reg = <0xfe203e00 0x100>; - interrupts = <GIC_SPI 150 IRQ_TYPE_NONE>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usb1>; - clocks = <&clk_s_a1_ls 0>, - <&clockgen_b0 0>; - clock-names = "ic", "clk48"; - phys = <&usb2_phy>; - phy-names = "usb"; - resets = <&powerdown STIH416_USB1_POWERDOWN>, - <&softreset STIH416_USB1_SOFTRESET>; - reset-names = "power", "softreset"; - }; - - ohci1: usb@fe203c00 { - compatible = "st,st-ohci-300x"; - reg = <0xfe203c00 0x100>; - interrupts = <GIC_SPI 151 IRQ_TYPE_NONE>; - clocks = <&clk_s_a1_ls 0>, - <&clockgen_b0 0>; - clock-names = "ic", "clk48"; - phys = <&usb2_phy>; - phy-names = "usb"; - resets = <&powerdown STIH416_USB1_POWERDOWN>, - <&softreset STIH416_USB1_SOFTRESET>; - reset-names = "power", "softreset"; - }; - - ehci2: usb@fe303e00 { - compatible = "st,st-ehci-300x"; - reg = <0xfe303e00 0x100>; - interrupts = <GIC_SPI 152 IRQ_TYPE_NONE>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usb2>; - clocks = <&clk_s_a1_ls 0>, - <&clockgen_b0 0>; - clock-names = "ic", "clk48"; - phys = <&usb2_phy>; - phy-names = "usb"; - resets = <&powerdown STIH416_USB2_POWERDOWN>, - <&softreset STIH416_USB2_SOFTRESET>; - reset-names = "power", "softreset"; - }; - - ohci2: usb@fe303c00 { - compatible = "st,st-ohci-300x"; - reg = <0xfe303c00 0x100>; - interrupts = <GIC_SPI 153 IRQ_TYPE_NONE>; - clocks = <&clk_s_a1_ls 0>, - <&clockgen_b0 0>; - clock-names = "ic", "clk48"; - phys = <&usb2_phy>; - phy-names = "usb"; - resets = <&powerdown STIH416_USB2_POWERDOWN>, - <&softreset STIH416_USB2_SOFTRESET>; - reset-names = "power", "softreset"; - }; - - ehci3: usb@fe343e00 { - compatible = "st,st-ehci-300x"; - reg = <0xfe343e00 0x100>; - interrupts = <GIC_SPI 154 IRQ_TYPE_NONE>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usb3>; - clocks = <&clk_s_a1_ls 0>, - <&clockgen_b0 0>; - clock-names = "ic", "clk48"; - phys = <&usb2_phy>; - phy-names = "usb"; - resets = <&powerdown STIH416_USB3_POWERDOWN>, - <&softreset STIH416_USB3_SOFTRESET>; - reset-names = "power", "softreset"; - }; - - ohci3: usb@fe343c00 { - compatible = "st,st-ohci-300x"; - reg = <0xfe343c00 0x100>; - interrupts = <GIC_SPI 155 IRQ_TYPE_NONE>; - clocks = <&clk_s_a1_ls 0>, - <&clockgen_b0 0>; - clock-names = "ic", "clk48"; - phys = <&usb2_phy>; - phy-names = "usb"; - resets = <&powerdown STIH416_USB3_POWERDOWN>, - <&softreset STIH416_USB3_SOFTRESET>; - reset-names = "power", "softreset"; - }; - - /* SAS PWM Module */ - pwm0: pwm@fed10000 { - compatible = "st,sti-pwm"; - status = "disabled"; - #pwm-cells = <2>; - reg = <0xfed10000 0x68>; - interrupts = <GIC_SPI 200 IRQ_TYPE_NONE>; - - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_pwm0_chan0_default - &pinctrl_pwm0_chan1_default - &pinctrl_pwm0_chan2_default - &pinctrl_pwm0_chan3_default>; - - clock-names = "pwm", "capture"; - clocks = <&clk_sysin>, <&clk_s_a0_ls CLK_ICN_REG>; - - st,pwm-num-chan = <4>; - st,capture-num-chan = <2>; - }; - - /* SBC PWM Module */ - pwm1: pwm@fe510000 { - compatible = "st,sti-pwm"; - status = "disabled"; - #pwm-cells = <2>; - reg = <0xfe510000 0x68>; - interrupts = <GIC_SPI 202 IRQ_TYPE_NONE>; - - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_pwm1_chan0_default - /* - * Shared with SBC_OBS_NOTRST. Don't - * enable unless you really know what - * you're doing. - * - * &pinctrl_pwm1_chan1_default - */ - &pinctrl_pwm1_chan2_default - &pinctrl_pwm1_chan3_default>; - - clock-names = "pwm"; - clocks = <&clk_sysin>; - st,pwm-num-chan = <3>; - }; - }; -}; diff --git a/arch/arm/boot/dts/stih41x-b2000.dtsi b/arch/arm/boot/dts/stih41x-b2000.dtsi deleted file mode 100644 index 9bfa0674b452..000000000000 --- a/arch/arm/boot/dts/stih41x-b2000.dtsi +++ /dev/null @@ -1,96 +0,0 @@ -/* - * Copyright (C) 2013 STMicroelectronics (R&D) Limited. - * Author: Srinivas Kandagatla <srinivas.kandagatla@st.com> - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * publishhed by the Free Software Foundation. - */ -#include <dt-bindings/input/input.h> -#include <dt-bindings/gpio/gpio.h> - -/ { - - memory{ - device_type = "memory"; - reg = <0x60000000 0x40000000>; - }; - - chosen { - bootargs = "console=ttyAS0,115200 clk_ignore_unused"; - linux,stdout-path = &serial2; - }; - - aliases { - ttyAS0 = &serial2; - ethernet0 = ðernet0; - ethernet1 = ðernet1; - }; - - soc { - serial2: serial@fed32000 { - status = "okay"; - }; - - leds { - compatible = "gpio-leds"; - fp_led { - label = "Front Panel LED"; - gpios = <&pio105 7 GPIO_ACTIVE_HIGH>; - linux,default-trigger = "heartbeat"; - }; - }; - - /* HDMI Tx I2C */ - i2c@fed41000 { - /* HDMI V1.3a supports Standard mode only */ - clock-frequency = <100000>; - i2c-min-scl-pulse-width-us = <0>; - i2c-min-sda-pulse-width-us = <5>; - - status = "okay"; - }; - - ethernet0: dwmac@fe810000 { - status = "okay"; - phy-mode = "mii"; - pinctrl-0 = <&pinctrl_mii0>; - - snps,reset-gpio = <&pio106 2>; - snps,reset-active-low; - snps,reset-delays-us = <0 10000 10000>; - }; - - ethernet1: dwmac@fef08000 { - status = "disabled"; - phy-mode = "mii"; - st,tx-retime-src = "txclk"; - - snps,reset-gpio = <&pio4 7>; - snps,reset-active-low; - snps,reset-delays-us = <0 10000 10000>; - }; - - keyscan: keyscan@fe4b0000 { - keypad,num-rows = <4>; - keypad,num-columns = <4>; - st,debounce-us = <5000>; - linux,keymap = < MATRIX_KEY(0x00, 0x00, KEY_F13) - MATRIX_KEY(0x00, 0x01, KEY_F9) - MATRIX_KEY(0x00, 0x02, KEY_F5) - MATRIX_KEY(0x00, 0x03, KEY_F1) - MATRIX_KEY(0x01, 0x00, KEY_F14) - MATRIX_KEY(0x01, 0x01, KEY_F10) - MATRIX_KEY(0x01, 0x02, KEY_F6) - MATRIX_KEY(0x01, 0x03, KEY_F2) - MATRIX_KEY(0x02, 0x00, KEY_F15) - MATRIX_KEY(0x02, 0x01, KEY_F11) - MATRIX_KEY(0x02, 0x02, KEY_F7) - MATRIX_KEY(0x02, 0x03, KEY_F3) - MATRIX_KEY(0x03, 0x00, KEY_F16) - MATRIX_KEY(0x03, 0x01, KEY_F12) - MATRIX_KEY(0x03, 0x02, KEY_F8) - MATRIX_KEY(0x03, 0x03, KEY_F4) >; - }; - }; -}; diff --git a/arch/arm/boot/dts/stih41x-b2020.dtsi b/arch/arm/boot/dts/stih41x-b2020.dtsi deleted file mode 100644 index 322e0e95176c..000000000000 --- a/arch/arm/boot/dts/stih41x-b2020.dtsi +++ /dev/null @@ -1,82 +0,0 @@ -/* - * Copyright (C) 2013 STMicroelectronics (R&D) Limited. - * Author: Srinivas Kandagatla <srinivas.kandagatla@st.com> - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * publishhed by the Free Software Foundation. - */ -#include "stih41x-b2020x.dtsi" -#include <dt-bindings/gpio/gpio.h> -/ { - memory{ - device_type = "memory"; - reg = <0x40000000 0x80000000>; - }; - - chosen { - bootargs = "console=ttyAS0,115200 clk_ignore_unused"; - linux,stdout-path = &sbc_serial1; - }; - - aliases { - ttyAS0 = &sbc_serial1; - ethernet1 = ðernet1; - }; - soc { - sbc_serial1: serial@fe531000 { - status = "okay"; - }; - - leds { - compatible = "gpio-leds"; - red { - label = "Front Panel LED"; - gpios = <&pio4 1 GPIO_ACTIVE_HIGH>; - linux,default-trigger = "heartbeat"; - }; - green { - gpios = <&pio4 7 GPIO_ACTIVE_HIGH>; - default-state = "off"; - }; - }; - - i2c@fed40000 { - status = "okay"; - }; - - /* HDMI Tx I2C */ - i2c@fed41000 { - /* HDMI V1.3a supports Standard mode only */ - clock-frequency = <100000>; - i2c-min-scl-pulse-width-us = <0>; - i2c-min-sda-pulse-width-us = <5>; - - status = "okay"; - }; - - i2c@fe540000 { - status = "okay"; - }; - - i2c@fe541000 { - status = "okay"; - }; - - ethernet1: dwmac@fef08000 { - status = "okay"; - phy-mode = "rgmii-id"; - max-speed = <1000>; - st,tx-retime-src = "clk_125"; - snps,reset-gpio = <&pio3 0>; - snps,reset-active-low; - snps,reset-delays-us = <0 10000 10000>; - - pinctrl-0 = <&pinctrl_rgmii1>; - }; - - mmc0: sdhci@fe81e000 { - bus-width = <8>; - }; - }; -}; diff --git a/arch/arm/boot/dts/stih41x-b2020x.dtsi b/arch/arm/boot/dts/stih41x-b2020x.dtsi deleted file mode 100644 index f797a0607382..000000000000 --- a/arch/arm/boot/dts/stih41x-b2020x.dtsi +++ /dev/null @@ -1,32 +0,0 @@ -/* - * Copyright (C) 2013 STMicroelectronics (R&D) Limited. - * Author: Lee Jones <lee.jones@linaro.org> - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * publishhed by the Free Software Foundation. - */ -/ { - soc { - mmc0: sdhci@fe81e000 { - status = "okay"; - }; - - spifsm: spifsm@fe902000 { - #address-cells = <1>; - #size-cells = <1>; - - status = "okay"; - - partition@0 { - label = "SerialFlash1"; - reg = <0x00000000 0x00500000>; - }; - - partition@500000 { - label = "SerialFlash2"; - reg = <0x00500000 0x00b00000>; - }; - }; - }; -}; diff --git a/arch/arm/boot/dts/stih41x.dtsi b/arch/arm/boot/dts/stih41x.dtsi deleted file mode 100644 index 5cb0e63376b5..000000000000 --- a/arch/arm/boot/dts/stih41x.dtsi +++ /dev/null @@ -1,47 +0,0 @@ -/* - * Copyright (C) 2014 STMicroelectronics Limited. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * publishhed by the Free Software Foundation. - */ -/ { - #address-cells = <1>; - #size-cells = <1>; - - cpus { - #address-cells = <1>; - #size-cells = <0>; - cpu@0 { - device_type = "cpu"; - compatible = "arm,cortex-a9"; - reg = <0>; - }; - cpu@1 { - device_type = "cpu"; - compatible = "arm,cortex-a9"; - reg = <1>; - }; - }; - - intc: interrupt-controller@fffe1000 { - compatible = "arm,cortex-a9-gic"; - #interrupt-cells = <3>; - interrupt-controller; - reg = <0xfffe1000 0x1000>, - <0xfffe0100 0x100>; - }; - - scu@fffe0000 { - compatible = "arm,cortex-a9-scu"; - reg = <0xfffe0000 0x1000>; - }; - - timer@fffe0200 { - interrupt-parent = <&intc>; - compatible = "arm,cortex-a9-global-timer"; - reg = <0xfffe0200 0x100>; - interrupts = <1 11 0x04>; - clocks = <&arm_periph_clk>; - }; -}; diff --git a/arch/arm/boot/dts/stihxxx-b2120.dtsi b/arch/arm/boot/dts/stihxxx-b2120.dtsi index ed2b7a99ecff..4b8f62f89664 100644 --- a/arch/arm/boot/dts/stihxxx-b2120.dtsi +++ b/arch/arm/boot/dts/stihxxx-b2120.dtsi @@ -135,6 +135,10 @@ }; }; + sti_uni_player0: sti-uni-player@8d80000 { + status = "okay"; + }; + sti_uni_player2: sti-uni-player@8d82000 { status = "okay"; }; @@ -151,13 +155,26 @@ sound { compatible = "simple-audio-card"; - simple-audio-card,name = "sti audio card"; + simple-audio-card,name = "STI-B2120"; status = "okay"; simple-audio-card,dai-link@0 { + /* HDMI */ + format = "i2s"; + mclk-fs = <128>; + cpu { + sound-dai = <&sti_uni_player0>; + }; + + codec { + sound-dai = <&sti_hdmi>; + }; + }; + simple-audio-card,dai-link@1 { /* DAC */ format = "i2s"; mclk-fs = <256>; + frame-inversion = <1>; cpu { sound-dai = <&sti_uni_player2>; }; @@ -166,7 +183,7 @@ sound-dai = <&sti_sasg_codec 1>; }; }; - simple-audio-card,dai-link@1 { + simple-audio-card,dai-link@2 { /* SPDIF */ format = "left_j"; mclk-fs = <128>; diff --git a/arch/arm/boot/dts/stm32429i-eval.dts b/arch/arm/boot/dts/stm32429i-eval.dts index 6bfc5959dac3..5436e880e28f 100644 --- a/arch/arm/boot/dts/stm32429i-eval.dts +++ b/arch/arm/boot/dts/stm32429i-eval.dts @@ -47,6 +47,7 @@ /dts-v1/; #include "stm32f429.dtsi" +#include <dt-bindings/input/input.h> / { model = "STMicroelectronics STM32429i-EVAL board"; @@ -65,6 +66,10 @@ serial0 = &usart1; }; + soc { + dma-ranges = <0xc0000000 0x0 0x10000000>; + }; + leds { compatible = "gpio-leds"; green { @@ -82,6 +87,23 @@ }; }; + gpio_keys { + compatible = "gpio-keys"; + #address-cells = <1>; + #size-cells = <0>; + autorepeat; + button@0 { + label = "Wake up"; + linux,code = <KEY_WAKEUP>; + gpios = <&gpioa 0 0>; + }; + button@1 { + label = "Tamper"; + linux,code = <KEY_RESTART>; + gpios = <&gpioc 13 0>; + }; + }; + usbotg_hs_phy: usbphy { #phy-cells = <0>; compatible = "usb-nop-xceiv"; @@ -94,11 +116,12 @@ clock-frequency = <25000000>; }; -ðernet0 { +&mac { status = "okay"; - pinctrl-0 = <ðernet0_mii>; + pinctrl-0 = <ðernet_mii>; pinctrl-names = "default"; - phy-mode = "mii-id"; + phy-mode = "mii"; + phy-handle = <&phy1>; mdio0 { #address-cells = <1>; #size-cells = <0>; diff --git a/arch/arm/boot/dts/stm32746g-eval.dts b/arch/arm/boot/dts/stm32746g-eval.dts new file mode 100644 index 000000000000..aa03fac1ec55 --- /dev/null +++ b/arch/arm/boot/dts/stm32746g-eval.dts @@ -0,0 +1,96 @@ +/* + * Copyright 2015 - Maxime Coquelin <mcoquelin.stm32@gmail.com> + * + * This file is dual-licensed: you can use it either under the terms + * of the GPL or the X11 license, at your option. Note that this dual + * licensing only applies to this file, and not this project as a + * whole. + * + * a) This file is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of the + * License, or (at your option) any later version. + * + * This file is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * Or, alternatively, + * + * b) Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, + * copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following + * conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + */ + +/dts-v1/; +#include "stm32f746.dtsi" +#include <dt-bindings/input/input.h> + +/ { + model = "STMicroelectronics STM32746g-EVAL board"; + compatible = "st,stm32746g-eval", "st,stm32f746"; + + chosen { + bootargs = "root=/dev/ram"; + stdout-path = "serial0:115200n8"; + }; + + memory { + reg = <0xc0000000 0x2000000>; + }; + + aliases { + serial0 = &usart1; + }; + + leds { + compatible = "gpio-leds"; + green { + gpios = <&gpiof 10 1>; + linux,default-trigger = "heartbeat"; + }; + red { + gpios = <&gpiob 7 1>; + }; + }; + + gpio_keys { + compatible = "gpio-keys"; + #address-cells = <1>; + #size-cells = <0>; + autorepeat; + button@0 { + label = "Wake up"; + linux,code = <KEY_WAKEUP>; + gpios = <&gpioc 13 0>; + }; + }; +}; + +&clk_hse { + clock-frequency = <25000000>; +}; + +&usart1 { + pinctrl-0 = <&usart1_pins_a>; + pinctrl-names = "default"; + status = "okay"; +}; diff --git a/arch/arm/boot/dts/stm32f429-disco.dts b/arch/arm/boot/dts/stm32f429-disco.dts index 01408073dd53..7d0415e80668 100644 --- a/arch/arm/boot/dts/stm32f429-disco.dts +++ b/arch/arm/boot/dts/stm32f429-disco.dts @@ -47,6 +47,7 @@ /dts-v1/; #include "stm32f429.dtsi" +#include <dt-bindings/input/input.h> / { model = "STMicroelectronics STM32F429i-DISCO board"; @@ -75,6 +76,18 @@ linux,default-trigger = "heartbeat"; }; }; + + gpio_keys { + compatible = "gpio-keys"; + #address-cells = <1>; + #size-cells = <0>; + autorepeat; + button@0 { + label = "User"; + linux,code = <KEY_HOME>; + gpios = <&gpioa 0 0>; + }; + }; }; &clk_hse { diff --git a/arch/arm/boot/dts/stm32f429.dtsi b/arch/arm/boot/dts/stm32f429.dtsi index 336ee4fb587d..e4dae0eda3cd 100644 --- a/arch/arm/boot/dts/stm32f429.dtsi +++ b/arch/arm/boot/dts/stm32f429.dtsi @@ -56,11 +56,21 @@ compatible = "fixed-clock"; clock-frequency = <0>; }; + + clk-lse { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-frequency = <32768>; + }; + + clk-lsi { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-frequency = <32000>; + }; }; soc { - dma-ranges = <0xc0000000 0x0 0x10000000>; - timer2: timer@40000000 { compatible = "st,stm32-timer"; reg = <0x40000000 0x400>; @@ -122,6 +132,9 @@ interrupts = <39>; clocks = <&rcc 0 146>; status = "disabled"; + dmas = <&dma1 1 4 0x400 0x0>, + <&dma1 3 4 0x400 0x0>; + dma-names = "rx", "tx"; }; usart4: serial@40004c00 { @@ -162,6 +175,9 @@ interrupts = <37>; clocks = <&rcc 0 164>; status = "disabled"; + dmas = <&dma2 2 4 0x400 0x0>, + <&dma2 7 4 0x400 0x0>; + dma-names = "rx", "tx"; }; usart6: serial@40011400 { @@ -185,11 +201,18 @@ interrupts = <1>, <2>, <3>, <6>, <7>, <8>, <9>, <10>, <23>, <40>, <41>, <42>, <62>, <76>; }; + pwrcfg: power-config@40007000 { + compatible = "syscon"; + reg = <0x40007000 0x400>; + }; + pin-controller { #address-cells = <1>; #size-cells = <1>; compatible = "st,stm32f429-pinctrl"; ranges = <0 0x40020000 0x3000>; + interrupt-parent = <&exti>; + st,syscfg = <&syscfg 0x8>; pins-are-numbered; gpioa: gpio@40020000 { @@ -313,7 +336,7 @@ }; }; - ethernet0_mii: mii@0 { + ethernet_mii: mii@0 { pins { pinmux = <STM32F429_PG13_FUNC_ETH_MII_TXD0_ETH_RMII_TXD0>, <STM32F429_PG14_FUNC_ETH_MII_TXD1_ETH_RMII_TXD1>, @@ -340,6 +363,7 @@ compatible = "st,stm32f42xx-rcc", "st,stm32-rcc"; reg = <0x40023800 0x400>; clocks = <&clk_hse>; + st,syscfg = <&pwrcfg>; }; dma1: dma-controller@40026000 { @@ -373,24 +397,22 @@ st,mem2mem; }; - ethernet0: dwmac@40028000 { + mac: ethernet@40028000 { compatible = "st,stm32-dwmac", "snps,dwmac-3.50a"; reg = <0x40028000 0x8000>; reg-names = "stmmaceth"; - interrupts = <61>, <62>; - interrupt-names = "macirq", "eth_wake_irq"; - clock-names = "stmmaceth", "tx-clk", "rx-clk"; + interrupts = <61>; + interrupt-names = "macirq"; + clock-names = "stmmaceth", "mac-clk-tx", "mac-clk-rx"; clocks = <&rcc 0 25>, <&rcc 0 26>, <&rcc 0 27>; st,syscon = <&syscfg 0x4>; snps,pbl = <8>; snps,mixed-burst; - dma-ranges; status = "disabled"; }; usbotg_hs: usb@40040000 { compatible = "snps,dwc2"; - dma-ranges; reg = <0x40040000 0x40000>; interrupts = <77>; clocks = <&rcc 0 29>; diff --git a/arch/arm/boot/dts/stm32f469-disco.dts b/arch/arm/boot/dts/stm32f469-disco.dts index e911af836471..8877c00ce8e8 100644 --- a/arch/arm/boot/dts/stm32f469-disco.dts +++ b/arch/arm/boot/dts/stm32f469-disco.dts @@ -64,6 +64,14 @@ aliases { serial0 = &usart3; }; + + soc { + dma-ranges = <0xc0000000 0x0 0x10000000>; + }; +}; + +&rcc { + compatible = "st,stm32f469-rcc", "st,stm32f42xx-rcc", "st,stm32-rcc"; }; &clk_hse { diff --git a/arch/arm/boot/dts/stm32f746.dtsi b/arch/arm/boot/dts/stm32f746.dtsi new file mode 100644 index 000000000000..f321ffe87144 --- /dev/null +++ b/arch/arm/boot/dts/stm32f746.dtsi @@ -0,0 +1,304 @@ +/* + * Copyright 2015 - Maxime Coquelin <mcoquelin.stm32@gmail.com> + * + * This file is dual-licensed: you can use it either under the terms + * of the GPL or the X11 license, at your option. Note that this dual + * licensing only applies to this file, and not this project as a + * whole. + * + * a) This file is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of the + * License, or (at your option) any later version. + * + * This file is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * Or, alternatively, + * + * b) Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, + * copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following + * conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + */ + +#include "skeleton.dtsi" +#include "armv7-m.dtsi" +#include <dt-bindings/pinctrl/stm32f746-pinfunc.h> + +/ { + clocks { + clk_hse: clk-hse { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-frequency = <0>; + }; + }; + + soc { + timer2: timer@40000000 { + compatible = "st,stm32-timer"; + reg = <0x40000000 0x400>; + interrupts = <28>; + clocks = <&rcc 0 128>; + status = "disabled"; + }; + + timer3: timer@40000400 { + compatible = "st,stm32-timer"; + reg = <0x40000400 0x400>; + interrupts = <29>; + clocks = <&rcc 0 129>; + status = "disabled"; + }; + + timer4: timer@40000800 { + compatible = "st,stm32-timer"; + reg = <0x40000800 0x400>; + interrupts = <30>; + clocks = <&rcc 0 130>; + status = "disabled"; + }; + + timer5: timer@40000c00 { + compatible = "st,stm32-timer"; + reg = <0x40000c00 0x400>; + interrupts = <50>; + clocks = <&rcc 0 131>; + }; + + timer6: timer@40001000 { + compatible = "st,stm32-timer"; + reg = <0x40001000 0x400>; + interrupts = <54>; + clocks = <&rcc 0 132>; + status = "disabled"; + }; + + timer7: timer@40001400 { + compatible = "st,stm32-timer"; + reg = <0x40001400 0x400>; + interrupts = <55>; + clocks = <&rcc 0 133>; + status = "disabled"; + }; + + usart2: serial@40004400 { + compatible = "st,stm32f7-usart", "st,stm32f7-uart"; + reg = <0x40004400 0x400>; + interrupts = <38>; + clocks = <&rcc 0 145>; + status = "disabled"; + }; + + usart3: serial@40004800 { + compatible = "st,stm32f7-usart", "st,stm32f7-uart"; + reg = <0x40004800 0x400>; + interrupts = <39>; + clocks = <&rcc 0 146>; + status = "disabled"; + }; + + usart4: serial@40004c00 { + compatible = "st,stm32f7-uart"; + reg = <0x40004c00 0x400>; + interrupts = <52>; + clocks = <&rcc 0 147>; + status = "disabled"; + }; + + usart5: serial@40005000 { + compatible = "st,stm32f7-uart"; + reg = <0x40005000 0x400>; + interrupts = <53>; + clocks = <&rcc 0 148>; + status = "disabled"; + }; + + usart7: serial@40007800 { + compatible = "st,stm32f7-usart", "st,stm32f7-uart"; + reg = <0x40007800 0x400>; + interrupts = <82>; + clocks = <&rcc 0 158>; + status = "disabled"; + }; + + usart8: serial@40007c00 { + compatible = "st,stm32f7-usart", "st,stm32f7-uart"; + reg = <0x40007c00 0x400>; + interrupts = <83>; + clocks = <&rcc 0 159>; + status = "disabled"; + }; + + usart1: serial@40011000 { + compatible = "st,stm32f7-usart", "st,stm32f7-uart"; + reg = <0x40011000 0x400>; + interrupts = <37>; + clocks = <&rcc 0 164>; + status = "disabled"; + }; + + usart6: serial@40011400 { + compatible = "st,stm32f7-usart", "st,stm32f7-uart"; + reg = <0x40011400 0x400>; + interrupts = <71>; + clocks = <&rcc 0 165>; + status = "disabled"; + }; + + syscfg: system-config@40013800 { + compatible = "syscon"; + reg = <0x40013800 0x400>; + }; + + exti: interrupt-controller@40013c00 { + compatible = "st,stm32-exti"; + interrupt-controller; + #interrupt-cells = <2>; + reg = <0x40013C00 0x400>; + interrupts = <1>, <2>, <3>, <6>, <7>, <8>, <9>, <10>, <23>, <40>, <41>, <42>, <62>, <76>; + }; + + pin-controller { + #address-cells = <1>; + #size-cells = <1>; + compatible = "st,stm32f746-pinctrl"; + ranges = <0 0x40020000 0x3000>; + interrupt-parent = <&exti>; + st,syscfg = <&syscfg 0x8>; + pins-are-numbered; + + gpioa: gpio@40020000 { + gpio-controller; + #gpio-cells = <2>; + reg = <0x0 0x400>; + clocks = <&rcc 0 256>; + st,bank-name = "GPIOA"; + }; + + gpiob: gpio@40020400 { + gpio-controller; + #gpio-cells = <2>; + reg = <0x400 0x400>; + clocks = <&rcc 0 257>; + st,bank-name = "GPIOB"; + }; + + gpioc: gpio@40020800 { + gpio-controller; + #gpio-cells = <2>; + reg = <0x800 0x400>; + clocks = <&rcc 0 258>; + st,bank-name = "GPIOC"; + }; + + gpiod: gpio@40020c00 { + gpio-controller; + #gpio-cells = <2>; + reg = <0xc00 0x400>; + clocks = <&rcc 0 259>; + st,bank-name = "GPIOD"; + }; + + gpioe: gpio@40021000 { + gpio-controller; + #gpio-cells = <2>; + reg = <0x1000 0x400>; + clocks = <&rcc 0 260>; + st,bank-name = "GPIOE"; + }; + + gpiof: gpio@40021400 { + gpio-controller; + #gpio-cells = <2>; + reg = <0x1400 0x400>; + clocks = <&rcc 0 261>; + st,bank-name = "GPIOF"; + }; + + gpiog: gpio@40021800 { + gpio-controller; + #gpio-cells = <2>; + reg = <0x1800 0x400>; + clocks = <&rcc 0 262>; + st,bank-name = "GPIOG"; + }; + + gpioh: gpio@40021c00 { + gpio-controller; + #gpio-cells = <2>; + reg = <0x1c00 0x400>; + clocks = <&rcc 0 263>; + st,bank-name = "GPIOH"; + }; + + gpioi: gpio@40022000 { + gpio-controller; + #gpio-cells = <2>; + reg = <0x2000 0x400>; + clocks = <&rcc 0 264>; + st,bank-name = "GPIOI"; + }; + + gpioj: gpio@40022400 { + gpio-controller; + #gpio-cells = <2>; + reg = <0x2400 0x400>; + clocks = <&rcc 0 265>; + st,bank-name = "GPIOJ"; + }; + + gpiok: gpio@40022800 { + gpio-controller; + #gpio-cells = <2>; + reg = <0x2800 0x400>; + clocks = <&rcc 0 266>; + st,bank-name = "GPIOK"; + }; + + usart1_pins_a: usart1@0 { + pins1 { + pinmux = <STM32F746_PA9_FUNC_USART1_TX>; + bias-disable; + drive-push-pull; + slew-rate = <0>; + }; + pins2 { + pinmux = <STM32F746_PA10_FUNC_USART1_RX>; + bias-disable; + }; + }; + }; + + rcc: rcc@40023800 { + #clock-cells = <2>; + compatible = "st,stm32f42xx-rcc", "st,stm32-rcc"; + reg = <0x40023800 0x400>; + clocks = <&clk_hse>; + }; + }; +}; + +&systick { + clocks = <&rcc 1 0>; + status = "okay"; +}; diff --git a/arch/arm/boot/dts/sun4i-a10.dtsi b/arch/arm/boot/dts/sun4i-a10.dtsi index 7e7dfc2b43db..b14a4281058d 100644 --- a/arch/arm/boot/dts/sun4i-a10.dtsi +++ b/arch/arm/boot/dts/sun4i-a10.dtsi @@ -967,7 +967,8 @@ compatible = "allwinner,sun4i-a10-pinctrl"; reg = <0x01c20800 0x400>; interrupts = <28>; - clocks = <&apb0_gates 5>; + clocks = <&apb0_gates 5>, <&osc24M>, <&osc32k>; + clock-names = "apb", "hosc", "losc"; gpio-controller; interrupt-controller; #interrupt-cells = <3>; diff --git a/arch/arm/boot/dts/sun5i-a10s-olinuxino-micro.dts b/arch/arm/boot/dts/sun5i-a10s-olinuxino-micro.dts index aef91476f9ae..0684d7930d65 100644 --- a/arch/arm/boot/dts/sun5i-a10s-olinuxino-micro.dts +++ b/arch/arm/boot/dts/sun5i-a10s-olinuxino-micro.dts @@ -250,8 +250,8 @@ &spi2 { pinctrl-names = "default"; - pinctrl-0 = <&spi2_pins_a>, - <&spi2_cs0_pins_a>; + pinctrl-0 = <&spi2_pins_b>, + <&spi2_cs0_pins_b>; status = "okay"; }; diff --git a/arch/arm/boot/dts/sun5i-a10s.dtsi b/arch/arm/boot/dts/sun5i-a10s.dtsi index c41a2ba34dde..7aa8c7aa0153 100644 --- a/arch/arm/boot/dts/sun5i-a10s.dtsi +++ b/arch/arm/boot/dts/sun5i-a10s.dtsi @@ -243,14 +243,14 @@ allwinner,pull = <SUN4I_PINCTRL_NO_PULL>; }; - spi2_pins_a: spi2@0 { + spi2_pins_b: spi2@1 { allwinner,pins = "PB12", "PB13", "PB14"; allwinner,function = "spi2"; allwinner,drive = <SUN4I_PINCTRL_10_MA>; allwinner,pull = <SUN4I_PINCTRL_NO_PULL>; }; - spi2_cs0_pins_a: spi2_cs0@0 { + spi2_cs0_pins_b: spi2_cs0@1 { allwinner,pins = "PB11"; allwinner,function = "spi2"; allwinner,drive = <SUN4I_PINCTRL_10_MA>; diff --git a/arch/arm/boot/dts/sun5i-a13-olinuxino.dts b/arch/arm/boot/dts/sun5i-a13-olinuxino.dts index b3c234c65ea1..bb7210e0e4a9 100644 --- a/arch/arm/boot/dts/sun5i-a13-olinuxino.dts +++ b/arch/arm/boot/dts/sun5i-a13-olinuxino.dts @@ -72,6 +72,47 @@ default-state = "on"; }; }; + + bridge { + compatible = "dumb-vga-dac"; + #address-cells = <1>; + #size-cells = <0>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + vga_bridge_in: endpoint { + remote-endpoint = <&tcon0_out_vga>; + }; + }; + + port@1 { + reg = <1>; + + vga_bridge_out: endpoint { + remote-endpoint = <&vga_con_in>; + }; + }; + }; + }; + + vga { + compatible = "vga-connector"; + + port { + vga_con_in: endpoint { + remote-endpoint = <&vga_bridge_out>; + }; + }; + }; +}; + +&be0 { + status = "okay"; }; &ehci0 { @@ -211,6 +252,19 @@ status = "okay"; }; +&tcon0 { + pinctrl-names = "default"; + pinctrl-0 = <&lcd_rgb666_pins>; + status = "okay"; +}; + +&tcon0_out { + tcon0_out_vga: endpoint@0 { + reg = <0>; + remote-endpoint = <&vga_bridge_in>; + }; +}; + &uart1 { pinctrl-names = "default"; pinctrl-0 = <&uart1_pins_b>; diff --git a/arch/arm/boot/dts/sun5i-a13-utoo-p66.dts b/arch/arm/boot/dts/sun5i-a13-utoo-p66.dts index a8b0bcc04514..3d7ff10a48e9 100644 --- a/arch/arm/boot/dts/sun5i-a13-utoo-p66.dts +++ b/arch/arm/boot/dts/sun5i-a13-utoo-p66.dts @@ -83,22 +83,6 @@ allwinner,pins = "PG3"; }; -&i2c1 { - icn8318: touchscreen@40 { - compatible = "chipone,icn8318"; - reg = <0x40>; - interrupt-parent = <&pio>; - interrupts = <6 9 IRQ_TYPE_EDGE_FALLING>; /* EINT9 (PG9) */ - pinctrl-names = "default"; - pinctrl-0 = <&ts_wake_pin_p66>; - wake-gpios = <&pio 1 3 GPIO_ACTIVE_HIGH>; /* PB3 */ - touchscreen-size-x = <800>; - touchscreen-size-y = <480>; - touchscreen-inverted-x; - touchscreen-swapped-x-y; - }; -}; - &mmc2 { pinctrl-names = "default"; pinctrl-0 = <&mmc2_pins_a>; @@ -121,20 +105,26 @@ allwinner,drive = <SUN4I_PINCTRL_10_MA>; allwinner,pull = <SUN4I_PINCTRL_PULL_UP>; }; - - ts_wake_pin_p66: ts_wake_pin@0 { - allwinner,pins = "PB3"; - allwinner,function = "gpio_out"; - allwinner,drive = <SUN4I_PINCTRL_10_MA>; - allwinner,pull = <SUN4I_PINCTRL_NO_PULL>; - }; - }; ®_usb0_vbus { gpio = <&pio 1 4 GPIO_ACTIVE_HIGH>; /* PB4 */ }; +&touchscreen { + compatible = "chipone,icn8318"; + reg = <0x40>; + /* The P66 uses a different EINT then the reference design */ + interrupts = <6 9 IRQ_TYPE_EDGE_FALLING>; /* EINT9 (PG9) */ + /* The icn8318 binding expects wake-gpios instead of power-gpios */ + wake-gpios = <&pio 1 3 GPIO_ACTIVE_HIGH>; /* PB3 */ + touchscreen-size-x = <800>; + touchscreen-size-y = <480>; + touchscreen-inverted-x; + touchscreen-swapped-x-y; + status = "okay"; +}; + &uart1 { /* The P66 uses the uart pins as gpios */ status = "disabled"; diff --git a/arch/arm/boot/dts/sun5i-gr8-chip-pro.dts b/arch/arm/boot/dts/sun5i-gr8-chip-pro.dts new file mode 100644 index 000000000000..92a2dc6250a5 --- /dev/null +++ b/arch/arm/boot/dts/sun5i-gr8-chip-pro.dts @@ -0,0 +1,266 @@ +/* + * Copyright 2016 Free Electrons + * Copyright 2016 NextThing Co + * + * Maxime Ripard <maxime.ripard@free-electrons.com> + * + * This file is dual-licensed: you can use it either under the terms + * of the GPL or the X11 license, at your option. Note that this dual + * licensing only applies to this file, and not this project as a + * whole. + * + * a) This file is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of the + * License, or (at your option) any later version. + * + * This file is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * Or, alternatively, + * + * b) Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, + * copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following + * conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + */ + +/dts-v1/; +#include "sun5i-gr8.dtsi" +#include "sunxi-common-regulators.dtsi" + +#include <dt-bindings/gpio/gpio.h> +#include <dt-bindings/input/input.h> +#include <dt-bindings/interrupt-controller/irq.h> + +/ { + model = "NextThing C.H.I.P. Pro"; + compatible = "nextthing,chip-pro", "nextthing,gr8"; + + aliases { + i2c0 = &i2c0; + i2c1 = &i2c1; + serial0 = &uart1; + serial1 = &uart2; + serial2 = &uart3; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; + + leds { + compatible = "gpio-leds"; + + status { + label = "chip-pro:white:status"; + gpios = <&axp_gpio 2 GPIO_ACTIVE_HIGH>; + default-state = "on"; + }; + }; + + mmc0_pwrseq: mmc0_pwrseq { + compatible = "mmc-pwrseq-simple"; + pinctrl-names = "default"; + pinctrl-0 = <&wifi_reg_on_pin_chip_pro>; + reset-gpios = <&pio 1 10 GPIO_ACTIVE_LOW>; /* PB10 */ + }; +}; + +&codec { + status = "okay"; +}; + +&ehci0 { + status = "okay"; +}; + +&i2c0 { + pinctrl-names = "default"; + pinctrl-0 = <&i2c0_pins_a>; + status = "okay"; + + axp209: pmic@34 { + reg = <0x34>; + + /* + * The interrupt is routed through the "External Fast + * Interrupt Request" pin (ball G13 of the module) + * directly to the main interrupt controller, without + * any other controller interfering. + */ + interrupts = <0>; + }; +}; + +#include "axp209.dtsi" + +&i2c1 { + pinctrl-names = "default"; + pinctrl-0 = <&i2c1_pins_a>; + status = "disabled"; +}; + +&i2s0 { + pinctrl-names = "default"; + pinctrl-0 = <&i2s0_mclk_pins_a>, <&i2s0_data_pins_a>; + status = "disabled"; +}; + +&mmc0 { + pinctrl-names = "default"; + pinctrl-0 = <&mmc0_pins_a>; + vmmc-supply = <®_vcc3v3>; + mmc-pwrseq = <&mmc0_pwrseq>; + bus-width = <4>; + non-removable; + status = "okay"; +}; + +&nfc { + pinctrl-names = "default"; + pinctrl-0 = <&nand_pins_a &nand_cs0_pins_a &nand_rb0_pins_a>; + status = "okay"; + + nand@0 { + #address-cells = <2>; + #size-cells = <2>; + reg = <0>; + allwinner,rb = <0>; + nand-ecc-mode = "hw"; + }; +}; + +&ohci0 { + status = "okay"; +}; + +&otg_sram { + status = "okay"; +}; + +&pio { + usb0_id_pin_chip_pro: usb0-id-pin@0 { + allwinner,pins = "PG2"; + allwinner,function = "gpio_in"; + allwinner,drive = <SUN4I_PINCTRL_10_MA>; + allwinner,pull = <SUN4I_PINCTRL_NO_PULL>; + }; + + wifi_reg_on_pin_chip_pro: wifi-reg-on-pin@0 { + allwinner,pins = "PB10"; + allwinner,function = "gpio_out"; + allwinner,drive = <SUN4I_PINCTRL_10_MA>; + allwinner,pull = <SUN4I_PINCTRL_NO_PULL>; + }; +}; + +&pwm { + pinctrl-names = "default"; + pinctrl-0 = <&pwm0_pins_a>, <&pwm1_pins>; + status = "disabled"; +}; + +®_dcdc2 { + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <1400000>; + regulator-name = "vdd-cpu"; + regulator-always-on; +}; + +®_dcdc3 { + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <1300000>; + regulator-name = "vdd-sys"; + regulator-always-on; +}; + +®_ldo1 { + regulator-name = "vdd-rtc"; +}; + +®_ldo2 { + regulator-min-microvolt = <2700000>; + regulator-max-microvolt = <3300000>; + regulator-name = "avcc"; + regulator-always-on; +}; + +/* + * Both LDO3 and LDO4 are used in parallel to power up the + * WiFi/BT chip. + */ +®_ldo3 { + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-name = "vcc-wifi-1"; + regulator-always-on; +}; + +®_ldo4 { + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-name = "vcc-wifi-2"; + regulator-always-on; +}; + +&uart1 { + pinctrl-names = "default"; + pinctrl-0 = <&uart1_pins_a>, <&uart1_cts_rts_pins_a>; + status = "okay"; +}; + +&uart2 { + pinctrl-names = "default"; + pinctrl-0 = <&uart2_pins_a>, <&uart2_cts_rts_pins_a>; + status = "disabled"; +}; + +&uart3 { + pinctrl-names = "default"; + pinctrl-0 = <&uart3_pins_a>, <&uart3_cts_rts_pins_a>; + status = "okay"; +}; + +&usb_otg { + /* + * The CHIP Pro doesn't have a controllable VBUS, nor does it + * have any 5v rail on the board itself. + * + * If one wants to use it as a true OTG port, it should be + * done in the baseboard, and its DT / overlay will add it. + */ + dr_mode = "otg"; + status = "okay"; +}; + +&usb_power_supply { + status = "okay"; +}; + +&usbphy { + pinctrl-names = "default"; + pinctrl-0 = <&usb0_id_pin_chip_pro>; + usb0_id_det-gpio = <&pio 6 2 GPIO_ACTIVE_HIGH>; /* PG2 */ + usb0_vbus_power-supply = <&usb_power_supply>; + usb1_vbus-supply = <®_vcc5v0>; + status = "okay"; +}; diff --git a/arch/arm/boot/dts/ntc-gr8-evb.dts b/arch/arm/boot/dts/sun5i-gr8-evb.dts index 4b622f3b5220..030605aa8065 100644 --- a/arch/arm/boot/dts/ntc-gr8-evb.dts +++ b/arch/arm/boot/dts/sun5i-gr8-evb.dts @@ -44,7 +44,7 @@ */ /dts-v1/; -#include "ntc-gr8.dtsi" +#include "sun5i-gr8.dtsi" #include "sunxi-common-regulators.dtsi" #include <dt-bindings/gpio/gpio.h> @@ -75,6 +75,39 @@ brightness-levels = <0 10 20 30 40 50 60 70 80 90 100>; default-brightness-level = <8>; }; + + sound-analog { + compatible = "simple-audio-card"; + simple-audio-card,name = "gr8-evb-wm8978"; + simple-audio-card,format = "i2s"; + simple-audio-card,mclk-fs = <512>; + + simple-audio-card,cpu { + sound-dai = <&i2s0>; + }; + + simple-audio-card,codec { + sound-dai = <&wm8978>; + }; + }; + + sound-spdif { + compatible = "simple-audio-card"; + simple-audio-card,name = "On-board SPDIF"; + + simple-audio-card,cpu { + sound-dai = <&spdif>; + }; + + simple-audio-card,codec { + sound-dai = <&spdif_out>; + }; + }; + + spdif_out: spdif-out { + #sound-dai-cells = <0>; + compatible = "linux,spdif-dit"; + }; }; &be0 { diff --git a/arch/arm/boot/dts/ntc-gr8.dtsi b/arch/arm/boot/dts/sun5i-gr8.dtsi index ca54e03ef366..ea86d4d58db6 100644 --- a/arch/arm/boot/dts/ntc-gr8.dtsi +++ b/arch/arm/boot/dts/sun5i-gr8.dtsi @@ -792,7 +792,7 @@ }; i2s0_mclk_pins_a: i2s0-mclk@0 { - allwinner,pins = "PB6", "PB7", "PB8", "PB9"; + allwinner,pins = "PB5"; allwinner,function = "i2s0"; allwinner,drive = <SUN4I_PINCTRL_10_MA>; allwinner,pull = <SUN4I_PINCTRL_NO_PULL>; @@ -854,6 +854,13 @@ allwinner,pull = <SUN4I_PINCTRL_NO_PULL>; }; + pwm1_pins: pwm1 { + allwinner,pins = "PG13"; + allwinner,function = "pwm1"; + allwinner,drive = <SUN4I_PINCTRL_10_MA>; + allwinner,pull = <SUN4I_PINCTRL_NO_PULL>; + }; + spdif_tx_pins_a: spdif@0 { allwinner,pins = "PB10"; allwinner,function = "spdif"; @@ -874,6 +881,34 @@ allwinner,drive = <SUN4I_PINCTRL_10_MA>; allwinner,pull = <SUN4I_PINCTRL_NO_PULL>; }; + + uart2_pins_a: uart2@1 { + allwinner,pins = "PD2", "PD3"; + allwinner,function = "uart2"; + allwinner,drive = <SUN4I_PINCTRL_10_MA>; + allwinner,pull = <SUN4I_PINCTRL_NO_PULL>; + }; + + uart2_cts_rts_pins_a: uart2-cts-rts@0 { + allwinner,pins = "PD4", "PD5"; + allwinner,function = "uart2"; + allwinner,drive = <SUN4I_PINCTRL_10_MA>; + allwinner,pull = <SUN4I_PINCTRL_NO_PULL>; + }; + + uart3_pins_a: uart3@1 { + allwinner,pins = "PG9", "PG10"; + allwinner,function = "uart3"; + allwinner,drive = <SUN4I_PINCTRL_10_MA>; + allwinner,pull = <SUN4I_PINCTRL_NO_PULL>; + }; + + uart3_cts_rts_pins_a: uart3-cts-rts@0 { + allwinner,pins = "PG11", "PG12"; + allwinner,function = "uart3"; + allwinner,drive = <SUN4I_PINCTRL_10_MA>; + allwinner,pull = <SUN4I_PINCTRL_NO_PULL>; + }; }; pwm: pwm@01c20e00 { @@ -978,6 +1013,16 @@ status = "disabled"; }; + uart3: serial@01c28c00 { + compatible = "snps,dw-apb-uart"; + reg = <0x01c28c00 0x400>; + interrupts = <4>; + reg-shift = <2>; + reg-io-width = <4>; + clocks = <&apb1_gates 19>; + status = "disabled"; + }; + i2c0: i2c@01c2ac00 { compatible = "allwinner,sun4i-a10-i2c"; reg = <0x01c2ac00 0x400>; diff --git a/arch/arm/boot/dts/sun5i-r8-chip.dts b/arch/arm/boot/dts/sun5i-r8-chip.dts index b68a12374b35..c6da5ad37152 100644 --- a/arch/arm/boot/dts/sun5i-r8-chip.dts +++ b/arch/arm/boot/dts/sun5i-r8-chip.dts @@ -56,9 +56,11 @@ aliases { i2c0 = &i2c0; + i2c1 = &i2c1; i2c2 = &i2c2; serial0 = &uart1; serial1 = &uart3; + spi0 = &spi2; }; chosen { @@ -74,6 +76,20 @@ default-state = "on"; }; }; + + mmc0_pwrseq: mmc0_pwrseq { + compatible = "mmc-pwrseq-simple"; + pinctrl-names = "default"; + pinctrl-0 = <&chip_wifi_reg_on_pin>; + reset-gpios = <&pio 2 19 GPIO_ACTIVE_LOW>; /* PC19 */ + }; + + onewire { + compatible = "w1-gpio"; + gpios = <&pio 3 2 GPIO_ACTIVE_HIGH>; /* PD2 */ + pinctrl-names = "default"; + pinctrl-0 = <&chip_w1_pin>; + }; }; &be0 { @@ -112,6 +128,12 @@ #include "axp209.dtsi" +&i2c1 { + pinctrl-names = "default"; + pinctrl-0 = <&i2c1_pins_a>; + status = "disabled"; +}; + &i2c2 { pinctrl-names = "default"; pinctrl-0 = <&i2c2_pins_a>; @@ -131,10 +153,15 @@ }; }; +&mmc0_pins_a { + allwinner,pull = <SUN4I_PINCTRL_PULL_UP>; +}; + &mmc0 { pinctrl-names = "default"; pinctrl-0 = <&mmc0_pins_a>; vmmc-supply = <®_vcc3v3>; + mmc-pwrseq = <&mmc0_pwrseq>; bus-width = <4>; non-removable; status = "okay"; @@ -156,12 +183,26 @@ allwinner,pull = <SUN4I_PINCTRL_NO_PULL>; }; + chip_wifi_reg_on_pin: chip_wifi_reg_on_pin@0 { + allwinner,pins = "PC19"; + allwinner,function = "gpio_out"; + allwinner,drive = <SUN4I_PINCTRL_10_MA>; + allwinner,pull = <SUN4I_PINCTRL_NO_PULL>; + }; + chip_id_det_pin: chip_id_det_pin@0 { allwinner,pins = "PG2"; allwinner,function = "gpio_in"; allwinner,drive = <SUN4I_PINCTRL_10_MA>; allwinner,pull = <SUN4I_PINCTRL_NO_PULL>; }; + + chip_w1_pin: chip_w1_pin@0 { + allwinner,pins = "PD2"; + allwinner,function = "gpio_in"; + allwinner,drive = <SUN4I_PINCTRL_10_MA>; + allwinner,pull = <SUN4I_PINCTRL_PULL_UP>; + }; }; ®_dcdc2 { @@ -189,6 +230,28 @@ regulator-always-on; }; +/* + * Both LDO3 and LDO4 are used in parallel to power up the WiFi/BT + * Chip. + * + * If those are not enabled, the SDIO part will not enumerate, and + * since there's no way currently to pass DT infos to an SDIO device, + * we cannot really do better than this ugly hack for now. + */ +®_ldo3 { + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-name = "vcc-wifi-1"; + regulator-always-on; +}; + +®_ldo4 { + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-name = "vcc-wifi-2"; + regulator-always-on; +}; + ®_ldo5 { regulator-min-microvolt = <1800000>; regulator-max-microvolt = <1800000>; @@ -202,6 +265,12 @@ status = "okay"; }; +&spi2 { + pinctrl-names = "default"; + pinctrl-0 = <&spi2_pins_a>; + status = "disabled"; +}; + &tcon0 { status = "okay"; }; diff --git a/arch/arm/boot/dts/sun5i-reference-design-tablet.dtsi b/arch/arm/boot/dts/sun5i-reference-design-tablet.dtsi index 20cc940f5f91..82f87cdcd164 100644 --- a/arch/arm/boot/dts/sun5i-reference-design-tablet.dtsi +++ b/arch/arm/boot/dts/sun5i-reference-design-tablet.dtsi @@ -41,6 +41,7 @@ */ #include "sunxi-reference-design-tablet.dtsi" +#include <dt-bindings/interrupt-controller/irq.h> #include <dt-bindings/pwm/pwm.h> / { @@ -84,6 +85,23 @@ }; &i2c1 { + /* + * The gsl1680 is rated at 400KHz and it will not work reliable at + * 100KHz, this has been confirmed on multiple different q8 tablets. + * All other devices on this bus are also rated for 400KHz. + */ + clock-frequency = <400000>; + + touchscreen: touchscreen { + interrupt-parent = <&pio>; + interrupts = <6 11 IRQ_TYPE_EDGE_FALLING>; /* EINT11 (PG11) */ + pinctrl-names = "default"; + pinctrl-0 = <&ts_power_pin>; + power-gpios = <&pio 1 3 GPIO_ACTIVE_HIGH>; /* PB3 */ + /* Tablet dts must provide reg and compatible */ + status = "disabled"; + }; + pcf8563: rtc@51 { compatible = "nxp,pcf8563"; reg = <0x51>; @@ -125,6 +143,13 @@ allwinner,pull = <SUN4I_PINCTRL_PULL_UP>; }; + ts_power_pin: ts_power_pin { + pins = "PB3"; + function = "gpio_out"; + drive-strength = <10>; + bias-disable; + }; + usb0_vbus_detect_pin: usb0_vbus_detect_pin@0 { allwinner,pins = "PG1"; allwinner,function = "gpio_in"; diff --git a/arch/arm/boot/dts/sun5i.dtsi b/arch/arm/boot/dts/sun5i.dtsi index e374f4fc8073..b0fca4ef4dae 100644 --- a/arch/arm/boot/dts/sun5i.dtsi +++ b/arch/arm/boot/dts/sun5i.dtsi @@ -547,7 +547,8 @@ pio: pinctrl@01c20800 { reg = <0x01c20800 0x400>; interrupts = <28>; - clocks = <&apb0_gates 5>; + clocks = <&apb0_gates 5>, <&osc24M>, <&osc32k>; + clock-names = "apb", "hosc", "losc"; gpio-controller; interrupt-controller; #interrupt-cells = <3>; @@ -574,6 +575,16 @@ allwinner,pull = <SUN4I_PINCTRL_NO_PULL>; }; + lcd_rgb565_pins: lcd_rgb565@0 { + allwinner,pins = "PD3", "PD4", "PD5", "PD6", "PD7", + "PD10", "PD11", "PD12", "PD13", "PD14", "PD15", + "PD19", "PD20", "PD21", "PD22", "PD23", + "PD24", "PD25", "PD26", "PD27"; + allwinner,function = "lcd0"; + allwinner,drive = <SUN4I_PINCTRL_10_MA>; + allwinner,pull = <SUN4I_PINCTRL_NO_PULL>; + }; + mmc0_pins_a: mmc0@0 { allwinner,pins = "PF0", "PF1", "PF2", "PF3", "PF4", "PF5"; @@ -591,6 +602,20 @@ allwinner,pull = <SUN4I_PINCTRL_PULL_UP>; }; + spi2_pins_a: spi2@0 { + allwinner,pins = "PE1", "PE2", "PE3"; + allwinner,function = "spi2"; + allwinner,drive = <SUN4I_PINCTRL_10_MA>; + allwinner,pull = <SUN4I_PINCTRL_NO_PULL>; + }; + + spi2_cs0_pins_a: spi2-cs0@0 { + allwinner,pins = "PE0"; + allwinner,function = "spi2"; + allwinner,drive = <SUN4I_PINCTRL_10_MA>; + allwinner,pull = <SUN4I_PINCTRL_NO_PULL>; + }; + uart3_pins_a: uart3@0 { allwinner,pins = "PG9", "PG10"; allwinner,function = "uart3"; diff --git a/arch/arm/boot/dts/sun6i-a31-hummingbird.dts b/arch/arm/boot/dts/sun6i-a31-hummingbird.dts index 9a74637f677f..735914f6ae44 100644 --- a/arch/arm/boot/dts/sun6i-a31-hummingbird.dts +++ b/arch/arm/boot/dts/sun6i-a31-hummingbird.dts @@ -63,12 +63,79 @@ stdout-path = "serial0:115200n8"; }; + vga-connector { + compatible = "vga-connector"; + + port { + vga_con_in: endpoint { + remote-endpoint = <&vga_dac_out>; + }; + }; + }; + + vga-dac { + compatible = "dumb-vga-dac"; + vdd-supply = <®_vga_3v3>; + #address-cells = <1>; + #size-cells = <0>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0>; + + vga_dac_in: endpoint@0 { + reg = <0>; + remote-endpoint = <&tcon0_out_vga>; + }; + }; + + port@1 { + #address-cells = <1>; + #size-cells = <0>; + reg = <1>; + + vga_dac_out: endpoint@0 { + reg = <0>; + remote-endpoint = <&vga_con_in>; + }; + }; + }; + }; + + reg_vga_3v3: vga_3v3_regulator { + compatible = "regulator-fixed"; + regulator-name = "vga-3v3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-boot-on; + enable-active-high; + gpio = <&pio 7 25 GPIO_ACTIVE_HIGH>; /* PH25 */ + }; + wifi_pwrseq: wifi_pwrseq { compatible = "mmc-pwrseq-simple"; reset-gpios = <&pio 6 10 GPIO_ACTIVE_LOW>; /* PG10 */ }; }; +&codec { + allwinner,audio-routing = + "Headphone", "HP", + "Speaker", "LINEOUT", + "LINEIN", "Line In", + "MIC1", "Mic", + "MIC2", "Headset Mic", + "Mic", "MBIAS", + "Headset Mic", "HBIAS"; + allwinner,pa-gpios = <&pio 7 22 GPIO_ACTIVE_HIGH>; /* PH22 */ + status = "okay"; +}; + &cpu0 { cpu-supply = <®_dcdc3>; }; @@ -245,6 +312,19 @@ status = "okay"; }; +&tcon0 { + pinctrl-names = "default"; + pinctrl-0 = <&lcd0_rgb888_pins>; + status = "okay"; +}; + +&tcon0_out { + tcon0_out_vga: endpoint@0 { + reg = <0>; + remote-endpoint = <&vga_dac_in>; + }; +}; + &uart0 { pinctrl-names = "default"; pinctrl-0 = <&uart0_pins_a>; diff --git a/arch/arm/boot/dts/sun6i-a31.dtsi b/arch/arm/boot/dts/sun6i-a31.dtsi index ce1960453a0b..2b26175d55d1 100644 --- a/arch/arm/boot/dts/sun6i-a31.dtsi +++ b/arch/arm/boot/dts/sun6i-a31.dtsi @@ -231,6 +231,11 @@ }; }; + de: display-engine { + compatible = "allwinner,sun6i-a31-display-engine"; + allwinner,pipelines = <&fe0>; + }; + soc@01c00000 { compatible = "simple-bus"; #address-cells = <1>; @@ -246,6 +251,44 @@ #dma-cells = <1>; }; + tcon0: lcd-controller@01c0c000 { + compatible = "allwinner,sun6i-a31-tcon"; + reg = <0x01c0c000 0x1000>; + interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>; + resets = <&ccu RST_AHB1_LCD0>; + reset-names = "lcd"; + clocks = <&ccu CLK_AHB1_LCD0>, + <&ccu CLK_LCD0_CH0>, + <&ccu CLK_LCD0_CH1>; + clock-names = "ahb", + "tcon-ch0", + "tcon-ch1"; + clock-output-names = "tcon0-pixel-clock"; + status = "disabled"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + tcon0_in: port@0 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0>; + + tcon0_in_drc0: endpoint@0 { + reg = <0>; + remote-endpoint = <&drc0_out_tcon0>; + }; + }; + + tcon0_out: port@1 { + #address-cells = <1>; + #size-cells = <0>; + reg = <1>; + }; + }; + }; + mmc0: mmc@01c0f000 { compatible = "allwinner,sun7i-a20-mmc"; reg = <0x01c0f000 0x1000>; @@ -428,19 +471,55 @@ <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&ccu CLK_APB1_PIO>; + clocks = <&ccu CLK_APB1_PIO>, <&osc24M>, <&osc32k>; + clock-names = "apb", "hosc", "losc"; gpio-controller; interrupt-controller; #interrupt-cells = <3>; #gpio-cells = <3>; - uart0_pins_a: uart0@0 { - allwinner,pins = "PH20", "PH21"; - allwinner,function = "uart0"; + gmac_pins_gmii_a: gmac_gmii@0 { + allwinner,pins = "PA0", "PA1", "PA2", "PA3", + "PA4", "PA5", "PA6", "PA7", + "PA8", "PA9", "PA10", "PA11", + "PA12", "PA13", "PA14", "PA15", + "PA16", "PA17", "PA18", "PA19", + "PA20", "PA21", "PA22", "PA23", + "PA24", "PA25", "PA26", "PA27"; + allwinner,function = "gmac"; + /* + * data lines in GMII mode run at 125MHz and + * might need a higher signal drive strength + */ + allwinner,drive = <SUN4I_PINCTRL_30_MA>; + allwinner,pull = <SUN4I_PINCTRL_NO_PULL>; + }; + + gmac_pins_mii_a: gmac_mii@0 { + allwinner,pins = "PA0", "PA1", "PA2", "PA3", + "PA8", "PA9", "PA11", + "PA12", "PA13", "PA14", "PA19", + "PA20", "PA21", "PA22", "PA23", + "PA24", "PA26", "PA27"; + allwinner,function = "gmac"; allwinner,drive = <SUN4I_PINCTRL_10_MA>; allwinner,pull = <SUN4I_PINCTRL_NO_PULL>; }; + gmac_pins_rgmii_a: gmac_rgmii@0 { + allwinner,pins = "PA0", "PA1", "PA2", "PA3", + "PA9", "PA10", "PA11", + "PA12", "PA13", "PA14", "PA19", + "PA20", "PA25", "PA26", "PA27"; + allwinner,function = "gmac"; + /* + * data lines in RGMII mode use DDR mode + * and need a higher signal drive strength + */ + allwinner,drive = <SUN4I_PINCTRL_40_MA>; + allwinner,pull = <SUN4I_PINCTRL_NO_PULL>; + }; + i2c0_pins_a: i2c0@0 { allwinner,pins = "PH14", "PH15"; allwinner,function = "i2c0"; @@ -462,6 +541,19 @@ allwinner,pull = <SUN4I_PINCTRL_NO_PULL>; }; + lcd0_rgb888_pins: lcd0_rgb888 { + allwinner,pins = "PD0", "PD1", "PD2", "PD3", + "PD4", "PD5", "PD6", "PD7", + "PD8", "PD9", "PD10", "PD11", + "PD12", "PD13", "PD14", "PD15", + "PD16", "PD17", "PD18", "PD19", + "PD20", "PD21", "PD22", "PD23", + "PD24", "PD25", "PD26", "PD27"; + allwinner,function = "lcd0"; + allwinner,drive = <SUN4I_PINCTRL_10_MA>; + allwinner,pull = <SUN4I_PINCTRL_NO_PULL>; + }; + mmc0_pins_a: mmc0@0 { allwinner,pins = "PF0", "PF1", "PF2", "PF3", "PF4", "PF5"; @@ -506,47 +598,12 @@ allwinner,pull = <SUN4I_PINCTRL_NO_PULL>; }; - gmac_pins_mii_a: gmac_mii@0 { - allwinner,pins = "PA0", "PA1", "PA2", "PA3", - "PA8", "PA9", "PA11", - "PA12", "PA13", "PA14", "PA19", - "PA20", "PA21", "PA22", "PA23", - "PA24", "PA26", "PA27"; - allwinner,function = "gmac"; + uart0_pins_a: uart0@0 { + allwinner,pins = "PH20", "PH21"; + allwinner,function = "uart0"; allwinner,drive = <SUN4I_PINCTRL_10_MA>; allwinner,pull = <SUN4I_PINCTRL_NO_PULL>; }; - - gmac_pins_gmii_a: gmac_gmii@0 { - allwinner,pins = "PA0", "PA1", "PA2", "PA3", - "PA4", "PA5", "PA6", "PA7", - "PA8", "PA9", "PA10", "PA11", - "PA12", "PA13", "PA14", "PA15", - "PA16", "PA17", "PA18", "PA19", - "PA20", "PA21", "PA22", "PA23", - "PA24", "PA25", "PA26", "PA27"; - allwinner,function = "gmac"; - /* - * data lines in GMII mode run at 125MHz and - * might need a higher signal drive strength - */ - allwinner,drive = <SUN4I_PINCTRL_30_MA>; - allwinner,pull = <SUN4I_PINCTRL_NO_PULL>; - }; - - gmac_pins_rgmii_a: gmac_rgmii@0 { - allwinner,pins = "PA0", "PA1", "PA2", "PA3", - "PA9", "PA10", "PA11", - "PA12", "PA13", "PA14", "PA19", - "PA20", "PA25", "PA26", "PA27"; - allwinner,function = "gmac"; - /* - * data lines in RGMII mode use DDR mode - * and need a higher signal drive strength - */ - allwinner,drive = <SUN4I_PINCTRL_40_MA>; - allwinner,pull = <SUN4I_PINCTRL_NO_PULL>; - }; }; timer@01c20c00 { @@ -728,6 +785,19 @@ reset-names = "ahb"; }; + codec: codec@01c22c00 { + #sound-dai-cells = <0>; + compatible = "allwinner,sun6i-a31-codec"; + reg = <0x01c22c00 0x400>; + interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&ccu CLK_APB1_CODEC>, <&ccu CLK_CODEC>; + clock-names = "apb", "codec"; + resets = <&ccu RST_APB1_CODEC>; + dmas = <&dma 15>, <&dma 15>; + dma-names = "rx", "tx"; + status = "disabled"; + }; + timer@01c60000 { compatible = "allwinner,sun6i-a31-hstimer", "allwinner,sun7i-a20-hstimer"; @@ -799,6 +869,115 @@ interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; }; + fe0: display-frontend@01e00000 { + compatible = "allwinner,sun6i-a31-display-frontend"; + reg = <0x01e00000 0x20000>; + interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&ccu CLK_AHB1_FE0>, <&ccu CLK_FE0>, + <&ccu CLK_DRAM_FE0>; + clock-names = "ahb", "mod", + "ram"; + resets = <&ccu RST_AHB1_FE0>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + fe0_out: port@1 { + #address-cells = <1>; + #size-cells = <0>; + reg = <1>; + + fe0_out_be0: endpoint@0 { + reg = <0>; + remote-endpoint = <&be0_in_fe0>; + }; + }; + }; + }; + + be0: display-backend@01e60000 { + compatible = "allwinner,sun6i-a31-display-backend"; + reg = <0x01e60000 0x10000>; + interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&ccu CLK_AHB1_BE0>, <&ccu CLK_BE0>, + <&ccu CLK_DRAM_BE0>; + clock-names = "ahb", "mod", + "ram"; + resets = <&ccu RST_AHB1_BE0>; + + assigned-clocks = <&ccu CLK_BE0>; + assigned-clock-rates = <300000000>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + be0_in: port@0 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0>; + + be0_in_fe0: endpoint@0 { + reg = <0>; + remote-endpoint = <&fe0_out_be0>; + }; + }; + + be0_out: port@1 { + #address-cells = <1>; + #size-cells = <0>; + reg = <1>; + + be0_out_drc0: endpoint@0 { + reg = <0>; + remote-endpoint = <&drc0_in_be0>; + }; + }; + }; + }; + + drc0: drc@01e70000 { + compatible = "allwinner,sun6i-a31-drc"; + reg = <0x01e70000 0x10000>; + interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&ccu CLK_AHB1_DRC0>, <&ccu CLK_IEP_DRC0>, + <&ccu CLK_DRAM_DRC0>; + clock-names = "ahb", "mod", + "ram"; + resets = <&ccu RST_AHB1_DRC0>; + + assigned-clocks = <&ccu CLK_IEP_DRC0>; + assigned-clock-rates = <300000000>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + drc0_in: port@0 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0>; + + drc0_in_be0: endpoint@0 { + reg = <0>; + remote-endpoint = <&be0_out_drc0>; + }; + }; + + drc0_out: port@1 { + #address-cells = <1>; + #size-cells = <0>; + reg = <1>; + + drc0_out_tcon0: endpoint@0 { + reg = <0>; + remote-endpoint = <&tcon0_in_drc0>; + }; + }; + }; + }; + rtc: rtc@01f00000 { compatible = "allwinner,sun6i-a31-rtc"; reg = <0x01f00000 0x54>; @@ -886,7 +1065,8 @@ reg = <0x01f02c00 0x400>; interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&apb0_gates 0>; + clocks = <&apb0_gates 0>, <&osc24M>, <&osc32k>; + clock-names = "apb", "hosc", "losc"; resets = <&apb0_rst 0>; gpio-controller; interrupt-controller; diff --git a/arch/arm/boot/dts/sun6i-a31s-sina31s.dts b/arch/arm/boot/dts/sun6i-a31s-sina31s.dts index 6ead2f5c847a..c35ec112f5a0 100644 --- a/arch/arm/boot/dts/sun6i-a31s-sina31s.dts +++ b/arch/arm/boot/dts/sun6i-a31s-sina31s.dts @@ -65,6 +65,14 @@ }; }; +&codec { + allwinner,audio-routing = + "Line Out", "LINEOUT", + "MIC1", "Mic", + "Mic", "MBIAS"; + status = "okay"; +}; + &ehci0 { /* USB 2.0 4 port hub IC */ status = "okay"; diff --git a/arch/arm/boot/dts/sun6i-a31s.dtsi b/arch/arm/boot/dts/sun6i-a31s.dtsi index c17a32771b98..97e2c51d0aea 100644 --- a/arch/arm/boot/dts/sun6i-a31s.dtsi +++ b/arch/arm/boot/dts/sun6i-a31s.dtsi @@ -48,6 +48,14 @@ #include "sun6i-a31.dtsi" +&de { + compatible = "allwinner,sun6i-a31s-display-engine"; +}; + &pio { compatible = "allwinner,sun6i-a31s-pinctrl"; }; + +&tcon0 { + compatible = "allwinner,sun6i-a31s-tcon"; +}; diff --git a/arch/arm/boot/dts/sun7i-a20-bananapi-m1-plus.dts b/arch/arm/boot/dts/sun7i-a20-bananapi-m1-plus.dts index ba5bca0fe997..532f1a160560 100644 --- a/arch/arm/boot/dts/sun7i-a20-bananapi-m1-plus.dts +++ b/arch/arm/boot/dts/sun7i-a20-bananapi-m1-plus.dts @@ -105,6 +105,10 @@ status = "okay"; }; +&cpu0 { + cpu-supply = <®_dcdc2>; +}; + &ehci0 { status = "okay"; }; @@ -132,16 +136,14 @@ status = "okay"; axp209: pmic@34 { - compatible = "x-powers,axp209"; reg = <0x34>; interrupt-parent = <&nmi_intc>; interrupts = <0 IRQ_TYPE_LEVEL_LOW>; - - interrupt-controller; - #interrupt-cells = <1>; }; }; +#include "axp209.dtsi" + &ir0 { pinctrl-names = "default"; pinctrl-0 = <&ir0_rx_pins_a>; @@ -167,7 +169,7 @@ mmc-pwrseq = <&mmc3_pwrseq>; bus-width = <4>; non-removable; - enable-sdio-wakeup; + wakeup-source; status = "okay"; brcmf: bcrmf@1 { @@ -192,6 +194,10 @@ status = "okay"; }; +&otg_sram { + status = "okay"; +}; + &pio { gmac_power_pin_bpi_m1p: gmac_power_pin@0 { allwinner,pins = "PH23"; @@ -222,8 +228,54 @@ }; }; +®_dcdc2 { + regulator-always-on; + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <1400000>; + regulator-name = "vdd-cpu"; +}; + +®_dcdc3 { + regulator-always-on; + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <1400000>; + regulator-name = "vdd-int-dll"; +}; + +®_ldo1 { + regulator-name = "vdd-rtc"; +}; + +®_ldo2 { + regulator-always-on; + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3000000>; + regulator-name = "avcc"; +}; + +®_usb0_vbus { + status = "okay"; +}; + &uart0 { pinctrl-names = "default"; pinctrl-0 = <&uart0_pins_a>; status = "okay"; }; + +&usb_otg { + dr_mode = "otg"; + status = "okay"; +}; + +&usb_power_supply { + status = "okay"; +}; + +&usbphy { + usb0_id_det-gpios = <&pio 7 4 GPIO_ACTIVE_HIGH>; /* PH4 */ + usb0_vbus_power-supply = <&usb_power_supply>; + usb0_vbus-supply = <®_usb0_vbus>; + /* VBUS on usb host ports are tied to DC5V and therefore always on */ + status = "okay"; +}; diff --git a/arch/arm/boot/dts/sun7i-a20-olimex-som-evb.dts b/arch/arm/boot/dts/sun7i-a20-olimex-som-evb.dts index 23aacce4d6c7..134e0c1b129d 100644 --- a/arch/arm/boot/dts/sun7i-a20-olimex-som-evb.dts +++ b/arch/arm/boot/dts/sun7i-a20-olimex-som-evb.dts @@ -88,6 +88,10 @@ status = "okay"; }; +&cpu0 { + cpu-supply = <®_dcdc2>; +}; + &codec { status = "okay"; }; diff --git a/arch/arm/boot/dts/sun7i-a20.dtsi b/arch/arm/boot/dts/sun7i-a20.dtsi index 94cf5a1c7172..f7db067b0de0 100644 --- a/arch/arm/boot/dts/sun7i-a20.dtsi +++ b/arch/arm/boot/dts/sun7i-a20.dtsi @@ -1085,7 +1085,8 @@ compatible = "allwinner,sun7i-a20-pinctrl"; reg = <0x01c20800 0x400>; interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&apb0_gates 5>; + clocks = <&apb0_gates 5>, <&osc24M>, <&osc32k>; + clock-names = "apb", "hosc", "losc"; gpio-controller; interrupt-controller; #interrupt-cells = <3>; diff --git a/arch/arm/boot/dts/sun8i-a23-a33.dtsi b/arch/arm/boot/dts/sun8i-a23-a33.dtsi index 48fc24f36fcb..e4991a78ad73 100644 --- a/arch/arm/boot/dts/sun8i-a23-a33.dtsi +++ b/arch/arm/boot/dts/sun8i-a23-a33.dtsi @@ -266,7 +266,8 @@ /* compatible gets set in SoC specific dtsi file */ reg = <0x01c20800 0x400>; /* interrupts get set in SoC specific dtsi file */ - clocks = <&ccu CLK_BUS_PIO>; + clocks = <&ccu CLK_BUS_PIO>, <&osc24M>, <&osc32k>; + clock-names = "apb", "hosc", "losc"; gpio-controller; interrupt-controller; #interrupt-cells = <3>; @@ -282,11 +283,15 @@ uart1_pins_a: uart1@0 { allwinner,pins = "PG6", "PG7"; allwinner,function = "uart1"; + allwinner,drive = <SUN4I_PINCTRL_10_MA>; + allwinner,pull = <SUN4I_PINCTRL_NO_PULL>; }; uart1_pins_cts_rts_a: uart1-cts-rts@0 { allwinner,pins = "PG8", "PG9"; allwinner,function = "uart1"; + allwinner,drive = <SUN4I_PINCTRL_10_MA>; + allwinner,pull = <SUN4I_PINCTRL_NO_PULL>; }; mmc0_pins_a: mmc0@0 { @@ -571,7 +576,8 @@ compatible = "allwinner,sun8i-a23-r-pinctrl"; reg = <0x01f02c00 0x400>; interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&apb0_gates 0>; + clocks = <&apb0_gates 0>, <&osc24M>, <&osc32k>; + clock-names = "apb", "hosc", "losc"; resets = <&apb0_rst 0>; gpio-controller; interrupt-controller; diff --git a/arch/arm/boot/dts/sun8i-a23-polaroid-mid2407pxe03.dts b/arch/arm/boot/dts/sun8i-a23-polaroid-mid2407pxe03.dts index a86cbedda34c..21bb291b9568 100644 --- a/arch/arm/boot/dts/sun8i-a23-polaroid-mid2407pxe03.dts +++ b/arch/arm/boot/dts/sun8i-a23-polaroid-mid2407pxe03.dts @@ -98,13 +98,6 @@ }; }; -®_ldo_io1 { - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-name = "vcc-touchscreen"; - status = "okay"; -}; - &touchscreen { reg = <0x40>; compatible = "silead,gsl1680"; diff --git a/arch/arm/boot/dts/sun8i-a33-sinlinx-sina33.dts b/arch/arm/boot/dts/sun8i-a33-sinlinx-sina33.dts index fef6abc0a703..71bb9418c5f9 100644 --- a/arch/arm/boot/dts/sun8i-a33-sinlinx-sina33.dts +++ b/arch/arm/boot/dts/sun8i-a33-sinlinx-sina33.dts @@ -213,6 +213,11 @@ status = "okay"; }; +&usb_otg { + dr_mode = "peripheral"; + status = "okay"; +}; + &usbphy { status = "okay"; usb1_vbus-supply = <®_vcc5v0>; /* USB1 VBUS is always on */ diff --git a/arch/arm/boot/dts/sun8i-h3-nanopi-m1.dts b/arch/arm/boot/dts/sun8i-h3-nanopi-m1.dts new file mode 100644 index 000000000000..ec63d104b404 --- /dev/null +++ b/arch/arm/boot/dts/sun8i-h3-nanopi-m1.dts @@ -0,0 +1,64 @@ +/* + * Copyright (C) 2016 Milo Kim <woogyom.kim@gmail.com> + * + * This file is dual-licensed: you can use it either under the terms + * of the GPL or the X11 license, at your option. Note that this dual + * licensing only applies to this file, and not this project as a + * whole. + * + * a) This file is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of the + * License, or (at your option) any later version. + * + * This file is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * Or, alternatively, + * + * b) Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, + * copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following + * conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + */ + +#include "sun8i-h3-nanopi.dtsi" + +/ { + model = "FriendlyArm NanoPi M1"; + compatible = "friendlyarm,nanopi-m1", "allwinner,sun8i-h3"; +}; + +&ehci1 { + status = "okay"; +}; + +&ehci2 { + status = "okay"; +}; + +&ohci1 { + status = "okay"; +}; + +&ohci2 { + status = "okay"; +}; diff --git a/arch/arm/boot/dts/sun8i-h3-nanopi-neo.dts b/arch/arm/boot/dts/sun8i-h3-nanopi-neo.dts index 3d64cafc1e90..8d2cc6e9a03f 100644 --- a/arch/arm/boot/dts/sun8i-h3-nanopi-neo.dts +++ b/arch/arm/boot/dts/sun8i-h3-nanopi-neo.dts @@ -40,86 +40,9 @@ * OTHER DEALINGS IN THE SOFTWARE. */ -/dts-v1/; -#include "sun8i-h3.dtsi" -#include "sunxi-common-regulators.dtsi" - -#include <dt-bindings/gpio/gpio.h> -#include <dt-bindings/pinctrl/sun4i-a10.h> +#include "sun8i-h3-nanopi.dtsi" / { model = "FriendlyARM NanoPi NEO"; compatible = "friendlyarm,nanopi-neo", "allwinner,sun8i-h3"; - - aliases { - serial0 = &uart0; - }; - - chosen { - stdout-path = "serial0:115200n8"; - }; - - leds { - compatible = "gpio-leds"; - pinctrl-names = "default"; - pinctrl-0 = <&leds_opc>, <&leds_r_opc>; - - pwr { - label = "nanopi:green:pwr"; - gpios = <&r_pio 0 10 GPIO_ACTIVE_HIGH>; /* PL10 */ - default-state = "on"; - }; - - status { - label = "nanopi:blue:status"; - gpios = <&pio 0 10 GPIO_ACTIVE_HIGH>; /* PA10 */ - }; - }; -}; - -&ehci3 { - status = "okay"; -}; - -&mmc0 { - pinctrl-names = "default"; - pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin>; - vmmc-supply = <®_vcc3v3>; - bus-width = <4>; - cd-gpios = <&pio 5 6 GPIO_ACTIVE_HIGH>; /* PF6 */ - cd-inverted; - status = "okay"; -}; - -&ohci3 { - status = "okay"; -}; - -&pio { - leds_opc: led-pins { - allwinner,pins = "PA10"; - allwinner,function = "gpio_out"; - allwinner,drive = <SUN4I_PINCTRL_10_MA>; - allwinner,pull = <SUN4I_PINCTRL_NO_PULL>; - }; -}; - -&r_pio { - leds_r_opc: led-pins { - allwinner,pins = "PL10"; - allwinner,function = "gpio_out"; - allwinner,drive = <SUN4I_PINCTRL_10_MA>; - allwinner,pull = <SUN4I_PINCTRL_NO_PULL>; - }; -}; - -&uart0 { - pinctrl-names = "default"; - pinctrl-0 = <&uart0_pins_a>; - status = "okay"; -}; - -&usbphy { - /* USB VBUS is always on */ - status = "okay"; }; diff --git a/arch/arm/boot/dts/sun8i-h3-nanopi.dtsi b/arch/arm/boot/dts/sun8i-h3-nanopi.dtsi new file mode 100644 index 000000000000..8038aa29a5a7 --- /dev/null +++ b/arch/arm/boot/dts/sun8i-h3-nanopi.dtsi @@ -0,0 +1,144 @@ +/* + * Copyright (C) 2016 James Pettigrew <james@innovum.com.au> + * Copyright (C) 2016 Milo Kim <woogyom.kim@gmail.com> + * + * This file is dual-licensed: you can use it either under the terms + * of the GPL or the X11 license, at your option. Note that this dual + * licensing only applies to this file, and not this project as a + * whole. + * + * a) This file is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of the + * License, or (at your option) any later version. + * + * This file is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * Or, alternatively, + * + * b) Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, + * copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following + * conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + */ + +/dts-v1/; +#include "sun8i-h3.dtsi" +#include "sunxi-common-regulators.dtsi" + +#include <dt-bindings/gpio/gpio.h> +#include <dt-bindings/input/input.h> +#include <dt-bindings/pinctrl/sun4i-a10.h> + +/ { + aliases { + serial0 = &uart0; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; + + leds { + compatible = "gpio-leds"; + pinctrl-names = "default"; + pinctrl-0 = <&leds_npi>, <&leds_r_npi>; + + status { + label = "nanopi:blue:status"; + gpios = <&pio 0 10 GPIO_ACTIVE_HIGH>; + linux,default-trigger = "heartbeat"; + }; + + pwr { + label = "nanopi:green:pwr"; + gpios = <&r_pio 0 10 GPIO_ACTIVE_HIGH>; + default-state = "on"; + }; + }; + + r_gpio_keys { + compatible = "gpio-keys"; + input-name = "k1"; + pinctrl-names = "default"; + pinctrl-0 = <&sw_r_npi>; + + k1@0 { + label = "k1"; + linux,code = <KEY_POWER>; + gpios = <&r_pio 0 3 GPIO_ACTIVE_LOW>; + }; + }; +}; + +&ehci3 { + status = "okay"; +}; + +&mmc0 { + bus-width = <4>; + cd-gpios = <&pio 5 6 GPIO_ACTIVE_HIGH>; + cd-inverted; + pinctrl-names = "default"; + pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin>; + status = "okay"; + vmmc-supply = <®_vcc3v3>; +}; + +&ohci3 { + status = "okay"; +}; + +&pio { + leds_npi: led_pins@0 { + allwinner,pins = "PA10"; + allwinner,function = "gpio_out"; + allwinner,drive = <SUN4I_PINCTRL_10_MA>; + allwinner,pull = <SUN4I_PINCTRL_NO_PULL>; + }; +}; + +&r_pio { + leds_r_npi: led_pins@0 { + allwinner,pins = "PL10"; + allwinner,function = "gpio_out"; + allwinner,drive = <SUN4I_PINCTRL_10_MA>; + allwinner,pull = <SUN4I_PINCTRL_NO_PULL>; + }; + + sw_r_npi: key_pins@0 { + allwinner,pins = "PL3"; + allwinner,function = "gpio_in"; + allwinner,drive = <SUN4I_PINCTRL_10_MA>; + allwinner,pull = <SUN4I_PINCTRL_NO_PULL>; + }; +}; + +&uart0 { + pinctrl-names = "default"; + pinctrl-0 = <&uart0_pins_a>; + status = "okay"; +}; + +&usbphy { + status = "okay"; +}; diff --git a/arch/arm/boot/dts/sun8i-h3.dtsi b/arch/arm/boot/dts/sun8i-h3.dtsi index 75a865406d3e..3c6596f06ebc 100644 --- a/arch/arm/boot/dts/sun8i-h3.dtsi +++ b/arch/arm/boot/dts/sun8i-h3.dtsi @@ -321,7 +321,8 @@ reg = <0x01c20800 0x400>; interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&ccu CLK_BUS_PIO>; + clocks = <&ccu CLK_BUS_PIO>, <&osc24M>, <&osc32k>; + clock-names = "apb", "hosc", "losc"; gpio-controller; #gpio-cells = <3>; interrupt-controller; @@ -381,6 +382,20 @@ allwinner,pull = <SUN4I_PINCTRL_NO_PULL>; }; + spi0_pins: spi0 { + allwinner,pins = "PC0", "PC1", "PC2", "PC3"; + allwinner,function = "spi0"; + allwinner,drive = <SUN4I_PINCTRL_10_MA>; + allwinner,pull = <SUN4I_PINCTRL_NO_PULL>; + }; + + spi1_pins: spi1 { + allwinner,pins = "PA15", "PA16", "PA14", "PA13"; + allwinner,function = "spi1"; + allwinner,drive = <SUN4I_PINCTRL_10_MA>; + allwinner,pull = <SUN4I_PINCTRL_NO_PULL>; + }; + uart0_pins_a: uart0@0 { allwinner,pins = "PA4", "PA5"; allwinner,function = "uart0"; @@ -425,6 +440,38 @@ clocks = <&osc24M>; }; + spi0: spi@01c68000 { + compatible = "allwinner,sun8i-h3-spi"; + reg = <0x01c68000 0x1000>; + interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&ccu CLK_BUS_SPI0>, <&ccu CLK_SPI0>; + clock-names = "ahb", "mod"; + dmas = <&dma 23>, <&dma 23>; + dma-names = "rx", "tx"; + pinctrl-names = "default"; + pinctrl-0 = <&spi0_pins>; + resets = <&ccu RST_BUS_SPI0>; + status = "disabled"; + #address-cells = <1>; + #size-cells = <0>; + }; + + spi1: spi@01c69000 { + compatible = "allwinner,sun8i-h3-spi"; + reg = <0x01c69000 0x1000>; + interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&ccu CLK_BUS_SPI1>, <&ccu CLK_SPI1>; + clock-names = "ahb", "mod"; + dmas = <&dma 24>, <&dma 24>; + dma-names = "rx", "tx"; + pinctrl-names = "default"; + pinctrl-0 = <&spi1_pins>; + resets = <&ccu RST_BUS_SPI1>; + status = "disabled"; + #address-cells = <1>; + #size-cells = <0>; + }; + wdt0: watchdog@01c20ca0 { compatible = "allwinner,sun6i-a31-wdt"; reg = <0x01c20ca0 0x20>; @@ -568,7 +615,8 @@ compatible = "allwinner,sun8i-h3-r-pinctrl"; reg = <0x01f02c00 0x400>; interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&apb0_gates 0>; + clocks = <&apb0_gates 0>, <&osc24M>, <&osc32k>; + clock-names = "apb", "hosc", "losc"; resets = <&apb0_reset 0>; gpio-controller; #gpio-cells = <3>; diff --git a/arch/arm/boot/dts/sun8i-reference-design-tablet.dtsi b/arch/arm/boot/dts/sun8i-reference-design-tablet.dtsi index 08cd00143635..69bc0cd26ca7 100644 --- a/arch/arm/boot/dts/sun8i-reference-design-tablet.dtsi +++ b/arch/arm/boot/dts/sun8i-reference-design-tablet.dtsi @@ -209,6 +209,13 @@ status = "okay"; }; +®_ldo_io1 { + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-name = "vcc-touchscreen"; + status = "okay"; +}; + ®_rtc_ldo { regulator-name = "vcc-rtc"; }; diff --git a/arch/arm/boot/dts/sun9i-a80-cubieboard4.dts b/arch/arm/boot/dts/sun9i-a80-cubieboard4.dts index 439847acd41e..67b02fe7f11c 100644 --- a/arch/arm/boot/dts/sun9i-a80-cubieboard4.dts +++ b/arch/arm/boot/dts/sun9i-a80-cubieboard4.dts @@ -76,6 +76,14 @@ gpios = <&pio 7 6 GPIO_ACTIVE_HIGH>; /* PH6 */ }; }; + + wifi_pwrseq: wifi_pwrseq { + compatible = "mmc-pwrseq-simple"; + clocks = <&ac100_rtc 1>; + clock-names = "ext_clock"; + /* enables internal regulator and de-asserts reset */ + reset-gpios = <&r_pio 0 2 GPIO_ACTIVE_LOW>; /* PL2 WL-PMU-EN */ + }; }; &mmc0 { @@ -88,6 +96,21 @@ status = "okay"; }; +&mmc1 { + pinctrl-names = "default"; + pinctrl-0 = <&mmc1_pins>, <&wifi_en_pin_cubieboard4>; + vmmc-supply = <®_dldo1>; + vqmmc-supply = <®_cldo3>; + mmc-pwrseq = <&wifi_pwrseq>; + bus-width = <4>; + non-removable; + status = "okay"; +}; + +&mmc1_pins { + allwinner,pull = <SUN4I_PINCTRL_PULL_UP>; +}; + &mmc2 { pinctrl-names = "default"; pinctrl-0 = <&mmc2_8bit_pins>; @@ -128,6 +151,15 @@ status = "okay"; }; +&r_pio { + wifi_en_pin_cubieboard4: wifi_en_pin@0 { + allwinner,pins = "PL2"; + allwinner,function = "gpio_out"; + allwinner,drive = <SUN4I_PINCTRL_10_MA>; + allwinner,pull = <SUN4I_PINCTRL_NO_PULL>; + }; +}; + &r_rsb { status = "okay"; diff --git a/arch/arm/boot/dts/sun9i-a80-optimus.dts b/arch/arm/boot/dts/sun9i-a80-optimus.dts index ceb6ef15d669..7e036b2be762 100644 --- a/arch/arm/boot/dts/sun9i-a80-optimus.dts +++ b/arch/arm/boot/dts/sun9i-a80-optimus.dts @@ -105,6 +105,14 @@ enable-active-high; gpio = <&pio 7 5 GPIO_ACTIVE_HIGH>; /* PH5 */ }; + + wifi_pwrseq: wifi_pwrseq { + compatible = "mmc-pwrseq-simple"; + clocks = <&ac100_rtc 1>; + clock-names = "ext_clock"; + /* enables internal regulator and de-asserts reset */ + reset-gpios = <&r_pio 0 2 GPIO_ACTIVE_LOW>; /* PL2 WL-PMU-EN */ + }; }; &ehci0 { @@ -130,6 +138,21 @@ status = "okay"; }; +&mmc1 { + pinctrl-names = "default"; + pinctrl-0 = <&mmc1_pins>, <&wifi_en_pin_optimus>; + vmmc-supply = <®_dldo1>; + vqmmc-supply = <®_cldo3>; + mmc-pwrseq = <&wifi_pwrseq>; + bus-width = <4>; + non-removable; + status = "okay"; +}; + +&mmc1_pins { + allwinner,pull = <SUN4I_PINCTRL_PULL_UP>; +}; + &mmc2 { pinctrl-names = "default"; pinctrl-0 = <&mmc2_8bit_pins>; @@ -199,6 +222,13 @@ allwinner,drive = <SUN4I_PINCTRL_10_MA>; allwinner,pull = <SUN4I_PINCTRL_NO_PULL>; }; + + wifi_en_pin_optimus: wifi_en_pin@0 { + allwinner,pins = "PL2"; + allwinner,function = "gpio_out"; + allwinner,drive = <SUN4I_PINCTRL_10_MA>; + allwinner,pull = <SUN4I_PINCTRL_NO_PULL>; + }; }; &r_rsb { diff --git a/arch/arm/boot/dts/sun9i-a80.dtsi b/arch/arm/boot/dts/sun9i-a80.dtsi index 3c5214cbe4e6..979ad1aacfb1 100644 --- a/arch/arm/boot/dts/sun9i-a80.dtsi +++ b/arch/arm/boot/dts/sun9i-a80.dtsi @@ -678,7 +678,8 @@ <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&apb0_gates 5>; + clocks = <&apb0_gates 5>, <&osc24M>, <&osc32k>; + clock-names = "apb", "hosc", "losc"; gpio-controller; interrupt-controller; #interrupt-cells = <3>; @@ -700,6 +701,14 @@ allwinner,pull = <SUN4I_PINCTRL_NO_PULL>; }; + mmc1_pins: mmc1 { + allwinner,pins = "PG0", "PG1" ,"PG2", "PG3", + "PG4", "PG5"; + allwinner,function = "mmc1"; + allwinner,drive = <SUN4I_PINCTRL_30_MA>; + allwinner,pull = <SUN4I_PINCTRL_NO_PULL>; + }; + mmc2_8bit_pins: mmc2_8bit { allwinner,pins = "PC6", "PC7", "PC8", "PC9", "PC10", "PC11", "PC12", @@ -894,7 +903,8 @@ reg = <0x08002c00 0x400>; interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&apbs_gates 0>; + clocks = <&apbs_gates 0>, <&osc24M>, <&osc32k>; + clock-names = "apb", "hosc", "losc"; resets = <&apbs_rst 0>; gpio-controller; interrupt-controller; diff --git a/arch/arm/boot/dts/tegra124-apalis.dtsi b/arch/arm/boot/dts/tegra124-apalis.dtsi index e7a73db17613..0819721dda59 100644 --- a/arch/arm/boot/dts/tegra124-apalis.dtsi +++ b/arch/arm/boot/dts/tegra124-apalis.dtsi @@ -1595,7 +1595,7 @@ clock-frequency = <400000>; /* SGTL5000 audio codec */ - sgtl5000: codec@0a { + sgtl5000: codec@a { compatible = "fsl,sgtl5000"; reg = <0x0a>; VDDA-supply = <®_3v3>; diff --git a/arch/arm/boot/dts/tegra124-nyan.dtsi b/arch/arm/boot/dts/tegra124-nyan.dtsi index 271505e0715f..eabfa655a3cd 100644 --- a/arch/arm/boot/dts/tegra124-nyan.dtsi +++ b/arch/arm/boot/dts/tegra124-nyan.dtsi @@ -42,6 +42,12 @@ }; }; + gpu@0,57000000 { + status = "okay"; + + vdd-supply = <&vdd_gpu>; + }; + serial@70006000 { /* Debug connector on the bottom of the board near SD card. */ status = "okay"; @@ -214,7 +220,7 @@ regulator-always-on; }; - sd6 { + vdd_gpu: sd6 { regulator-name = "+VDD_GPU_AP"; regulator-min-microvolt = <650000>; regulator-max-microvolt = <1200000>; diff --git a/arch/arm/boot/dts/tegra20.dtsi b/arch/arm/boot/dts/tegra20.dtsi index 2207c08e3fa3..e8807503f87c 100644 --- a/arch/arm/boot/dts/tegra20.dtsi +++ b/arch/arm/boot/dts/tegra20.dtsi @@ -376,6 +376,19 @@ status = "disabled"; }; + gmi@70009000 { + compatible = "nvidia,tegra20-gmi"; + reg = <0x70009000 0x1000>; + #address-cells = <2>; + #size-cells = <1>; + ranges = <0 0 0xd0000000 0xfffffff>; + clocks = <&tegra_car TEGRA20_CLK_NOR>; + clock-names = "gmi"; + resets = <&tegra_car 42>; + reset-names = "gmi"; + status = "disabled"; + }; + pwm: pwm@7000a000 { compatible = "nvidia,tegra20-pwm"; reg = <0x7000a000 0x100>; diff --git a/arch/arm/boot/dts/tegra30-apalis.dtsi b/arch/arm/boot/dts/tegra30-apalis.dtsi index 192b95177aac..f6c7c3e958ac 100644 --- a/arch/arm/boot/dts/tegra30-apalis.dtsi +++ b/arch/arm/boot/dts/tegra30-apalis.dtsi @@ -48,6 +48,24 @@ pinctrl-0 = <&state_default>; state_default: pinmux { + /* Analogue Audio (On-module) */ + clk1_out_pw4 { + nvidia,pins = "clk1_out_pw4"; + nvidia,function = "extperiph1"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_DISABLE>; + }; + dap3_fs_pp0 { + nvidia,pins = "dap3_fs_pp0", + "dap3_sclk_pp3", + "dap3_din_pp1", + "dap3_dout_pp2"; + nvidia,function = "i2s2"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + }; + /* Apalis BKL1_ON */ pv2 { nvidia,pins = "pv2"; @@ -429,6 +447,15 @@ status = "okay"; clock-frequency = <100000>; + /* SGTL5000 audio codec */ + sgtl5000: codec@a { + compatible = "fsl,sgtl5000"; + reg = <0x0a>; + VDDA-supply = <&sys_3v3_reg>; + VDDIO-supply = <&sys_3v3_reg>; + clocks = <&tegra_car TEGRA30_CLK_EXTERN1>; + }; + pmic: tps65911@2d { compatible = "ti,tps65911"; reg = <0x2d>; @@ -660,6 +687,12 @@ nvidia,sys-clock-req-active-high; }; + ahub@70080000 { + i2s@70080500 { + status = "okay"; + }; + }; + /* eMMC */ sdhci@78000600 { status = "okay"; @@ -733,4 +766,20 @@ regulator-always-on; }; }; + + sound { + compatible = "toradex,tegra-audio-sgtl5000-apalis_t30", + "nvidia,tegra-audio-sgtl5000"; + nvidia,model = "Toradex Apalis T30"; + nvidia,audio-routing = + "Headphone Jack", "HP_OUT", + "LINE_IN", "Line In Jack", + "MIC_IN", "Mic Jack"; + nvidia,i2s-controller = <&tegra_i2s2>; + nvidia,audio-codec = <&sgtl5000>; + clocks = <&tegra_car TEGRA30_CLK_PLL_A>, + <&tegra_car TEGRA30_CLK_PLL_A_OUT0>, + <&tegra_car TEGRA30_CLK_EXTERN1>; + clock-names = "pll_a", "pll_a_out0", "mclk"; + }; }; diff --git a/arch/arm/boot/dts/tegra30-colibri.dtsi b/arch/arm/boot/dts/tegra30-colibri.dtsi index a265534cd314..5360d638eedc 100644 --- a/arch/arm/boot/dts/tegra30-colibri.dtsi +++ b/arch/arm/boot/dts/tegra30-colibri.dtsi @@ -29,6 +29,24 @@ pinctrl-0 = <&state_default>; state_default: pinmux { + /* Analogue Audio (On-module) */ + clk1_out_pw4 { + nvidia,pins = "clk1_out_pw4"; + nvidia,function = "extperiph1"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_DISABLE>; + }; + dap3_fs_pp0 { + nvidia,pins = "dap3_fs_pp0", + "dap3_sclk_pp3", + "dap3_din_pp1", + "dap3_dout_pp2"; + nvidia,function = "i2s2"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + }; + /* Colibri BL_ON */ pv2 { nvidia,pins = "pv2"; @@ -207,6 +225,15 @@ status = "okay"; clock-frequency = <100000>; + /* SGTL5000 audio codec */ + sgtl5000: codec@a { + compatible = "fsl,sgtl5000"; + reg = <0x0a>; + VDDA-supply = <&sys_3v3_reg>; + VDDIO-supply = <&sys_3v3_reg>; + clocks = <&tegra_car TEGRA30_CLK_EXTERN1>; + }; + pmic: tps65911@2d { compatible = "ti,tps65911"; reg = <0x2d>; @@ -396,6 +423,12 @@ nvidia,sys-clock-req-active-high; }; + ahub@70080000 { + i2s@70080500 { + status = "okay"; + }; + }; + /* eMMC */ sdhci@78000600 { status = "okay"; @@ -471,4 +504,20 @@ regulator-always-on; }; }; + + sound { + compatible = "toradex,tegra-audio-sgtl5000-colibri_t30", + "nvidia,tegra-audio-sgtl5000"; + nvidia,model = "Toradex Colibri T30"; + nvidia,audio-routing = + "Headphone Jack", "HP_OUT", + "LINE_IN", "Line In Jack", + "MIC_IN", "Mic Jack"; + nvidia,i2s-controller = <&tegra_i2s2>; + nvidia,audio-codec = <&sgtl5000>; + clocks = <&tegra_car TEGRA30_CLK_PLL_A>, + <&tegra_car TEGRA30_CLK_PLL_A_OUT0>, + <&tegra_car TEGRA30_CLK_EXTERN1>; + clock-names = "pll_a", "pll_a_out0", "mclk"; + }; }; diff --git a/arch/arm/boot/dts/tegra30.dtsi b/arch/arm/boot/dts/tegra30.dtsi index 5030065cbdfe..bbb1c002e7f1 100644 --- a/arch/arm/boot/dts/tegra30.dtsi +++ b/arch/arm/boot/dts/tegra30.dtsi @@ -439,6 +439,19 @@ status = "disabled"; }; + gmi@70009000 { + compatible = "nvidia,tegra30-gmi"; + reg = <0x70009000 0x1000>; + #address-cells = <2>; + #size-cells = <1>; + ranges = <0 0 0x48000000 0x7ffffff>; + clocks = <&tegra_car TEGRA30_CLK_NOR>; + clock-names = "gmi"; + resets = <&tegra_car 42>; + reset-names = "gmi"; + status = "disabled"; + }; + pwm: pwm@7000a000 { compatible = "nvidia,tegra30-pwm", "nvidia,tegra20-pwm"; reg = <0x7000a000 0x100>; diff --git a/arch/arm/boot/dts/tps65217.dtsi b/arch/arm/boot/dts/tps65217.dtsi index a63272422d76..02de56b55823 100644 --- a/arch/arm/boot/dts/tps65217.dtsi +++ b/arch/arm/boot/dts/tps65217.dtsi @@ -13,6 +13,18 @@ &tps { compatible = "ti,tps65217"; + interrupt-controller; + #interrupt-cells = <1>; + + charger { + compatible = "ti,tps65217-charger"; + status = "disabled"; + }; + + pwrbutton { + compatible = "ti,tps65217-pwrbutton"; + status = "disabled"; + }; regulators { #address-cells = <1>; diff --git a/arch/arm/boot/dts/uniphier-common32.dtsi b/arch/arm/boot/dts/uniphier-common32.dtsi deleted file mode 100644 index 8c8a85176b64..000000000000 --- a/arch/arm/boot/dts/uniphier-common32.dtsi +++ /dev/null @@ -1,199 +0,0 @@ -/* - * Device Tree Source commonly used by UniPhier ARM SoCs - * - * Copyright (C) 2015-2016 Socionext Inc. - * Author: Masahiro Yamada <yamada.masahiro@socionext.com> - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of the - * License, or (at your option) any later version. - * - * This file is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - */ - -/include/ "skeleton.dtsi" - -/ { - psci { - compatible = "arm,psci-0.2"; - method = "smc"; - }; - - clocks { - refclk: ref { - #clock-cells = <0>; - compatible = "fixed-clock"; - }; - }; - - soc: soc { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <1>; - ranges; - interrupt-parent = <&intc>; - - serial0: serial@54006800 { - compatible = "socionext,uniphier-uart"; - status = "disabled"; - reg = <0x54006800 0x40>; - interrupts = <0 33 4>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart0>; - clocks = <&peri_clk 0>; - }; - - serial1: serial@54006900 { - compatible = "socionext,uniphier-uart"; - status = "disabled"; - reg = <0x54006900 0x40>; - interrupts = <0 35 4>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart1>; - clocks = <&peri_clk 1>; - }; - - serial2: serial@54006a00 { - compatible = "socionext,uniphier-uart"; - status = "disabled"; - reg = <0x54006a00 0x40>; - interrupts = <0 37 4>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart2>; - clocks = <&peri_clk 2>; - }; - - serial3: serial@54006b00 { - compatible = "socionext,uniphier-uart"; - status = "disabled"; - reg = <0x54006b00 0x40>; - interrupts = <0 177 4>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart3>; - clocks = <&peri_clk 3>; - }; - - system_bus: system-bus@58c00000 { - compatible = "socionext,uniphier-system-bus"; - status = "disabled"; - reg = <0x58c00000 0x400>; - #address-cells = <2>; - #size-cells = <1>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_system_bus>; - }; - - smpctrl@59800000 { - compatible = "socionext,uniphier-smpctrl"; - reg = <0x59801000 0x400>; - }; - - mioctrl@59810000 { - compatible = "socionext,uniphier-mioctrl", - "simple-mfd", "syscon"; - reg = <0x59810000 0x800>; - - mio_clk: clock { - #clock-cells = <1>; - }; - - mio_rst: reset { - #reset-cells = <1>; - }; - }; - - perictrl@59820000 { - compatible = "socionext,uniphier-perictrl", - "simple-mfd", "syscon"; - reg = <0x59820000 0x200>; - - peri_clk: clock { - #clock-cells = <1>; - }; - - peri_rst: reset { - #reset-cells = <1>; - }; - }; - - timer@60000200 { - compatible = "arm,cortex-a9-global-timer"; - reg = <0x60000200 0x20>; - interrupts = <1 11 0x104>; - clocks = <&arm_timer_clk>; - }; - - timer@60000600 { - compatible = "arm,cortex-a9-twd-timer"; - reg = <0x60000600 0x20>; - interrupts = <1 13 0x104>; - clocks = <&arm_timer_clk>; - }; - - intc: interrupt-controller@60001000 { - compatible = "arm,cortex-a9-gic"; - reg = <0x60001000 0x1000>, - <0x60000100 0x100>; - #interrupt-cells = <3>; - interrupt-controller; - }; - - soc-glue@5f800000 { - compatible = "socionext,uniphier-soc-glue", - "simple-mfd", "syscon"; - reg = <0x5f800000 0x2000>; - - pinctrl: pinctrl { - /* specify compatible in each SoC DTSI */ - }; - }; - - sysctrl@61840000 { - compatible = "socionext,uniphier-sysctrl", - "simple-mfd", "syscon"; - reg = <0x61840000 0x4000>; - - sys_clk: clock { - #clock-cells = <1>; - }; - - sys_rst: reset { - #reset-cells = <1>; - }; - }; - }; -}; - -/include/ "uniphier-pinctrl.dtsi" diff --git a/arch/arm/boot/dts/uniphier-ld4.dtsi b/arch/arm/boot/dts/uniphier-ld4.dtsi index 95f342c9d9c1..a7c494d7c43a 100644 --- a/arch/arm/boot/dts/uniphier-ld4.dtsi +++ b/arch/arm/boot/dts/uniphier-ld4.dtsi @@ -43,7 +43,7 @@ * OTHER DEALINGS IN THE SOFTWARE. */ -/include/ "uniphier-common32.dtsi" +/include/ "skeleton.dtsi" / { compatible = "socionext,uniphier-ld4"; @@ -61,147 +61,267 @@ }; }; + psci { + compatible = "arm,psci-0.2"; + method = "smc"; + }; + clocks { + refclk: ref { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <24576000>; + }; + arm_timer_clk: arm_timer_clk { #clock-cells = <0>; compatible = "fixed-clock"; clock-frequency = <50000000>; }; }; -}; - -&soc { - l2: l2-cache@500c0000 { - compatible = "socionext,uniphier-system-cache"; - reg = <0x500c0000 0x2000>, <0x503c0100 0x4>, <0x506c0000 0x400>; - interrupts = <0 174 4>, <0 175 4>; - cache-unified; - cache-size = <(512 * 1024)>; - cache-sets = <256>; - cache-line-size = <128>; - cache-level = <2>; - }; - i2c0: i2c@58400000 { - compatible = "socionext,uniphier-i2c"; - status = "disabled"; - reg = <0x58400000 0x40>; + soc { + compatible = "simple-bus"; #address-cells = <1>; - #size-cells = <0>; - interrupts = <0 41 1>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c0>; - clocks = <&peri_clk 4>; - clock-frequency = <100000>; - }; + #size-cells = <1>; + ranges; + interrupt-parent = <&intc>; - i2c1: i2c@58480000 { - compatible = "socionext,uniphier-i2c"; - status = "disabled"; - reg = <0x58480000 0x40>; - #address-cells = <1>; - #size-cells = <0>; - interrupts = <0 42 1>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c1>; - clocks = <&peri_clk 5>; - clock-frequency = <100000>; - }; + l2: l2-cache@500c0000 { + compatible = "socionext,uniphier-system-cache"; + reg = <0x500c0000 0x2000>, <0x503c0100 0x4>, + <0x506c0000 0x400>; + interrupts = <0 174 4>, <0 175 4>; + cache-unified; + cache-size = <(512 * 1024)>; + cache-sets = <256>; + cache-line-size = <128>; + cache-level = <2>; + }; - /* chip-internal connection for DMD */ - i2c2: i2c@58500000 { - compatible = "socionext,uniphier-i2c"; - reg = <0x58500000 0x40>; - #address-cells = <1>; - #size-cells = <0>; - interrupts = <0 43 1>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c2>; - clocks = <&peri_clk 6>; - clock-frequency = <400000>; - }; + serial0: serial@54006800 { + compatible = "socionext,uniphier-uart"; + status = "disabled"; + reg = <0x54006800 0x40>; + interrupts = <0 33 4>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart0>; + clocks = <&peri_clk 0>; + }; - i2c3: i2c@58580000 { - compatible = "socionext,uniphier-i2c"; - status = "disabled"; - reg = <0x58580000 0x40>; - #address-cells = <1>; - #size-cells = <0>; - interrupts = <0 44 1>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c3>; - clocks = <&peri_clk 7>; - clock-frequency = <100000>; - }; + serial1: serial@54006900 { + compatible = "socionext,uniphier-uart"; + status = "disabled"; + reg = <0x54006900 0x40>; + interrupts = <0 35 4>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart1>; + clocks = <&peri_clk 1>; + }; - usb0: usb@5a800100 { - compatible = "socionext,uniphier-ehci", "generic-ehci"; - status = "disabled"; - reg = <0x5a800100 0x100>; - interrupts = <0 80 4>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usb0>; - clocks = <&mio_clk 7>, <&mio_clk 8>, <&mio_clk 12>; - resets = <&mio_rst 7>, <&mio_rst 8>, <&mio_rst 12>, <&sys_rst 8>; - }; + serial2: serial@54006a00 { + compatible = "socionext,uniphier-uart"; + status = "disabled"; + reg = <0x54006a00 0x40>; + interrupts = <0 37 4>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart2>; + clocks = <&peri_clk 2>; + }; - usb1: usb@5a810100 { - compatible = "socionext,uniphier-ehci", "generic-ehci"; - status = "disabled"; - reg = <0x5a810100 0x100>; - interrupts = <0 81 4>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usb1>; - clocks = <&mio_clk 7>, <&mio_clk 9>, <&mio_clk 13>; - resets = <&mio_rst 7>, <&mio_rst 9>, <&mio_rst 13>, <&sys_rst 8>; - }; + serial3: serial@54006b00 { + compatible = "socionext,uniphier-uart"; + status = "disabled"; + reg = <0x54006b00 0x40>; + interrupts = <0 29 4>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart3>; + clocks = <&peri_clk 3>; + }; - usb2: usb@5a820100 { - compatible = "socionext,uniphier-ehci", "generic-ehci"; - status = "disabled"; - reg = <0x5a820100 0x100>; - interrupts = <0 82 4>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usb2>; - clocks = <&mio_clk 7>, <&mio_clk 10>, <&mio_clk 14>; - resets = <&mio_rst 7>, <&mio_rst 10>, <&mio_rst 14>, <&sys_rst 8>; - }; + i2c0: i2c@58400000 { + compatible = "socionext,uniphier-i2c"; + status = "disabled"; + reg = <0x58400000 0x40>; + #address-cells = <1>; + #size-cells = <0>; + interrupts = <0 41 1>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c0>; + clocks = <&peri_clk 4>; + clock-frequency = <100000>; + }; -}; + i2c1: i2c@58480000 { + compatible = "socionext,uniphier-i2c"; + status = "disabled"; + reg = <0x58480000 0x40>; + #address-cells = <1>; + #size-cells = <0>; + interrupts = <0 42 1>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c1>; + clocks = <&peri_clk 5>; + clock-frequency = <100000>; + }; -&refclk { - clock-frequency = <24576000>; -}; + /* chip-internal connection for DMD */ + i2c2: i2c@58500000 { + compatible = "socionext,uniphier-i2c"; + reg = <0x58500000 0x40>; + #address-cells = <1>; + #size-cells = <0>; + interrupts = <0 43 1>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c2>; + clocks = <&peri_clk 6>; + clock-frequency = <400000>; + }; -&serial3 { - interrupts = <0 29 4>; -}; + i2c3: i2c@58580000 { + compatible = "socionext,uniphier-i2c"; + status = "disabled"; + reg = <0x58580000 0x40>; + #address-cells = <1>; + #size-cells = <0>; + interrupts = <0 44 1>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c3>; + clocks = <&peri_clk 7>; + clock-frequency = <100000>; + }; -&mio_clk { - compatible = "socionext,uniphier-ld4-mio-clock"; -}; + system_bus: system-bus@58c00000 { + compatible = "socionext,uniphier-system-bus"; + status = "disabled"; + reg = <0x58c00000 0x400>; + #address-cells = <2>; + #size-cells = <1>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_system_bus>; + }; -&mio_rst { - compatible = "socionext,uniphier-ld4-mio-reset"; - resets = <&sys_rst 7>; -}; + smpctrl@59800000 { + compatible = "socionext,uniphier-smpctrl"; + reg = <0x59801000 0x400>; + }; -&peri_clk { - compatible = "socionext,uniphier-ld4-peri-clock"; -}; + mioctrl@59810000 { + compatible = "socionext,uniphier-ld4-mioctrl", + "simple-mfd", "syscon"; + reg = <0x59810000 0x800>; -&peri_rst { - compatible = "socionext,uniphier-ld4-peri-reset"; -}; + mio_clk: clock { + compatible = "socionext,uniphier-ld4-mio-clock"; + #clock-cells = <1>; + }; -&pinctrl { - compatible = "socionext,uniphier-ld4-pinctrl"; -}; + mio_rst: reset { + compatible = "socionext,uniphier-ld4-mio-reset"; + #reset-cells = <1>; + }; + }; -&sys_clk { - compatible = "socionext,uniphier-ld4-clock"; -}; + perictrl@59820000 { + compatible = "socionext,uniphier-ld4-perictrl", + "simple-mfd", "syscon"; + reg = <0x59820000 0x200>; + + peri_clk: clock { + compatible = "socionext,uniphier-ld4-peri-clock"; + #clock-cells = <1>; + }; + + peri_rst: reset { + compatible = "socionext,uniphier-ld4-peri-reset"; + #reset-cells = <1>; + }; + }; + + usb0: usb@5a800100 { + compatible = "socionext,uniphier-ehci", "generic-ehci"; + status = "disabled"; + reg = <0x5a800100 0x100>; + interrupts = <0 80 4>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usb0>; + clocks = <&mio_clk 7>, <&mio_clk 8>, <&mio_clk 12>; + resets = <&sys_rst 8>, <&mio_rst 7>, <&mio_rst 8>, + <&mio_rst 12>; + }; + + usb1: usb@5a810100 { + compatible = "socionext,uniphier-ehci", "generic-ehci"; + status = "disabled"; + reg = <0x5a810100 0x100>; + interrupts = <0 81 4>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usb1>; + clocks = <&mio_clk 7>, <&mio_clk 9>, <&mio_clk 13>; + resets = <&sys_rst 8>, <&mio_rst 7>, <&mio_rst 9>, + <&mio_rst 13>; + }; -&sys_rst { - compatible = "socionext,uniphier-ld4-reset"; + usb2: usb@5a820100 { + compatible = "socionext,uniphier-ehci", "generic-ehci"; + status = "disabled"; + reg = <0x5a820100 0x100>; + interrupts = <0 82 4>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usb2>; + clocks = <&mio_clk 7>, <&mio_clk 10>, <&mio_clk 14>; + resets = <&sys_rst 8>, <&mio_rst 7>, <&mio_rst 10>, + <&mio_rst 14>; + }; + + soc-glue@5f800000 { + compatible = "socionext,uniphier-ld4-soc-glue", + "simple-mfd", "syscon"; + reg = <0x5f800000 0x2000>; + + pinctrl: pinctrl { + compatible = "socionext,uniphier-ld4-pinctrl"; + }; + }; + + timer@60000200 { + compatible = "arm,cortex-a9-global-timer"; + reg = <0x60000200 0x20>; + interrupts = <1 11 0x104>; + clocks = <&arm_timer_clk>; + }; + + timer@60000600 { + compatible = "arm,cortex-a9-twd-timer"; + reg = <0x60000600 0x20>; + interrupts = <1 13 0x104>; + clocks = <&arm_timer_clk>; + }; + + intc: interrupt-controller@60001000 { + compatible = "arm,cortex-a9-gic"; + reg = <0x60001000 0x1000>, + <0x60000100 0x100>; + #interrupt-cells = <3>; + interrupt-controller; + }; + + sysctrl@61840000 { + compatible = "socionext,uniphier-ld4-sysctrl", + "simple-mfd", "syscon"; + reg = <0x61840000 0x10000>; + + sys_clk: clock { + compatible = "socionext,uniphier-ld4-clock"; + #clock-cells = <1>; + }; + + sys_rst: reset { + compatible = "socionext,uniphier-ld4-reset"; + #reset-cells = <1>; + }; + }; + }; }; + +/include/ "uniphier-pinctrl.dtsi" diff --git a/arch/arm/boot/dts/uniphier-pro4.dtsi b/arch/arm/boot/dts/uniphier-pro4.dtsi index ba700267ad66..e960b09ff01c 100644 --- a/arch/arm/boot/dts/uniphier-pro4.dtsi +++ b/arch/arm/boot/dts/uniphier-pro4.dtsi @@ -43,7 +43,7 @@ * OTHER DEALINGS IN THE SOFTWARE. */ -/include/ "uniphier-common32.dtsi" +/include/ "skeleton.dtsi" / { compatible = "socionext,uniphier-pro4"; @@ -69,155 +69,279 @@ }; }; + psci { + compatible = "arm,psci-0.2"; + method = "smc"; + }; + clocks { + refclk: ref { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <25000000>; + }; + arm_timer_clk: arm_timer_clk { #clock-cells = <0>; compatible = "fixed-clock"; clock-frequency = <50000000>; }; }; -}; -&soc { - l2: l2-cache@500c0000 { - compatible = "socionext,uniphier-system-cache"; - reg = <0x500c0000 0x2000>, <0x503c0100 0x4>, <0x506c0000 0x400>; - interrupts = <0 174 4>, <0 175 4>; - cache-unified; - cache-size = <(768 * 1024)>; - cache-sets = <256>; - cache-line-size = <128>; - cache-level = <2>; - }; - - i2c0: i2c@58780000 { - compatible = "socionext,uniphier-fi2c"; - status = "disabled"; - reg = <0x58780000 0x80>; + soc { + compatible = "simple-bus"; #address-cells = <1>; - #size-cells = <0>; - interrupts = <0 41 4>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c0>; - clocks = <&peri_clk 4>; - clock-frequency = <100000>; - }; + #size-cells = <1>; + ranges; + interrupt-parent = <&intc>; - i2c1: i2c@58781000 { - compatible = "socionext,uniphier-fi2c"; - status = "disabled"; - reg = <0x58781000 0x80>; - #address-cells = <1>; - #size-cells = <0>; - interrupts = <0 42 4>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c1>; - clocks = <&peri_clk 5>; - clock-frequency = <100000>; - }; + l2: l2-cache@500c0000 { + compatible = "socionext,uniphier-system-cache"; + reg = <0x500c0000 0x2000>, <0x503c0100 0x4>, + <0x506c0000 0x400>; + interrupts = <0 174 4>, <0 175 4>; + cache-unified; + cache-size = <(768 * 1024)>; + cache-sets = <256>; + cache-line-size = <128>; + cache-level = <2>; + }; - i2c2: i2c@58782000 { - compatible = "socionext,uniphier-fi2c"; - status = "disabled"; - reg = <0x58782000 0x80>; - #address-cells = <1>; - #size-cells = <0>; - interrupts = <0 43 4>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c2>; - clocks = <&peri_clk 6>; - clock-frequency = <100000>; - }; + serial0: serial@54006800 { + compatible = "socionext,uniphier-uart"; + status = "disabled"; + reg = <0x54006800 0x40>; + interrupts = <0 33 4>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart0>; + clocks = <&peri_clk 0>; + }; - i2c3: i2c@58783000 { - compatible = "socionext,uniphier-fi2c"; - status = "disabled"; - reg = <0x58783000 0x80>; - #address-cells = <1>; - #size-cells = <0>; - interrupts = <0 44 4>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c3>; - clocks = <&peri_clk 7>; - clock-frequency = <100000>; - }; + serial1: serial@54006900 { + compatible = "socionext,uniphier-uart"; + status = "disabled"; + reg = <0x54006900 0x40>; + interrupts = <0 35 4>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart1>; + clocks = <&peri_clk 1>; + }; - /* i2c4 does not exist */ + serial2: serial@54006a00 { + compatible = "socionext,uniphier-uart"; + status = "disabled"; + reg = <0x54006a00 0x40>; + interrupts = <0 37 4>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart2>; + clocks = <&peri_clk 2>; + }; - /* chip-internal connection for DMD */ - i2c5: i2c@58785000 { - compatible = "socionext,uniphier-fi2c"; - reg = <0x58785000 0x80>; - #address-cells = <1>; - #size-cells = <0>; - interrupts = <0 25 4>; - clocks = <&peri_clk 9>; - clock-frequency = <400000>; - }; + serial3: serial@54006b00 { + compatible = "socionext,uniphier-uart"; + status = "disabled"; + reg = <0x54006b00 0x40>; + interrupts = <0 177 4>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart3>; + clocks = <&peri_clk 3>; + }; - /* chip-internal connection for HDMI */ - i2c6: i2c@58786000 { - compatible = "socionext,uniphier-fi2c"; - reg = <0x58786000 0x80>; - #address-cells = <1>; - #size-cells = <0>; - interrupts = <0 26 4>; - clocks = <&peri_clk 10>; - clock-frequency = <400000>; - }; + i2c0: i2c@58780000 { + compatible = "socionext,uniphier-fi2c"; + status = "disabled"; + reg = <0x58780000 0x80>; + #address-cells = <1>; + #size-cells = <0>; + interrupts = <0 41 4>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c0>; + clocks = <&peri_clk 4>; + clock-frequency = <100000>; + }; - usb2: usb@5a800100 { - compatible = "socionext,uniphier-ehci", "generic-ehci"; - status = "disabled"; - reg = <0x5a800100 0x100>; - interrupts = <0 80 4>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usb2>; - clocks = <&mio_clk 7>, <&mio_clk 8>, <&mio_clk 12>; - resets = <&mio_rst 7>, <&mio_rst 8>, <&mio_rst 12>, <&sys_rst 8>; - }; + i2c1: i2c@58781000 { + compatible = "socionext,uniphier-fi2c"; + status = "disabled"; + reg = <0x58781000 0x80>; + #address-cells = <1>; + #size-cells = <0>; + interrupts = <0 42 4>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c1>; + clocks = <&peri_clk 5>; + clock-frequency = <100000>; + }; - usb3: usb@5a810100 { - compatible = "socionext,uniphier-ehci", "generic-ehci"; - status = "disabled"; - reg = <0x5a810100 0x100>; - interrupts = <0 81 4>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usb3>; - clocks = <&mio_clk 7>, <&mio_clk 9>, <&mio_clk 13>; - resets = <&mio_rst 7>, <&mio_rst 9>, <&mio_rst 13>, <&sys_rst 8>; - }; -}; + i2c2: i2c@58782000 { + compatible = "socionext,uniphier-fi2c"; + status = "disabled"; + reg = <0x58782000 0x80>; + #address-cells = <1>; + #size-cells = <0>; + interrupts = <0 43 4>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c2>; + clocks = <&peri_clk 6>; + clock-frequency = <100000>; + }; -&refclk { - clock-frequency = <25000000>; -}; + i2c3: i2c@58783000 { + compatible = "socionext,uniphier-fi2c"; + status = "disabled"; + reg = <0x58783000 0x80>; + #address-cells = <1>; + #size-cells = <0>; + interrupts = <0 44 4>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c3>; + clocks = <&peri_clk 7>; + clock-frequency = <100000>; + }; -&mio_clk { - compatible = "socionext,uniphier-pro4-mio-clock"; -}; + /* i2c4 does not exist */ -&mio_rst { - compatible = "socionext,uniphier-pro4-mio-reset"; - resets = <&sys_rst 7>; -}; + /* chip-internal connection for DMD */ + i2c5: i2c@58785000 { + compatible = "socionext,uniphier-fi2c"; + reg = <0x58785000 0x80>; + #address-cells = <1>; + #size-cells = <0>; + interrupts = <0 25 4>; + clocks = <&peri_clk 9>; + clock-frequency = <400000>; + }; -&peri_clk { - compatible = "socionext,uniphier-pro4-peri-clock"; -}; + /* chip-internal connection for HDMI */ + i2c6: i2c@58786000 { + compatible = "socionext,uniphier-fi2c"; + reg = <0x58786000 0x80>; + #address-cells = <1>; + #size-cells = <0>; + interrupts = <0 26 4>; + clocks = <&peri_clk 10>; + clock-frequency = <400000>; + }; -&peri_rst { - compatible = "socionext,uniphier-pro4-peri-reset"; -}; + system_bus: system-bus@58c00000 { + compatible = "socionext,uniphier-system-bus"; + status = "disabled"; + reg = <0x58c00000 0x400>; + #address-cells = <2>; + #size-cells = <1>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_system_bus>; + }; -&pinctrl { - compatible = "socionext,uniphier-pro4-pinctrl"; -}; + smpctrl@59800000 { + compatible = "socionext,uniphier-smpctrl"; + reg = <0x59801000 0x400>; + }; -&sys_clk { - compatible = "socionext,uniphier-pro4-clock"; -}; + mioctrl@59810000 { + compatible = "socionext,uniphier-pro4-mioctrl", + "simple-mfd", "syscon"; + reg = <0x59810000 0x800>; + + mio_clk: clock { + compatible = "socionext,uniphier-pro4-mio-clock"; + #clock-cells = <1>; + }; + + mio_rst: reset { + compatible = "socionext,uniphier-pro4-mio-reset"; + #reset-cells = <1>; + }; + }; + + perictrl@59820000 { + compatible = "socionext,uniphier-pro4-perictrl", + "simple-mfd", "syscon"; + reg = <0x59820000 0x200>; + + peri_clk: clock { + compatible = "socionext,uniphier-pro4-peri-clock"; + #clock-cells = <1>; + }; + + peri_rst: reset { + compatible = "socionext,uniphier-pro4-peri-reset"; + #reset-cells = <1>; + }; + }; -&sys_rst { - compatible = "socionext,uniphier-pro4-reset"; + usb2: usb@5a800100 { + compatible = "socionext,uniphier-ehci", "generic-ehci"; + status = "disabled"; + reg = <0x5a800100 0x100>; + interrupts = <0 80 4>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usb2>; + clocks = <&mio_clk 7>, <&mio_clk 8>, <&mio_clk 12>; + resets = <&sys_rst 8>, <&mio_rst 7>, <&mio_rst 8>, + <&mio_rst 12>; + }; + + usb3: usb@5a810100 { + compatible = "socionext,uniphier-ehci", "generic-ehci"; + status = "disabled"; + reg = <0x5a810100 0x100>; + interrupts = <0 81 4>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usb3>; + clocks = <&mio_clk 7>, <&mio_clk 9>, <&mio_clk 13>; + resets = <&sys_rst 8>, <&mio_rst 7>, <&mio_rst 9>, + <&mio_rst 13>; + }; + + soc-glue@5f800000 { + compatible = "socionext,uniphier-pro4-soc-glue", + "simple-mfd", "syscon"; + reg = <0x5f800000 0x2000>; + + pinctrl: pinctrl { + compatible = "socionext,uniphier-pro4-pinctrl"; + }; + }; + + timer@60000200 { + compatible = "arm,cortex-a9-global-timer"; + reg = <0x60000200 0x20>; + interrupts = <1 11 0x304>; + clocks = <&arm_timer_clk>; + }; + + timer@60000600 { + compatible = "arm,cortex-a9-twd-timer"; + reg = <0x60000600 0x20>; + interrupts = <1 13 0x304>; + clocks = <&arm_timer_clk>; + }; + + intc: interrupt-controller@60001000 { + compatible = "arm,cortex-a9-gic"; + reg = <0x60001000 0x1000>, + <0x60000100 0x100>; + #interrupt-cells = <3>; + interrupt-controller; + }; + + sysctrl@61840000 { + compatible = "socionext,uniphier-pro4-sysctrl", + "simple-mfd", "syscon"; + reg = <0x61840000 0x10000>; + + sys_clk: clock { + compatible = "socionext,uniphier-pro4-clock"; + #clock-cells = <1>; + }; + + sys_rst: reset { + compatible = "socionext,uniphier-pro4-reset"; + #reset-cells = <1>; + }; + }; + }; }; + +/include/ "uniphier-pinctrl.dtsi" diff --git a/arch/arm/boot/dts/uniphier-pro5.dtsi b/arch/arm/boot/dts/uniphier-pro5.dtsi index 2c49c3614bda..dbc5e5333163 100644 --- a/arch/arm/boot/dts/uniphier-pro5.dtsi +++ b/arch/arm/boot/dts/uniphier-pro5.dtsi @@ -43,7 +43,7 @@ * OTHER DEALINGS IN THE SOFTWARE. */ -/include/ "uniphier-common32.dtsi" +/include/ "skeleton.dtsi" / { compatible = "socionext,uniphier-pro5"; @@ -56,157 +56,355 @@ device_type = "cpu"; compatible = "arm,cortex-a9"; reg = <0>; + clocks = <&sys_clk 32>; enable-method = "psci"; next-level-cache = <&l2>; + operating-points-v2 = <&cpu_opp>; }; cpu@1 { device_type = "cpu"; compatible = "arm,cortex-a9"; reg = <1>; + clocks = <&sys_clk 32>; enable-method = "psci"; next-level-cache = <&l2>; + operating-points-v2 = <&cpu_opp>; }; }; + cpu_opp: opp_table { + compatible = "operating-points-v2"; + opp-shared; + + opp@100000000 { + opp-hz = /bits/ 64 <100000000>; + clock-latency-ns = <300>; + }; + opp@116667000 { + opp-hz = /bits/ 64 <116667000>; + clock-latency-ns = <300>; + }; + opp@150000000 { + opp-hz = /bits/ 64 <150000000>; + clock-latency-ns = <300>; + }; + opp@175000000 { + opp-hz = /bits/ 64 <175000000>; + clock-latency-ns = <300>; + }; + opp@200000000 { + opp-hz = /bits/ 64 <200000000>; + clock-latency-ns = <300>; + }; + opp@233334000 { + opp-hz = /bits/ 64 <233334000>; + clock-latency-ns = <300>; + }; + opp@300000000 { + opp-hz = /bits/ 64 <300000000>; + clock-latency-ns = <300>; + }; + opp@350000000 { + opp-hz = /bits/ 64 <350000000>; + clock-latency-ns = <300>; + }; + opp@400000000 { + opp-hz = /bits/ 64 <400000000>; + clock-latency-ns = <300>; + }; + opp@466667000 { + opp-hz = /bits/ 64 <466667000>; + clock-latency-ns = <300>; + }; + opp@600000000 { + opp-hz = /bits/ 64 <600000000>; + clock-latency-ns = <300>; + }; + opp@700000000 { + opp-hz = /bits/ 64 <700000000>; + clock-latency-ns = <300>; + }; + opp@800000000 { + opp-hz = /bits/ 64 <800000000>; + clock-latency-ns = <300>; + }; + opp@933334000 { + opp-hz = /bits/ 64 <933334000>; + clock-latency-ns = <300>; + }; + opp@1200000000 { + opp-hz = /bits/ 64 <1200000000>; + clock-latency-ns = <300>; + }; + opp@1400000000 { + opp-hz = /bits/ 64 <1400000000>; + clock-latency-ns = <300>; + }; + }; + + psci { + compatible = "arm,psci-0.2"; + method = "smc"; + }; + clocks { + refclk: ref { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <20000000>; + }; + arm_timer_clk: arm_timer_clk { #clock-cells = <0>; compatible = "fixed-clock"; clock-frequency = <50000000>; }; }; -}; -&soc { - l2: l2-cache@500c0000 { - compatible = "socionext,uniphier-system-cache"; - reg = <0x500c0000 0x2000>, <0x503c0100 0x8>, <0x506c0000 0x400>; - interrupts = <0 190 4>, <0 191 4>; - cache-unified; - cache-size = <(2 * 1024 * 1024)>; - cache-sets = <512>; - cache-line-size = <128>; - cache-level = <2>; - next-level-cache = <&l3>; - }; + soc { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + ranges; + interrupt-parent = <&intc>; - l3: l3-cache@500c8000 { - compatible = "socionext,uniphier-system-cache"; - reg = <0x500c8000 0x2000>, <0x503c8100 0x8>, <0x506c8000 0x400>; - interrupts = <0 174 4>, <0 175 4>; - cache-unified; - cache-size = <(2 * 1024 * 1024)>; - cache-sets = <512>; - cache-line-size = <256>; - cache-level = <3>; - }; + l2: l2-cache@500c0000 { + compatible = "socionext,uniphier-system-cache"; + reg = <0x500c0000 0x2000>, <0x503c0100 0x8>, + <0x506c0000 0x400>; + interrupts = <0 190 4>, <0 191 4>; + cache-unified; + cache-size = <(2 * 1024 * 1024)>; + cache-sets = <512>; + cache-line-size = <128>; + cache-level = <2>; + next-level-cache = <&l3>; + }; - i2c0: i2c@58780000 { - compatible = "socionext,uniphier-fi2c"; - status = "disabled"; - reg = <0x58780000 0x80>; - #address-cells = <1>; - #size-cells = <0>; - interrupts = <0 41 4>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c0>; - clocks = <&peri_clk 4>; - clock-frequency = <100000>; - }; + l3: l3-cache@500c8000 { + compatible = "socionext,uniphier-system-cache"; + reg = <0x500c8000 0x2000>, <0x503c8100 0x8>, + <0x506c8000 0x400>; + interrupts = <0 174 4>, <0 175 4>; + cache-unified; + cache-size = <(2 * 1024 * 1024)>; + cache-sets = <512>; + cache-line-size = <256>; + cache-level = <3>; + }; - i2c1: i2c@58781000 { - compatible = "socionext,uniphier-fi2c"; - status = "disabled"; - reg = <0x58781000 0x80>; - #address-cells = <1>; - #size-cells = <0>; - interrupts = <0 42 4>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c1>; - clocks = <&peri_clk 5>; - clock-frequency = <100000>; - }; + serial0: serial@54006800 { + compatible = "socionext,uniphier-uart"; + status = "disabled"; + reg = <0x54006800 0x40>; + interrupts = <0 33 4>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart0>; + clocks = <&peri_clk 0>; + }; - i2c2: i2c@58782000 { - compatible = "socionext,uniphier-fi2c"; - status = "disabled"; - reg = <0x58782000 0x80>; - #address-cells = <1>; - #size-cells = <0>; - interrupts = <0 43 4>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c2>; - clocks = <&peri_clk 6>; - clock-frequency = <100000>; - }; + serial1: serial@54006900 { + compatible = "socionext,uniphier-uart"; + status = "disabled"; + reg = <0x54006900 0x40>; + interrupts = <0 35 4>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart1>; + clocks = <&peri_clk 1>; + }; - i2c3: i2c@58783000 { - compatible = "socionext,uniphier-fi2c"; - status = "disabled"; - reg = <0x58783000 0x80>; - #address-cells = <1>; - #size-cells = <0>; - interrupts = <0 44 4>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c3>; - clocks = <&peri_clk 7>; - clock-frequency = <100000>; - }; + serial2: serial@54006a00 { + compatible = "socionext,uniphier-uart"; + status = "disabled"; + reg = <0x54006a00 0x40>; + interrupts = <0 37 4>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart2>; + clocks = <&peri_clk 2>; + }; - /* i2c4 does not exist */ + serial3: serial@54006b00 { + compatible = "socionext,uniphier-uart"; + status = "disabled"; + reg = <0x54006b00 0x40>; + interrupts = <0 177 4>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart3>; + clocks = <&peri_clk 3>; + }; - /* chip-internal connection for DMD */ - i2c5: i2c@58785000 { - compatible = "socionext,uniphier-fi2c"; - reg = <0x58785000 0x80>; - #address-cells = <1>; - #size-cells = <0>; - interrupts = <0 25 4>; - clocks = <&peri_clk 9>; - clock-frequency = <400000>; - }; + i2c0: i2c@58780000 { + compatible = "socionext,uniphier-fi2c"; + status = "disabled"; + reg = <0x58780000 0x80>; + #address-cells = <1>; + #size-cells = <0>; + interrupts = <0 41 4>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c0>; + clocks = <&peri_clk 4>; + clock-frequency = <100000>; + }; - /* chip-internal connection for HDMI */ - i2c6: i2c@58786000 { - compatible = "socionext,uniphier-fi2c"; - reg = <0x58786000 0x80>; - #address-cells = <1>; - #size-cells = <0>; - interrupts = <0 26 4>; - clocks = <&peri_clk 10>; - clock-frequency = <400000>; - }; -}; + i2c1: i2c@58781000 { + compatible = "socionext,uniphier-fi2c"; + status = "disabled"; + reg = <0x58781000 0x80>; + #address-cells = <1>; + #size-cells = <0>; + interrupts = <0 42 4>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c1>; + clocks = <&peri_clk 5>; + clock-frequency = <100000>; + }; -&refclk { - clock-frequency = <20000000>; -}; + i2c2: i2c@58782000 { + compatible = "socionext,uniphier-fi2c"; + status = "disabled"; + reg = <0x58782000 0x80>; + #address-cells = <1>; + #size-cells = <0>; + interrupts = <0 43 4>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c2>; + clocks = <&peri_clk 6>; + clock-frequency = <100000>; + }; -&mio_clk { - compatible = "socionext,uniphier-pro5-mio-clock"; -}; + i2c3: i2c@58783000 { + compatible = "socionext,uniphier-fi2c"; + status = "disabled"; + reg = <0x58783000 0x80>; + #address-cells = <1>; + #size-cells = <0>; + interrupts = <0 44 4>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c3>; + clocks = <&peri_clk 7>; + clock-frequency = <100000>; + }; -&mio_rst { - compatible = "socionext,uniphier-pro5-mio-reset"; -}; + /* i2c4 does not exist */ -&peri_clk { - compatible = "socionext,uniphier-pro5-peri-clock"; -}; + /* chip-internal connection for DMD */ + i2c5: i2c@58785000 { + compatible = "socionext,uniphier-fi2c"; + reg = <0x58785000 0x80>; + #address-cells = <1>; + #size-cells = <0>; + interrupts = <0 25 4>; + clocks = <&peri_clk 9>; + clock-frequency = <400000>; + }; -&peri_rst { - compatible = "socionext,uniphier-pro5-peri-reset"; -}; + /* chip-internal connection for HDMI */ + i2c6: i2c@58786000 { + compatible = "socionext,uniphier-fi2c"; + reg = <0x58786000 0x80>; + #address-cells = <1>; + #size-cells = <0>; + interrupts = <0 26 4>; + clocks = <&peri_clk 10>; + clock-frequency = <400000>; + }; -&pinctrl { - compatible = "socionext,uniphier-pro5-pinctrl"; -}; + system_bus: system-bus@58c00000 { + compatible = "socionext,uniphier-system-bus"; + status = "disabled"; + reg = <0x58c00000 0x400>; + #address-cells = <2>; + #size-cells = <1>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_system_bus>; + }; -&sys_clk { - compatible = "socionext,uniphier-pro5-clock"; -}; + smpctrl@59800000 { + compatible = "socionext,uniphier-smpctrl"; + reg = <0x59801000 0x400>; + }; -&sys_rst { - compatible = "socionext,uniphier-pro5-reset"; + sdctrl@59810000 { + compatible = "socionext,uniphier-pro5-sdctrl", + "simple-mfd", "syscon"; + reg = <0x59810000 0x800>; + + sd_clk: clock { + compatible = "socionext,uniphier-pro5-sd-clock"; + #clock-cells = <1>; + }; + + sd_rst: reset { + compatible = "socionext,uniphier-pro5-sd-reset"; + #reset-cells = <1>; + }; + }; + + perictrl@59820000 { + compatible = "socionext,uniphier-pro5-perictrl", + "simple-mfd", "syscon"; + reg = <0x59820000 0x200>; + + peri_clk: clock { + compatible = "socionext,uniphier-pro5-peri-clock"; + #clock-cells = <1>; + }; + + peri_rst: reset { + compatible = "socionext,uniphier-pro5-peri-reset"; + #reset-cells = <1>; + }; + }; + + soc-glue@5f800000 { + compatible = "socionext,uniphier-pro5-soc-glue", + "simple-mfd", "syscon"; + reg = <0x5f800000 0x2000>; + + pinctrl: pinctrl { + compatible = "socionext,uniphier-pro5-pinctrl"; + }; + }; + + timer@60000200 { + compatible = "arm,cortex-a9-global-timer"; + reg = <0x60000200 0x20>; + interrupts = <1 11 0x304>; + clocks = <&arm_timer_clk>; + }; + + timer@60000600 { + compatible = "arm,cortex-a9-twd-timer"; + reg = <0x60000600 0x20>; + interrupts = <1 13 0x304>; + clocks = <&arm_timer_clk>; + }; + + intc: interrupt-controller@60001000 { + compatible = "arm,cortex-a9-gic"; + reg = <0x60001000 0x1000>, + <0x60000100 0x100>; + #interrupt-cells = <3>; + interrupt-controller; + }; + + sysctrl@61840000 { + compatible = "socionext,uniphier-pro5-sysctrl", + "simple-mfd", "syscon"; + reg = <0x61840000 0x10000>; + + sys_clk: clock { + compatible = "socionext,uniphier-pro5-clock"; + #clock-cells = <1>; + }; + + sys_rst: reset { + compatible = "socionext,uniphier-pro5-reset"; + #reset-cells = <1>; + }; + }; + }; }; + +/include/ "uniphier-pinctrl.dtsi" diff --git a/arch/arm/boot/dts/uniphier-pxs2.dtsi b/arch/arm/boot/dts/uniphier-pxs2.dtsi index 8789cd518933..e9e031d63c1a 100644 --- a/arch/arm/boot/dts/uniphier-pxs2.dtsi +++ b/arch/arm/boot/dts/uniphier-pxs2.dtsi @@ -43,7 +43,7 @@ * OTHER DEALINGS IN THE SOFTWARE. */ -/include/ "uniphier-common32.dtsi" +/include/ "skeleton.dtsi" / { compatible = "socionext,uniphier-pxs2"; @@ -56,170 +56,339 @@ device_type = "cpu"; compatible = "arm,cortex-a9"; reg = <0>; + clocks = <&sys_clk 32>; enable-method = "psci"; next-level-cache = <&l2>; + operating-points-v2 = <&cpu_opp>; }; cpu@1 { device_type = "cpu"; compatible = "arm,cortex-a9"; reg = <1>; + clocks = <&sys_clk 32>; enable-method = "psci"; next-level-cache = <&l2>; + operating-points-v2 = <&cpu_opp>; }; cpu@2 { device_type = "cpu"; compatible = "arm,cortex-a9"; reg = <2>; + clocks = <&sys_clk 32>; enable-method = "psci"; next-level-cache = <&l2>; + operating-points-v2 = <&cpu_opp>; }; cpu@3 { device_type = "cpu"; compatible = "arm,cortex-a9"; reg = <3>; + clocks = <&sys_clk 32>; enable-method = "psci"; next-level-cache = <&l2>; + operating-points-v2 = <&cpu_opp>; }; }; + cpu_opp: opp_table { + compatible = "operating-points-v2"; + opp-shared; + + opp@100000000 { + opp-hz = /bits/ 64 <100000000>; + clock-latency-ns = <300>; + }; + opp@150000000 { + opp-hz = /bits/ 64 <150000000>; + clock-latency-ns = <300>; + }; + opp@200000000 { + opp-hz = /bits/ 64 <200000000>; + clock-latency-ns = <300>; + }; + opp@300000000 { + opp-hz = /bits/ 64 <300000000>; + clock-latency-ns = <300>; + }; + opp@400000000 { + opp-hz = /bits/ 64 <400000000>; + clock-latency-ns = <300>; + }; + opp@600000000 { + opp-hz = /bits/ 64 <600000000>; + clock-latency-ns = <300>; + }; + opp@800000000 { + opp-hz = /bits/ 64 <800000000>; + clock-latency-ns = <300>; + }; + opp@1200000000 { + opp-hz = /bits/ 64 <1200000000>; + clock-latency-ns = <300>; + }; + }; + + psci { + compatible = "arm,psci-0.2"; + method = "smc"; + }; + clocks { + refclk: ref { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <25000000>; + }; + arm_timer_clk: arm_timer_clk { #clock-cells = <0>; compatible = "fixed-clock"; clock-frequency = <50000000>; }; }; -}; - -&soc { - l2: l2-cache@500c0000 { - compatible = "socionext,uniphier-system-cache"; - reg = <0x500c0000 0x2000>, <0x503c0100 0x4>, <0x506c0000 0x400>; - interrupts = <0 174 4>, <0 175 4>, <0 190 4>, <0 191 4>; - cache-unified; - cache-size = <(1280 * 1024)>; - cache-sets = <512>; - cache-line-size = <128>; - cache-level = <2>; - }; - i2c0: i2c@58780000 { - compatible = "socionext,uniphier-fi2c"; - status = "disabled"; - reg = <0x58780000 0x80>; + soc { + compatible = "simple-bus"; #address-cells = <1>; - #size-cells = <0>; - interrupts = <0 41 4>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c0>; - clocks = <&peri_clk 4>; - clock-frequency = <100000>; - }; + #size-cells = <1>; + ranges; + interrupt-parent = <&intc>; - i2c1: i2c@58781000 { - compatible = "socionext,uniphier-fi2c"; - status = "disabled"; - reg = <0x58781000 0x80>; - #address-cells = <1>; - #size-cells = <0>; - interrupts = <0 42 4>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c1>; - clocks = <&peri_clk 5>; - clock-frequency = <100000>; - }; + l2: l2-cache@500c0000 { + compatible = "socionext,uniphier-system-cache"; + reg = <0x500c0000 0x2000>, <0x503c0100 0x8>, + <0x506c0000 0x400>; + interrupts = <0 174 4>, <0 175 4>, <0 190 4>, <0 191 4>; + cache-unified; + cache-size = <(1280 * 1024)>; + cache-sets = <512>; + cache-line-size = <128>; + cache-level = <2>; + }; - i2c2: i2c@58782000 { - compatible = "socionext,uniphier-fi2c"; - status = "disabled"; - reg = <0x58782000 0x80>; - #address-cells = <1>; - #size-cells = <0>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c2>; - interrupts = <0 43 4>; - clocks = <&peri_clk 6>; - clock-frequency = <100000>; - }; + serial0: serial@54006800 { + compatible = "socionext,uniphier-uart"; + status = "disabled"; + reg = <0x54006800 0x40>; + interrupts = <0 33 4>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart0>; + clocks = <&peri_clk 0>; + }; - i2c3: i2c@58783000 { - compatible = "socionext,uniphier-fi2c"; - status = "disabled"; - reg = <0x58783000 0x80>; - #address-cells = <1>; - #size-cells = <0>; - interrupts = <0 44 4>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c3>; - clocks = <&peri_clk 7>; - clock-frequency = <100000>; - }; + serial1: serial@54006900 { + compatible = "socionext,uniphier-uart"; + status = "disabled"; + reg = <0x54006900 0x40>; + interrupts = <0 35 4>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart1>; + clocks = <&peri_clk 1>; + }; - /* chip-internal connection for DMD */ - i2c4: i2c@58784000 { - compatible = "socionext,uniphier-fi2c"; - reg = <0x58784000 0x80>; - #address-cells = <1>; - #size-cells = <0>; - interrupts = <0 45 4>; - clocks = <&peri_clk 8>; - clock-frequency = <400000>; - }; + serial2: serial@54006a00 { + compatible = "socionext,uniphier-uart"; + status = "disabled"; + reg = <0x54006a00 0x40>; + interrupts = <0 37 4>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart2>; + clocks = <&peri_clk 2>; + }; - /* chip-internal connection for STM */ - i2c5: i2c@58785000 { - compatible = "socionext,uniphier-fi2c"; - reg = <0x58785000 0x80>; - #address-cells = <1>; - #size-cells = <0>; - interrupts = <0 25 4>; - clocks = <&peri_clk 9>; - clock-frequency = <400000>; - }; + serial3: serial@54006b00 { + compatible = "socionext,uniphier-uart"; + status = "disabled"; + reg = <0x54006b00 0x40>; + interrupts = <0 177 4>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart3>; + clocks = <&peri_clk 3>; + }; - /* chip-internal connection for HDMI */ - i2c6: i2c@58786000 { - compatible = "socionext,uniphier-fi2c"; - reg = <0x58786000 0x80>; - #address-cells = <1>; - #size-cells = <0>; - interrupts = <0 26 4>; - clocks = <&peri_clk 10>; - clock-frequency = <400000>; - }; -}; + i2c0: i2c@58780000 { + compatible = "socionext,uniphier-fi2c"; + status = "disabled"; + reg = <0x58780000 0x80>; + #address-cells = <1>; + #size-cells = <0>; + interrupts = <0 41 4>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c0>; + clocks = <&peri_clk 4>; + clock-frequency = <100000>; + }; -&refclk { - clock-frequency = <25000000>; -}; + i2c1: i2c@58781000 { + compatible = "socionext,uniphier-fi2c"; + status = "disabled"; + reg = <0x58781000 0x80>; + #address-cells = <1>; + #size-cells = <0>; + interrupts = <0 42 4>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c1>; + clocks = <&peri_clk 5>; + clock-frequency = <100000>; + }; -&mio_clk { - compatible = "socionext,uniphier-pxs2-mio-clock"; -}; + i2c2: i2c@58782000 { + compatible = "socionext,uniphier-fi2c"; + status = "disabled"; + reg = <0x58782000 0x80>; + #address-cells = <1>; + #size-cells = <0>; + interrupts = <0 43 4>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c2>; + clocks = <&peri_clk 6>; + clock-frequency = <100000>; + }; -&mio_rst { - compatible = "socionext,uniphier-pxs2-mio-reset"; -}; + i2c3: i2c@58783000 { + compatible = "socionext,uniphier-fi2c"; + status = "disabled"; + reg = <0x58783000 0x80>; + #address-cells = <1>; + #size-cells = <0>; + interrupts = <0 44 4>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c3>; + clocks = <&peri_clk 7>; + clock-frequency = <100000>; + }; -&peri_clk { - compatible = "socionext,uniphier-pxs2-peri-clock"; -}; + /* chip-internal connection for DMD */ + i2c4: i2c@58784000 { + compatible = "socionext,uniphier-fi2c"; + reg = <0x58784000 0x80>; + #address-cells = <1>; + #size-cells = <0>; + interrupts = <0 45 4>; + clocks = <&peri_clk 8>; + clock-frequency = <400000>; + }; -&peri_rst { - compatible = "socionext,uniphier-pxs2-peri-reset"; -}; + /* chip-internal connection for STM */ + i2c5: i2c@58785000 { + compatible = "socionext,uniphier-fi2c"; + reg = <0x58785000 0x80>; + #address-cells = <1>; + #size-cells = <0>; + interrupts = <0 25 4>; + clocks = <&peri_clk 9>; + clock-frequency = <400000>; + }; -&pinctrl { - compatible = "socionext,uniphier-pxs2-pinctrl"; -}; + /* chip-internal connection for HDMI */ + i2c6: i2c@58786000 { + compatible = "socionext,uniphier-fi2c"; + reg = <0x58786000 0x80>; + #address-cells = <1>; + #size-cells = <0>; + interrupts = <0 26 4>; + clocks = <&peri_clk 10>; + clock-frequency = <400000>; + }; -&sys_clk { - compatible = "socionext,uniphier-pxs2-clock"; -}; + system_bus: system-bus@58c00000 { + compatible = "socionext,uniphier-system-bus"; + status = "disabled"; + reg = <0x58c00000 0x400>; + #address-cells = <2>; + #size-cells = <1>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_system_bus>; + }; + + smpctrl@59800000 { + compatible = "socionext,uniphier-smpctrl"; + reg = <0x59801000 0x400>; + }; + + sdctrl@59810000 { + compatible = "socionext,uniphier-pxs2-sdctrl", + "simple-mfd", "syscon"; + reg = <0x59810000 0x800>; -&sys_rst { - compatible = "socionext,uniphier-pxs2-reset"; + sd_clk: clock { + compatible = "socionext,uniphier-pxs2-sd-clock"; + #clock-cells = <1>; + }; + + sd_rst: reset { + compatible = "socionext,uniphier-pxs2-sd-reset"; + #reset-cells = <1>; + }; + }; + + perictrl@59820000 { + compatible = "socionext,uniphier-pxs2-perictrl", + "simple-mfd", "syscon"; + reg = <0x59820000 0x200>; + + peri_clk: clock { + compatible = "socionext,uniphier-pxs2-peri-clock"; + #clock-cells = <1>; + }; + + peri_rst: reset { + compatible = "socionext,uniphier-pxs2-peri-reset"; + #reset-cells = <1>; + }; + }; + + soc-glue@5f800000 { + compatible = "socionext,uniphier-pxs2-soc-glue", + "simple-mfd", "syscon"; + reg = <0x5f800000 0x2000>; + + pinctrl: pinctrl { + compatible = "socionext,uniphier-pxs2-pinctrl"; + }; + }; + + timer@60000200 { + compatible = "arm,cortex-a9-global-timer"; + reg = <0x60000200 0x20>; + interrupts = <1 11 0xf04>; + clocks = <&arm_timer_clk>; + }; + + timer@60000600 { + compatible = "arm,cortex-a9-twd-timer"; + reg = <0x60000600 0x20>; + interrupts = <1 13 0xf04>; + clocks = <&arm_timer_clk>; + }; + + intc: interrupt-controller@60001000 { + compatible = "arm,cortex-a9-gic"; + reg = <0x60001000 0x1000>, + <0x60000100 0x100>; + #interrupt-cells = <3>; + interrupt-controller; + }; + + sysctrl@61840000 { + compatible = "socionext,uniphier-pxs2-sysctrl", + "simple-mfd", "syscon"; + reg = <0x61840000 0x10000>; + + sys_clk: clock { + compatible = "socionext,uniphier-pxs2-clock"; + #clock-cells = <1>; + }; + + sys_rst: reset { + compatible = "socionext,uniphier-pxs2-reset"; + #reset-cells = <1>; + }; + }; + }; }; + +/include/ "uniphier-pinctrl.dtsi" diff --git a/arch/arm/boot/dts/uniphier-sld3.dtsi b/arch/arm/boot/dts/uniphier-sld3.dtsi index 5fa96c939b5c..9fad6bd2db8a 100644 --- a/arch/arm/boot/dts/uniphier-sld3.dtsi +++ b/arch/arm/boot/dts/uniphier-sld3.dtsi @@ -135,7 +135,6 @@ reg = <0x54006800 0x40>; interrupts = <0 33 4>; clocks = <&sys_clk 0>; - fifo-size = <64>; }; serial1: serial@54006900 { @@ -144,7 +143,6 @@ reg = <0x54006900 0x40>; interrupts = <0 35 4>; clocks = <&sys_clk 0>; - fifo-size = <64>; }; serial2: serial@54006a00 { @@ -153,7 +151,6 @@ reg = <0x54006a00 0x40>; interrupts = <0 37 4>; clocks = <&sys_clk 0>; - fifo-size = <64>; }; i2c0: i2c@58400000 { @@ -225,7 +222,7 @@ }; mioctrl@59810000 { - compatible = "socionext,uniphier-mioctrl", + compatible = "socionext,uniphier-sld3-mioctrl", "simple-mfd", "syscon"; reg = <0x59810000 0x800>; @@ -245,6 +242,9 @@ status = "disabled"; reg = <0x5a800100 0x100>; interrupts = <0 80 4>; + clocks = <&mio_clk 7>, <&mio_clk 8>, <&mio_clk 12>; + resets = <&sys_rst 8>, <&mio_rst 7>, <&mio_rst 8>, + <&mio_rst 12>; }; usb1: usb@5a810100 { @@ -252,6 +252,9 @@ status = "disabled"; reg = <0x5a810100 0x100>; interrupts = <0 81 4>; + clocks = <&mio_clk 7>, <&mio_clk 9>, <&mio_clk 13>; + resets = <&sys_rst 8>, <&mio_rst 7>, <&mio_rst 9>, + <&mio_rst 13>; }; usb2: usb@5a820100 { @@ -259,6 +262,9 @@ status = "disabled"; reg = <0x5a820100 0x100>; interrupts = <0 82 4>; + clocks = <&mio_clk 7>, <&mio_clk 10>, <&mio_clk 14>; + resets = <&sys_rst 8>, <&mio_rst 7>, <&mio_rst 10>, + <&mio_rst 14>; }; usb3: usb@5a830100 { @@ -266,12 +272,15 @@ status = "disabled"; reg = <0x5a830100 0x100>; interrupts = <0 83 4>; + clocks = <&mio_clk 7>, <&mio_clk 11>, <&mio_clk 15>; + resets = <&sys_rst 8>, <&mio_rst 7>, <&mio_rst 11>, + <&mio_rst 15>; }; sysctrl@f1840000 { - compatible = "socionext,uniphier-sysctrl", + compatible = "socionext,uniphier-sld3-sysctrl", "simple-mfd", "syscon"; - reg = <0xf1840000 0x4000>; + reg = <0xf1840000 0x10000>; sys_clk: clock { compatible = "socionext,uniphier-sld3-clock"; diff --git a/arch/arm/boot/dts/uniphier-sld8.dtsi b/arch/arm/boot/dts/uniphier-sld8.dtsi index d8cf0e7e11ea..b2c980ead7f0 100644 --- a/arch/arm/boot/dts/uniphier-sld8.dtsi +++ b/arch/arm/boot/dts/uniphier-sld8.dtsi @@ -43,7 +43,7 @@ * OTHER DEALINGS IN THE SOFTWARE. */ -/include/ "uniphier-common32.dtsi" +/include/ "skeleton.dtsi" / { compatible = "socionext,uniphier-sld8"; @@ -61,146 +61,267 @@ }; }; + psci { + compatible = "arm,psci-0.2"; + method = "smc"; + }; + clocks { + refclk: ref { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <25000000>; + }; + arm_timer_clk: arm_timer_clk { #clock-cells = <0>; compatible = "fixed-clock"; clock-frequency = <50000000>; }; }; -}; - -&soc { - l2: l2-cache@500c0000 { - compatible = "socionext,uniphier-system-cache"; - reg = <0x500c0000 0x2000>, <0x503c0100 0x4>, <0x506c0000 0x400>; - interrupts = <0 174 4>, <0 175 4>; - cache-unified; - cache-size = <(256 * 1024)>; - cache-sets = <256>; - cache-line-size = <128>; - cache-level = <2>; - }; - i2c0: i2c@58400000 { - compatible = "socionext,uniphier-i2c"; - status = "disabled"; - reg = <0x58400000 0x40>; + soc { + compatible = "simple-bus"; #address-cells = <1>; - #size-cells = <0>; - interrupts = <0 41 1>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c0>; - clocks = <&peri_clk 4>; - clock-frequency = <100000>; - }; + #size-cells = <1>; + ranges; + interrupt-parent = <&intc>; - i2c1: i2c@58480000 { - compatible = "socionext,uniphier-i2c"; - status = "disabled"; - reg = <0x58480000 0x40>; - #address-cells = <1>; - #size-cells = <0>; - interrupts = <0 42 1>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c1>; - clocks = <&peri_clk 5>; - clock-frequency = <100000>; - }; + l2: l2-cache@500c0000 { + compatible = "socionext,uniphier-system-cache"; + reg = <0x500c0000 0x2000>, <0x503c0100 0x4>, + <0x506c0000 0x400>; + interrupts = <0 174 4>, <0 175 4>; + cache-unified; + cache-size = <(256 * 1024)>; + cache-sets = <256>; + cache-line-size = <128>; + cache-level = <2>; + }; - /* chip-internal connection for DMD */ - i2c2: i2c@58500000 { - compatible = "socionext,uniphier-i2c"; - reg = <0x58500000 0x40>; - #address-cells = <1>; - #size-cells = <0>; - interrupts = <0 43 1>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c2>; - clocks = <&peri_clk 6>; - clock-frequency = <400000>; - }; + serial0: serial@54006800 { + compatible = "socionext,uniphier-uart"; + status = "disabled"; + reg = <0x54006800 0x40>; + interrupts = <0 33 4>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart0>; + clocks = <&peri_clk 0>; + }; - i2c3: i2c@58580000 { - compatible = "socionext,uniphier-i2c"; - status = "disabled"; - reg = <0x58580000 0x40>; - #address-cells = <1>; - #size-cells = <0>; - interrupts = <0 44 1>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c3>; - clocks = <&peri_clk 7>; - clock-frequency = <100000>; - }; + serial1: serial@54006900 { + compatible = "socionext,uniphier-uart"; + status = "disabled"; + reg = <0x54006900 0x40>; + interrupts = <0 35 4>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart1>; + clocks = <&peri_clk 1>; + }; - usb0: usb@5a800100 { - compatible = "socionext,uniphier-ehci", "generic-ehci"; - status = "disabled"; - reg = <0x5a800100 0x100>; - interrupts = <0 80 4>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usb0>; - clocks = <&mio_clk 7>, <&mio_clk 8>, <&mio_clk 12>; - resets = <&mio_rst 7>, <&mio_rst 8>, <&mio_rst 12>, <&sys_rst 8>; - }; + serial2: serial@54006a00 { + compatible = "socionext,uniphier-uart"; + status = "disabled"; + reg = <0x54006a00 0x40>; + interrupts = <0 37 4>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart2>; + clocks = <&peri_clk 2>; + }; - usb1: usb@5a810100 { - compatible = "socionext,uniphier-ehci", "generic-ehci"; - status = "disabled"; - reg = <0x5a810100 0x100>; - interrupts = <0 81 4>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usb1>; - clocks = <&mio_clk 7>, <&mio_clk 9>, <&mio_clk 13>; - resets = <&mio_rst 7>, <&mio_rst 9>, <&mio_rst 13>, <&sys_rst 8>; - }; + serial3: serial@54006b00 { + compatible = "socionext,uniphier-uart"; + status = "disabled"; + reg = <0x54006b00 0x40>; + interrupts = <0 29 4>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart3>; + clocks = <&peri_clk 3>; + }; - usb2: usb@5a820100 { - compatible = "socionext,uniphier-ehci", "generic-ehci"; - status = "disabled"; - reg = <0x5a820100 0x100>; - interrupts = <0 82 4>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usb2>; - clocks = <&mio_clk 7>, <&mio_clk 10>, <&mio_clk 14>; - resets = <&mio_rst 7>, <&mio_rst 10>, <&mio_rst 14>, <&sys_rst 8>; - }; -}; + i2c0: i2c@58400000 { + compatible = "socionext,uniphier-i2c"; + status = "disabled"; + reg = <0x58400000 0x40>; + #address-cells = <1>; + #size-cells = <0>; + interrupts = <0 41 1>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c0>; + clocks = <&peri_clk 4>; + clock-frequency = <100000>; + }; -&refclk { - clock-frequency = <25000000>; -}; + i2c1: i2c@58480000 { + compatible = "socionext,uniphier-i2c"; + status = "disabled"; + reg = <0x58480000 0x40>; + #address-cells = <1>; + #size-cells = <0>; + interrupts = <0 42 1>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c1>; + clocks = <&peri_clk 5>; + clock-frequency = <100000>; + }; -&serial3 { - interrupts = <0 29 4>; -}; + /* chip-internal connection for DMD */ + i2c2: i2c@58500000 { + compatible = "socionext,uniphier-i2c"; + reg = <0x58500000 0x40>; + #address-cells = <1>; + #size-cells = <0>; + interrupts = <0 43 1>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c2>; + clocks = <&peri_clk 6>; + clock-frequency = <400000>; + }; -&mio_clk { - compatible = "socionext,uniphier-sld8-mio-clock"; -}; + i2c3: i2c@58580000 { + compatible = "socionext,uniphier-i2c"; + status = "disabled"; + reg = <0x58580000 0x40>; + #address-cells = <1>; + #size-cells = <0>; + interrupts = <0 44 1>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c3>; + clocks = <&peri_clk 7>; + clock-frequency = <100000>; + }; -&mio_rst { - compatible = "socionext,uniphier-sld8-mio-reset"; - resets = <&sys_rst 7>; -}; + system_bus: system-bus@58c00000 { + compatible = "socionext,uniphier-system-bus"; + status = "disabled"; + reg = <0x58c00000 0x400>; + #address-cells = <2>; + #size-cells = <1>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_system_bus>; + }; -&peri_clk { - compatible = "socionext,uniphier-sld8-peri-clock"; -}; + smpctrl@59800000 { + compatible = "socionext,uniphier-smpctrl"; + reg = <0x59801000 0x400>; + }; -&peri_rst { - compatible = "socionext,uniphier-sld8-peri-reset"; -}; + mioctrl@59810000 { + compatible = "socionext,uniphier-sld8-mioctrl", + "simple-mfd", "syscon"; + reg = <0x59810000 0x800>; -&pinctrl { - compatible = "socionext,uniphier-sld8-pinctrl"; -}; + mio_clk: clock { + compatible = "socionext,uniphier-sld8-mio-clock"; + #clock-cells = <1>; + }; -&sys_clk { - compatible = "socionext,uniphier-sld8-clock"; -}; + mio_rst: reset { + compatible = "socionext,uniphier-sld8-mio-reset"; + #reset-cells = <1>; + }; + }; + + perictrl@59820000 { + compatible = "socionext,uniphier-sld8-perictrl", + "simple-mfd", "syscon"; + reg = <0x59820000 0x200>; + + peri_clk: clock { + compatible = "socionext,uniphier-sld8-peri-clock"; + #clock-cells = <1>; + }; + + peri_rst: reset { + compatible = "socionext,uniphier-sld8-peri-reset"; + #reset-cells = <1>; + }; + }; + + usb0: usb@5a800100 { + compatible = "socionext,uniphier-ehci", "generic-ehci"; + status = "disabled"; + reg = <0x5a800100 0x100>; + interrupts = <0 80 4>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usb0>; + clocks = <&mio_clk 7>, <&mio_clk 8>, <&mio_clk 12>; + resets = <&sys_rst 8>, <&mio_rst 7>, <&mio_rst 8>, + <&mio_rst 12>; + }; + + usb1: usb@5a810100 { + compatible = "socionext,uniphier-ehci", "generic-ehci"; + status = "disabled"; + reg = <0x5a810100 0x100>; + interrupts = <0 81 4>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usb1>; + clocks = <&mio_clk 7>, <&mio_clk 9>, <&mio_clk 13>; + resets = <&sys_rst 8>, <&mio_rst 7>, <&mio_rst 9>, + <&mio_rst 13>; + }; + + usb2: usb@5a820100 { + compatible = "socionext,uniphier-ehci", "generic-ehci"; + status = "disabled"; + reg = <0x5a820100 0x100>; + interrupts = <0 82 4>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usb2>; + clocks = <&mio_clk 7>, <&mio_clk 10>, <&mio_clk 14>; + resets = <&sys_rst 8>, <&mio_rst 7>, <&mio_rst 10>, + <&mio_rst 14>; + }; -&sys_rst { - compatible = "socionext,uniphier-sld8-reset"; + soc-glue@5f800000 { + compatible = "socionext,uniphier-sld8-soc-glue", + "simple-mfd", "syscon"; + reg = <0x5f800000 0x2000>; + + pinctrl: pinctrl { + compatible = "socionext,uniphier-sld8-pinctrl"; + }; + }; + + timer@60000200 { + compatible = "arm,cortex-a9-global-timer"; + reg = <0x60000200 0x20>; + interrupts = <1 11 0x104>; + clocks = <&arm_timer_clk>; + }; + + timer@60000600 { + compatible = "arm,cortex-a9-twd-timer"; + reg = <0x60000600 0x20>; + interrupts = <1 13 0x104>; + clocks = <&arm_timer_clk>; + }; + + intc: interrupt-controller@60001000 { + compatible = "arm,cortex-a9-gic"; + reg = <0x60001000 0x1000>, + <0x60000100 0x100>; + #interrupt-cells = <3>; + interrupt-controller; + }; + + sysctrl@61840000 { + compatible = "socionext,uniphier-sld8-sysctrl", + "simple-mfd", "syscon"; + reg = <0x61840000 0x10000>; + + sys_clk: clock { + compatible = "socionext,uniphier-sld8-clock"; + #clock-cells = <1>; + }; + + sys_rst: reset { + compatible = "socionext,uniphier-sld8-reset"; + #reset-cells = <1>; + }; + }; + }; }; + +/include/ "uniphier-pinctrl.dtsi" diff --git a/arch/arm/boot/dts/vexpress-v2p-ca15_a7.dts b/arch/arm/boot/dts/vexpress-v2p-ca15_a7.dts index 0205c97efdef..45d08cc37b01 100644 --- a/arch/arm/boot/dts/vexpress-v2p-ca15_a7.dts +++ b/arch/arm/boot/dts/vexpress-v2p-ca15_a7.dts @@ -39,6 +39,7 @@ reg = <0>; cci-control-port = <&cci_control1>; cpu-idle-states = <&CLUSTER_SLEEP_BIG>; + capacity-dmips-mhz = <1024>; }; cpu1: cpu@1 { @@ -47,6 +48,7 @@ reg = <1>; cci-control-port = <&cci_control1>; cpu-idle-states = <&CLUSTER_SLEEP_BIG>; + capacity-dmips-mhz = <1024>; }; cpu2: cpu@2 { @@ -55,6 +57,7 @@ reg = <0x100>; cci-control-port = <&cci_control2>; cpu-idle-states = <&CLUSTER_SLEEP_LITTLE>; + capacity-dmips-mhz = <516>; }; cpu3: cpu@3 { @@ -63,6 +66,7 @@ reg = <0x101>; cci-control-port = <&cci_control2>; cpu-idle-states = <&CLUSTER_SLEEP_LITTLE>; + capacity-dmips-mhz = <516>; }; cpu4: cpu@4 { @@ -71,6 +75,7 @@ reg = <0x102>; cci-control-port = <&cci_control2>; cpu-idle-states = <&CLUSTER_SLEEP_LITTLE>; + capacity-dmips-mhz = <516>; }; idle-states { diff --git a/arch/arm/boot/dts/vf-colibri.dtsi b/arch/arm/boot/dts/vf-colibri.dtsi index b7417094dc11..21bfef957b68 100644 --- a/arch/arm/boot/dts/vf-colibri.dtsi +++ b/arch/arm/boot/dts/vf-colibri.dtsi @@ -108,6 +108,10 @@ status = "okay"; }; +&edma1 { + status = "okay"; +}; + &esdhc1 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_esdhc1>; diff --git a/arch/arm/boot/dts/vf500.dtsi b/arch/arm/boot/dts/vf500.dtsi index a3824e61bd72..d7fdb2a7d97b 100644 --- a/arch/arm/boot/dts/vf500.dtsi +++ b/arch/arm/boot/dts/vf500.dtsi @@ -70,7 +70,7 @@ global_timer: timer@40002200 { compatible = "arm,cortex-a9-global-timer"; reg = <0x40002200 0x20>; - interrupts = <GIC_PPI 11 IRQ_TYPE_LEVEL_HIGH>; + interrupts = <GIC_PPI 11 IRQ_TYPE_EDGE_RISING>; interrupt-parent = <&intc>; clocks = <&clks VF610_CLK_PLATFORM_BUS>; }; diff --git a/arch/arm/boot/dts/vf610-zii-dev-rev-b.dts b/arch/arm/boot/dts/vf610-zii-dev-rev-b.dts index 5c1fcab4a6f7..fa19cfdc33fb 100644 --- a/arch/arm/boot/dts/vf610-zii-dev-rev-b.dts +++ b/arch/arm/boot/dts/vf610-zii-dev-rev-b.dts @@ -499,13 +499,6 @@ }; }; -&i2c3 { - clock-frequency = <100000>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c3>; - status = "okay"; -}; - &uart0 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_uart0>; @@ -663,13 +656,6 @@ >; }; - pinctrl_i2c3: i2c3grp { - fsl,pins = < - VF610_PAD_PTA30__I2C3_SCL 0x37ff - VF610_PAD_PTA31__I2C3_SDA 0x37ff - >; - }; - pinctrl_leds_debug: pinctrl-leds-debug { fsl,pins = < VF610_PAD_PTD20__GPIO_74 0x31c2 diff --git a/arch/arm/boot/dts/vfxxx.dtsi b/arch/arm/boot/dts/vfxxx.dtsi index 2c13ec696ac5..e9d28474c26a 100644 --- a/arch/arm/boot/dts/vfxxx.dtsi +++ b/arch/arm/boot/dts/vfxxx.dtsi @@ -194,6 +194,9 @@ clocks = <&clks VF610_CLK_DSPI0>; clock-names = "dspi"; spi-num-chipselects = <6>; + dmas = <&edma1 1 12>, + <&edma1 1 13>; + dma-names = "rx", "tx"; status = "disabled"; }; @@ -206,6 +209,9 @@ clocks = <&clks VF610_CLK_DSPI1>; clock-names = "dspi"; spi-num-chipselects = <4>; + dmas = <&edma1 1 14>, + <&edma1 1 15>; + dma-names = "rx", "tx"; status = "disabled"; }; @@ -520,6 +526,12 @@ status = "disabled"; }; + ocotp: ocotp@400a5000 { + compatible = "fsl,vf610-ocotp"; + reg = <0x400a5000 0x1000>; + clocks = <&clks VF610_CLK_OCOTP>; + }; + snvs0: snvs@400a7000 { compatible = "fsl,sec-v4.0-mon", "syscon", "simple-mfd"; reg = <0x400a7000 0x2000>; @@ -561,6 +573,9 @@ clocks = <&clks VF610_CLK_DSPI2>; clock-names = "dspi"; spi-num-chipselects = <2>; + dmas = <&edma1 0 10>, + <&edma1 0 11>; + dma-names = "rx", "tx"; status = "disabled"; }; @@ -573,6 +588,9 @@ clocks = <&clks VF610_CLK_DSPI3>; clock-names = "dspi"; spi-num-chipselects = <2>; + dmas = <&edma1 0 12>, + <&edma1 0 13>; + dma-names = "rx", "tx"; status = "disabled"; }; diff --git a/arch/arm/configs/multi_v7_defconfig b/arch/arm/configs/multi_v7_defconfig index 437d0740dec6..11f37ed1dbff 100644 --- a/arch/arm/configs/multi_v7_defconfig +++ b/arch/arm/configs/multi_v7_defconfig @@ -850,6 +850,7 @@ CONFIG_PWM_SUN4I=y CONFIG_PWM_TEGRA=y CONFIG_PWM_VT8500=y CONFIG_PHY_HIX5HD2_SATA=y +CONFIG_E1000E=y CONFIG_PWM_STI=y CONFIG_PWM_BCM2835=y CONFIG_PWM_BRCMSTB=m diff --git a/arch/arm/kvm/arm.c b/arch/arm/kvm/arm.c index 03e9273f1876..08bb84f2ad58 100644 --- a/arch/arm/kvm/arm.c +++ b/arch/arm/kvm/arm.c @@ -1312,6 +1312,13 @@ static int init_hyp_mode(void) goto out_err; } + err = create_hyp_mappings(kvm_ksym_ref(__bss_start), + kvm_ksym_ref(__bss_stop), PAGE_HYP_RO); + if (err) { + kvm_err("Cannot map bss section\n"); + goto out_err; + } + /* * Map the Hyp stack pages */ diff --git a/arch/arm/mach-imx/gpc.c b/arch/arm/mach-imx/gpc.c index 0df062d8b2c9..b54db47f6f32 100644 --- a/arch/arm/mach-imx/gpc.c +++ b/arch/arm/mach-imx/gpc.c @@ -408,7 +408,7 @@ static struct genpd_onecell_data imx_gpc_onecell_data = { static int imx_gpc_genpd_init(struct device *dev, struct regulator *pu_reg) { struct clk *clk; - int i; + int i, ret; imx6q_pu_domain.reg = pu_reg; @@ -430,13 +430,22 @@ static int imx_gpc_genpd_init(struct device *dev, struct regulator *pu_reg) if (!IS_ENABLED(CONFIG_PM_GENERIC_DOMAINS)) return 0; - pm_genpd_init(&imx6q_pu_domain.base, NULL, false); - return of_genpd_add_provider_onecell(dev->of_node, + for (i = 0; i < ARRAY_SIZE(imx_gpc_domains); i++) + pm_genpd_init(imx_gpc_domains[i], NULL, false); + + ret = of_genpd_add_provider_onecell(dev->of_node, &imx_gpc_onecell_data); + if (ret) + goto power_off; + + return 0; +power_off: + imx6q_pm_pu_power_off(&imx6q_pu_domain.base); clk_err: while (i--) clk_put(imx6q_pu_domain.clk[i]); + imx6q_pu_domain.reg = NULL; return -EINVAL; } diff --git a/arch/arm/mach-imx/mach-imx6q.c b/arch/arm/mach-imx/mach-imx6q.c index 97fd25105e2c..45801b27ee5c 100644 --- a/arch/arm/mach-imx/mach-imx6q.c +++ b/arch/arm/mach-imx/mach-imx6q.c @@ -173,7 +173,7 @@ static void __init imx6q_enet_phy_init(void) ksz9021rn_phy_fixup); phy_register_fixup_for_uid(PHY_ID_KSZ9031, MICREL_PHY_ID_MASK, ksz9031rn_phy_fixup); - phy_register_fixup_for_uid(PHY_ID_AR8031, 0xffffffff, + phy_register_fixup_for_uid(PHY_ID_AR8031, 0xffffffef, ar8031_phy_fixup); phy_register_fixup_for_uid(PHY_ID_AR8035, 0xffffffef, ar8035_phy_fixup); diff --git a/arch/arm/mach-mvebu/Kconfig b/arch/arm/mach-mvebu/Kconfig index f9b6bd306cfe..541647f57192 100644 --- a/arch/arm/mach-mvebu/Kconfig +++ b/arch/arm/mach-mvebu/Kconfig @@ -23,6 +23,7 @@ config MACH_MVEBU_V7 select CACHE_L2X0 select ARM_CPU_SUSPEND select MACH_MVEBU_ANY + select MVEBU_CLK_COREDIV config MACH_ARMADA_370 bool "Marvell Armada 370 boards" @@ -32,7 +33,6 @@ config MACH_ARMADA_370 select CPU_PJ4B select MACH_MVEBU_V7 select PINCTRL_ARMADA_370 - select MVEBU_CLK_COREDIV help Say 'Y' here if you want your kernel to support boards based on the Marvell Armada 370 SoC with device tree. @@ -50,7 +50,6 @@ config MACH_ARMADA_375 select HAVE_SMP select MACH_MVEBU_V7 select PINCTRL_ARMADA_375 - select MVEBU_CLK_COREDIV help Say 'Y' here if you want your kernel to support boards based on the Marvell Armada 375 SoC with device tree. @@ -68,7 +67,6 @@ config MACH_ARMADA_38X select HAVE_SMP select MACH_MVEBU_V7 select PINCTRL_ARMADA_38X - select MVEBU_CLK_COREDIV help Say 'Y' here if you want your kernel to support boards based on the Marvell Armada 380/385 SoC with device tree. diff --git a/arch/arm/mach-uniphier/Kconfig b/arch/arm/mach-uniphier/Kconfig index 82dddee3a469..3930fbba30b4 100644 --- a/arch/arm/mach-uniphier/Kconfig +++ b/arch/arm/mach-uniphier/Kconfig @@ -1,6 +1,7 @@ config ARCH_UNIPHIER bool "Socionext UniPhier SoCs" depends on ARCH_MULTI_V7 + select ARCH_HAS_RESET_CONTROLLER select ARM_AMBA select ARM_GLOBAL_TIMER select ARM_GIC diff --git a/arch/arm64/Kconfig b/arch/arm64/Kconfig index 30398dbc940a..969ef880d234 100644 --- a/arch/arm64/Kconfig +++ b/arch/arm64/Kconfig @@ -915,7 +915,7 @@ config RANDOMIZE_BASE config RANDOMIZE_MODULE_REGION_FULL bool "Randomize the module region independently from the core kernel" - depends on RANDOMIZE_BASE + depends on RANDOMIZE_BASE && !DYNAMIC_FTRACE default y help Randomizes the location of the module region without considering the diff --git a/arch/arm64/Kconfig.platforms b/arch/arm64/Kconfig.platforms index cfbdf02ef566..101794f5ce10 100644 --- a/arch/arm64/Kconfig.platforms +++ b/arch/arm64/Kconfig.platforms @@ -190,6 +190,7 @@ config ARCH_THUNDER config ARCH_UNIPHIER bool "Socionext UniPhier SoC Family" + select ARCH_HAS_RESET_CONTROLLER select PINCTRL help This enables support for Socionext UniPhier SoC family. diff --git a/arch/arm64/Makefile b/arch/arm64/Makefile index ab51aed6b6c1..3635b8662724 100644 --- a/arch/arm64/Makefile +++ b/arch/arm64/Makefile @@ -15,7 +15,7 @@ CPPFLAGS_vmlinux.lds = -DTEXT_OFFSET=$(TEXT_OFFSET) GZFLAGS :=-9 ifneq ($(CONFIG_RELOCATABLE),) -LDFLAGS_vmlinux += -pie -Bsymbolic +LDFLAGS_vmlinux += -pie -shared -Bsymbolic endif ifeq ($(CONFIG_ARM64_ERRATUM_843419),y) diff --git a/arch/arm64/boot/dts/broadcom/ns2-svk.dts b/arch/arm64/boot/dts/broadcom/ns2-svk.dts index 2d7872a36b91..b09f3bc5c6c1 100644 --- a/arch/arm64/boot/dts/broadcom/ns2-svk.dts +++ b/arch/arm64/boot/dts/broadcom/ns2-svk.dts @@ -164,6 +164,8 @@ nand-ecc-mode = "hw"; nand-ecc-strength = <8>; nand-ecc-step-size = <512>; + nand-bus-width = <16>; + brcm,nand-oob-sector-size = <16>; #address-cells = <1>; #size-cells = <1>; }; diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi b/arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi index 220ac7057d12..97d331ec2500 100644 --- a/arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi +++ b/arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi @@ -123,6 +123,7 @@ <1 14 0xf08>, /* Physical Non-Secure PPI */ <1 11 0xf08>, /* Virtual PPI */ <1 10 0xf08>; /* Hypervisor PPI */ + fsl,erratum-a008585; }; pmu { diff --git a/arch/arm64/boot/dts/freescale/fsl-ls2080a.dtsi b/arch/arm64/boot/dts/freescale/fsl-ls2080a.dtsi index 337da90bd7da..7f0dc13b4087 100644 --- a/arch/arm64/boot/dts/freescale/fsl-ls2080a.dtsi +++ b/arch/arm64/boot/dts/freescale/fsl-ls2080a.dtsi @@ -195,6 +195,7 @@ <1 14 4>, /* Physical Non-Secure PPI, active-low */ <1 11 4>, /* Virtual PPI, active-low */ <1 10 4>; /* Hypervisor PPI, active-low */ + fsl,erratum-a008585; }; pmu { diff --git a/arch/arm64/boot/dts/hisilicon/hi6220.dtsi b/arch/arm64/boot/dts/hisilicon/hi6220.dtsi index 17839db585d5..8b5d42a90e89 100644 --- a/arch/arm64/boot/dts/hisilicon/hi6220.dtsi +++ b/arch/arm64/boot/dts/hisilicon/hi6220.dtsi @@ -364,6 +364,7 @@ reg = <0x0 0xf7010000 0x0 0x27c>; #address-cells = <1>; #size-cells = <1>; + #pinctrl-cells = <1>; #gpio-range-cells = <3>; pinctrl-single,register-width = <32>; pinctrl-single,function-mask = <7>; @@ -402,6 +403,7 @@ reg = <0x0 0xf7010800 0x0 0x28c>; #address-cells = <1>; #size-cells = <1>; + #pinctrl-cells = <1>; pinctrl-single,register-width = <32>; }; @@ -410,6 +412,7 @@ reg = <0x0 0xf8001800 0x0 0x78>; #address-cells = <1>; #size-cells = <1>; + #pinctrl-cells = <1>; pinctrl-single,register-width = <32>; }; diff --git a/arch/arm64/boot/dts/marvell/armada-cp110-master.dtsi b/arch/arm64/boot/dts/marvell/armada-cp110-master.dtsi index e5e3ed678b6f..602e2c2e9a4d 100644 --- a/arch/arm64/boot/dts/marvell/armada-cp110-master.dtsi +++ b/arch/arm64/boot/dts/marvell/armada-cp110-master.dtsi @@ -131,7 +131,7 @@ #address-cells = <0x1>; #size-cells = <0x0>; cell-index = <1>; - clocks = <&cpm_syscon0 0 3>; + clocks = <&cpm_syscon0 1 21>; status = "disabled"; }; diff --git a/arch/arm64/boot/dts/mediatek/mt8173.dtsi b/arch/arm64/boot/dts/mediatek/mt8173.dtsi index 1c71e256601d..6c03c1702bb3 100644 --- a/arch/arm64/boot/dts/mediatek/mt8173.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt8173.dtsi @@ -450,6 +450,9 @@ auxadc: auxadc@11001000 { compatible = "mediatek,mt8173-auxadc"; reg = <0 0x11001000 0 0x1000>; + clocks = <&pericfg CLK_PERI_AUXADC>; + clock-names = "main"; + #io-channel-cells = <1>; }; uart0: serial@11002000 { diff --git a/arch/arm64/boot/dts/rockchip/rk3368-geekbox.dts b/arch/arm64/boot/dts/rockchip/rk3368-geekbox.dts index 46cdddfcea6c..e5eeca2c2456 100644 --- a/arch/arm64/boot/dts/rockchip/rk3368-geekbox.dts +++ b/arch/arm64/boot/dts/rockchip/rk3368-geekbox.dts @@ -116,7 +116,6 @@ cap-mmc-highspeed; clock-frequency = <150000000>; disable-wp; - keep-power-in-suspend; non-removable; num-slots = <1>; vmmc-supply = <&vcc_io>; @@ -258,8 +257,6 @@ }; vcc_sd: SWITCH_REG1 { - regulator-always-on; - regulator-boot-on; regulator-name = "vcc_sd"; }; diff --git a/arch/arm64/boot/dts/rockchip/rk3368-orion-r68-meta.dts b/arch/arm64/boot/dts/rockchip/rk3368-orion-r68-meta.dts index 5797933ef80e..ea0a8eceefd4 100644 --- a/arch/arm64/boot/dts/rockchip/rk3368-orion-r68-meta.dts +++ b/arch/arm64/boot/dts/rockchip/rk3368-orion-r68-meta.dts @@ -152,8 +152,6 @@ gpio = <&gpio3 11 GPIO_ACTIVE_LOW>; regulator-min-microvolt = <1800000>; regulator-max-microvolt = <3300000>; - regulator-always-on; - regulator-boot-on; vin-supply = <&vcc_io>; }; @@ -201,7 +199,6 @@ bus-width = <8>; cap-mmc-highspeed; disable-wp; - keep-power-in-suspend; mmc-pwrseq = <&emmc_pwrseq>; mmc-hs200-1_2v; mmc-hs200-1_8v; @@ -350,7 +347,6 @@ clock-freq-min-max = <400000 50000000>; cap-sd-highspeed; card-detect-delay = <200>; - keep-power-in-suspend; num-slots = <1>; pinctrl-names = "default"; pinctrl-0 = <&sdmmc_clk &sdmmc_cmd &sdmmc_cd &sdmmc_bus4>; diff --git a/arch/arm64/boot/dts/socionext/uniphier-ld20.dtsi b/arch/arm64/boot/dts/socionext/uniphier-ld20.dtsi index 08fd7cf7769c..56a1b2e92cf3 100644 --- a/arch/arm64/boot/dts/socionext/uniphier-ld20.dtsi +++ b/arch/arm64/boot/dts/socionext/uniphier-ld20.dtsi @@ -257,18 +257,18 @@ reg = <0x59801000 0x400>; }; - mioctrl@59810000 { - compatible = "socionext,uniphier-mioctrl", + sdctrl@59810000 { + compatible = "socionext,uniphier-ld20-sdctrl", "simple-mfd", "syscon"; reg = <0x59810000 0x800>; - mio_clk: clock { - compatible = "socionext,uniphier-ld20-mio-clock"; + sd_clk: clock { + compatible = "socionext,uniphier-ld20-sd-clock"; #clock-cells = <1>; }; - mio_rst: reset { - compatible = "socionext,uniphier-ld20-mio-reset"; + sd_rst: reset { + compatible = "socionext,uniphier-ld20-sd-reset"; #reset-cells = <1>; }; }; diff --git a/arch/arm64/include/asm/cpufeature.h b/arch/arm64/include/asm/cpufeature.h index 758d74fedfad..a27c3245ba21 100644 --- a/arch/arm64/include/asm/cpufeature.h +++ b/arch/arm64/include/asm/cpufeature.h @@ -94,7 +94,7 @@ struct arm64_cpu_capabilities { u16 capability; int def_scope; /* default scope */ bool (*matches)(const struct arm64_cpu_capabilities *caps, int scope); - void (*enable)(void *); /* Called on all active CPUs */ + int (*enable)(void *); /* Called on all active CPUs */ union { struct { /* To be used for erratum handling only */ u32 midr_model; diff --git a/arch/arm64/include/asm/exec.h b/arch/arm64/include/asm/exec.h index db0563c23482..f7865dd9d868 100644 --- a/arch/arm64/include/asm/exec.h +++ b/arch/arm64/include/asm/exec.h @@ -18,6 +18,9 @@ #ifndef __ASM_EXEC_H #define __ASM_EXEC_H +#include <linux/sched.h> + extern unsigned long arch_align_stack(unsigned long sp); +void uao_thread_switch(struct task_struct *next); #endif /* __ASM_EXEC_H */ diff --git a/arch/arm64/include/asm/kvm_emulate.h b/arch/arm64/include/asm/kvm_emulate.h index fd9d5fd788f5..f5ea0ba70f07 100644 --- a/arch/arm64/include/asm/kvm_emulate.h +++ b/arch/arm64/include/asm/kvm_emulate.h @@ -178,11 +178,6 @@ static inline bool kvm_vcpu_dabt_isvalid(const struct kvm_vcpu *vcpu) return !!(kvm_vcpu_get_hsr(vcpu) & ESR_ELx_ISV); } -static inline bool kvm_vcpu_dabt_iswrite(const struct kvm_vcpu *vcpu) -{ - return !!(kvm_vcpu_get_hsr(vcpu) & ESR_ELx_WNR); -} - static inline bool kvm_vcpu_dabt_issext(const struct kvm_vcpu *vcpu) { return !!(kvm_vcpu_get_hsr(vcpu) & ESR_ELx_SSE); @@ -203,6 +198,12 @@ static inline bool kvm_vcpu_dabt_iss1tw(const struct kvm_vcpu *vcpu) return !!(kvm_vcpu_get_hsr(vcpu) & ESR_ELx_S1PTW); } +static inline bool kvm_vcpu_dabt_iswrite(const struct kvm_vcpu *vcpu) +{ + return !!(kvm_vcpu_get_hsr(vcpu) & ESR_ELx_WNR) || + kvm_vcpu_dabt_iss1tw(vcpu); /* AF/DBM update */ +} + static inline bool kvm_vcpu_dabt_is_cm(const struct kvm_vcpu *vcpu) { return !!(kvm_vcpu_get_hsr(vcpu) & ESR_ELx_CM); diff --git a/arch/arm64/include/asm/memory.h b/arch/arm64/include/asm/memory.h index ba62df8c6e35..b71086d25195 100644 --- a/arch/arm64/include/asm/memory.h +++ b/arch/arm64/include/asm/memory.h @@ -217,7 +217,7 @@ static inline void *phys_to_virt(phys_addr_t x) #define _virt_addr_valid(kaddr) pfn_valid(__pa(kaddr) >> PAGE_SHIFT) #else #define __virt_to_pgoff(kaddr) (((u64)(kaddr) & ~PAGE_OFFSET) / PAGE_SIZE * sizeof(struct page)) -#define __page_to_voff(kaddr) (((u64)(page) & ~VMEMMAP_START) * PAGE_SIZE / sizeof(struct page)) +#define __page_to_voff(page) (((u64)(page) & ~VMEMMAP_START) * PAGE_SIZE / sizeof(struct page)) #define page_to_virt(page) ((void *)((__page_to_voff(page)) | PAGE_OFFSET)) #define virt_to_page(vaddr) ((struct page *)((__virt_to_pgoff(vaddr)) | VMEMMAP_START)) diff --git a/arch/arm64/include/asm/module.h b/arch/arm64/include/asm/module.h index e12af6754634..06ff7fd9e81f 100644 --- a/arch/arm64/include/asm/module.h +++ b/arch/arm64/include/asm/module.h @@ -17,6 +17,7 @@ #define __ASM_MODULE_H #include <asm-generic/module.h> +#include <asm/memory.h> #define MODULE_ARCH_VERMAGIC "aarch64" @@ -32,6 +33,10 @@ u64 module_emit_plt_entry(struct module *mod, const Elf64_Rela *rela, Elf64_Sym *sym); #ifdef CONFIG_RANDOMIZE_BASE +#ifdef CONFIG_MODVERSIONS +#define ARCH_RELOCATES_KCRCTAB +#define reloc_start (kimage_vaddr - KIMAGE_VADDR) +#endif extern u64 module_alloc_base; #else #define module_alloc_base ((u64)_etext - MODULES_VSIZE) diff --git a/arch/arm64/include/asm/percpu.h b/arch/arm64/include/asm/percpu.h index 2fee2f59288c..5394c8405e66 100644 --- a/arch/arm64/include/asm/percpu.h +++ b/arch/arm64/include/asm/percpu.h @@ -44,48 +44,44 @@ static inline unsigned long __percpu_##op(void *ptr, \ \ switch (size) { \ case 1: \ - do { \ - asm ("//__per_cpu_" #op "_1\n" \ - "ldxrb %w[ret], %[ptr]\n" \ + asm ("//__per_cpu_" #op "_1\n" \ + "1: ldxrb %w[ret], %[ptr]\n" \ #asm_op " %w[ret], %w[ret], %w[val]\n" \ - "stxrb %w[loop], %w[ret], %[ptr]\n" \ - : [loop] "=&r" (loop), [ret] "=&r" (ret), \ - [ptr] "+Q"(*(u8 *)ptr) \ - : [val] "Ir" (val)); \ - } while (loop); \ + " stxrb %w[loop], %w[ret], %[ptr]\n" \ + " cbnz %w[loop], 1b" \ + : [loop] "=&r" (loop), [ret] "=&r" (ret), \ + [ptr] "+Q"(*(u8 *)ptr) \ + : [val] "Ir" (val)); \ break; \ case 2: \ - do { \ - asm ("//__per_cpu_" #op "_2\n" \ - "ldxrh %w[ret], %[ptr]\n" \ + asm ("//__per_cpu_" #op "_2\n" \ + "1: ldxrh %w[ret], %[ptr]\n" \ #asm_op " %w[ret], %w[ret], %w[val]\n" \ - "stxrh %w[loop], %w[ret], %[ptr]\n" \ - : [loop] "=&r" (loop), [ret] "=&r" (ret), \ - [ptr] "+Q"(*(u16 *)ptr) \ - : [val] "Ir" (val)); \ - } while (loop); \ + " stxrh %w[loop], %w[ret], %[ptr]\n" \ + " cbnz %w[loop], 1b" \ + : [loop] "=&r" (loop), [ret] "=&r" (ret), \ + [ptr] "+Q"(*(u16 *)ptr) \ + : [val] "Ir" (val)); \ break; \ case 4: \ - do { \ - asm ("//__per_cpu_" #op "_4\n" \ - "ldxr %w[ret], %[ptr]\n" \ + asm ("//__per_cpu_" #op "_4\n" \ + "1: ldxr %w[ret], %[ptr]\n" \ #asm_op " %w[ret], %w[ret], %w[val]\n" \ - "stxr %w[loop], %w[ret], %[ptr]\n" \ - : [loop] "=&r" (loop), [ret] "=&r" (ret), \ - [ptr] "+Q"(*(u32 *)ptr) \ - : [val] "Ir" (val)); \ - } while (loop); \ + " stxr %w[loop], %w[ret], %[ptr]\n" \ + " cbnz %w[loop], 1b" \ + : [loop] "=&r" (loop), [ret] "=&r" (ret), \ + [ptr] "+Q"(*(u32 *)ptr) \ + : [val] "Ir" (val)); \ break; \ case 8: \ - do { \ - asm ("//__per_cpu_" #op "_8\n" \ - "ldxr %[ret], %[ptr]\n" \ + asm ("//__per_cpu_" #op "_8\n" \ + "1: ldxr %[ret], %[ptr]\n" \ #asm_op " %[ret], %[ret], %[val]\n" \ - "stxr %w[loop], %[ret], %[ptr]\n" \ - : [loop] "=&r" (loop), [ret] "=&r" (ret), \ - [ptr] "+Q"(*(u64 *)ptr) \ - : [val] "Ir" (val)); \ - } while (loop); \ + " stxr %w[loop], %[ret], %[ptr]\n" \ + " cbnz %w[loop], 1b" \ + : [loop] "=&r" (loop), [ret] "=&r" (ret), \ + [ptr] "+Q"(*(u64 *)ptr) \ + : [val] "Ir" (val)); \ break; \ default: \ BUILD_BUG(); \ @@ -150,44 +146,40 @@ static inline unsigned long __percpu_xchg(void *ptr, unsigned long val, switch (size) { case 1: - do { - asm ("//__percpu_xchg_1\n" - "ldxrb %w[ret], %[ptr]\n" - "stxrb %w[loop], %w[val], %[ptr]\n" - : [loop] "=&r"(loop), [ret] "=&r"(ret), - [ptr] "+Q"(*(u8 *)ptr) - : [val] "r" (val)); - } while (loop); + asm ("//__percpu_xchg_1\n" + "1: ldxrb %w[ret], %[ptr]\n" + " stxrb %w[loop], %w[val], %[ptr]\n" + " cbnz %w[loop], 1b" + : [loop] "=&r"(loop), [ret] "=&r"(ret), + [ptr] "+Q"(*(u8 *)ptr) + : [val] "r" (val)); break; case 2: - do { - asm ("//__percpu_xchg_2\n" - "ldxrh %w[ret], %[ptr]\n" - "stxrh %w[loop], %w[val], %[ptr]\n" - : [loop] "=&r"(loop), [ret] "=&r"(ret), - [ptr] "+Q"(*(u16 *)ptr) - : [val] "r" (val)); - } while (loop); + asm ("//__percpu_xchg_2\n" + "1: ldxrh %w[ret], %[ptr]\n" + " stxrh %w[loop], %w[val], %[ptr]\n" + " cbnz %w[loop], 1b" + : [loop] "=&r"(loop), [ret] "=&r"(ret), + [ptr] "+Q"(*(u16 *)ptr) + : [val] "r" (val)); break; case 4: - do { - asm ("//__percpu_xchg_4\n" - "ldxr %w[ret], %[ptr]\n" - "stxr %w[loop], %w[val], %[ptr]\n" - : [loop] "=&r"(loop), [ret] "=&r"(ret), - [ptr] "+Q"(*(u32 *)ptr) - : [val] "r" (val)); - } while (loop); + asm ("//__percpu_xchg_4\n" + "1: ldxr %w[ret], %[ptr]\n" + " stxr %w[loop], %w[val], %[ptr]\n" + " cbnz %w[loop], 1b" + : [loop] "=&r"(loop), [ret] "=&r"(ret), + [ptr] "+Q"(*(u32 *)ptr) + : [val] "r" (val)); break; case 8: - do { - asm ("//__percpu_xchg_8\n" - "ldxr %[ret], %[ptr]\n" - "stxr %w[loop], %[val], %[ptr]\n" - : [loop] "=&r"(loop), [ret] "=&r"(ret), - [ptr] "+Q"(*(u64 *)ptr) - : [val] "r" (val)); - } while (loop); + asm ("//__percpu_xchg_8\n" + "1: ldxr %[ret], %[ptr]\n" + " stxr %w[loop], %[val], %[ptr]\n" + " cbnz %w[loop], 1b" + : [loop] "=&r"(loop), [ret] "=&r"(ret), + [ptr] "+Q"(*(u64 *)ptr) + : [val] "r" (val)); break; default: BUILD_BUG(); diff --git a/arch/arm64/include/asm/processor.h b/arch/arm64/include/asm/processor.h index df2e53d3a969..60e34824e18c 100644 --- a/arch/arm64/include/asm/processor.h +++ b/arch/arm64/include/asm/processor.h @@ -188,8 +188,8 @@ static inline void spin_lock_prefetch(const void *ptr) #endif -void cpu_enable_pan(void *__unused); -void cpu_enable_uao(void *__unused); -void cpu_enable_cache_maint_trap(void *__unused); +int cpu_enable_pan(void *__unused); +int cpu_enable_uao(void *__unused); +int cpu_enable_cache_maint_trap(void *__unused); #endif /* __ASM_PROCESSOR_H */ diff --git a/arch/arm64/include/asm/sysreg.h b/arch/arm64/include/asm/sysreg.h index e8d46e8e6079..6c80b3699cb8 100644 --- a/arch/arm64/include/asm/sysreg.h +++ b/arch/arm64/include/asm/sysreg.h @@ -286,7 +286,7 @@ asm( #define write_sysreg_s(v, r) do { \ u64 __val = (u64)v; \ - asm volatile("msr_s " __stringify(r) ", %0" : : "rZ" (__val)); \ + asm volatile("msr_s " __stringify(r) ", %x0" : : "rZ" (__val)); \ } while (0) static inline void config_sctlr_el1(u32 clear, u32 set) diff --git a/arch/arm64/include/asm/uaccess.h b/arch/arm64/include/asm/uaccess.h index bcaf6fba1b65..55d0adbf6509 100644 --- a/arch/arm64/include/asm/uaccess.h +++ b/arch/arm64/include/asm/uaccess.h @@ -21,6 +21,7 @@ /* * User space memory access functions */ +#include <linux/bitops.h> #include <linux/kasan-checks.h> #include <linux/string.h> #include <linux/thread_info.h> @@ -102,6 +103,13 @@ static inline void set_fs(mm_segment_t fs) flag; \ }) +/* + * When dealing with data aborts or instruction traps we may end up with + * a tagged userland pointer. Clear the tag to get a sane pointer to pass + * on to access_ok(), for instance. + */ +#define untagged_addr(addr) sign_extend64(addr, 55) + #define access_ok(type, addr, size) __range_ok(addr, size) #define user_addr_max get_fs diff --git a/arch/arm64/kernel/armv8_deprecated.c b/arch/arm64/kernel/armv8_deprecated.c index 42ffdb54e162..b0988bb1bf64 100644 --- a/arch/arm64/kernel/armv8_deprecated.c +++ b/arch/arm64/kernel/armv8_deprecated.c @@ -280,35 +280,43 @@ static void __init register_insn_emulation_sysctl(struct ctl_table *table) /* * Error-checking SWP macros implemented using ldxr{b}/stxr{b} */ -#define __user_swpX_asm(data, addr, res, temp, B) \ + +/* Arbitrary constant to ensure forward-progress of the LL/SC loop */ +#define __SWP_LL_SC_LOOPS 4 + +#define __user_swpX_asm(data, addr, res, temp, temp2, B) \ __asm__ __volatile__( \ + " mov %w3, %w7\n" \ ALTERNATIVE("nop", SET_PSTATE_PAN(0), ARM64_HAS_PAN, \ CONFIG_ARM64_PAN) \ - "0: ldxr"B" %w2, [%3]\n" \ - "1: stxr"B" %w0, %w1, [%3]\n" \ + "0: ldxr"B" %w2, [%4]\n" \ + "1: stxr"B" %w0, %w1, [%4]\n" \ " cbz %w0, 2f\n" \ - " mov %w0, %w4\n" \ + " sub %w3, %w3, #1\n" \ + " cbnz %w3, 0b\n" \ + " mov %w0, %w5\n" \ " b 3f\n" \ "2:\n" \ " mov %w1, %w2\n" \ "3:\n" \ " .pushsection .fixup,\"ax\"\n" \ " .align 2\n" \ - "4: mov %w0, %w5\n" \ + "4: mov %w0, %w6\n" \ " b 3b\n" \ " .popsection" \ _ASM_EXTABLE(0b, 4b) \ _ASM_EXTABLE(1b, 4b) \ ALTERNATIVE("nop", SET_PSTATE_PAN(1), ARM64_HAS_PAN, \ CONFIG_ARM64_PAN) \ - : "=&r" (res), "+r" (data), "=&r" (temp) \ - : "r" (addr), "i" (-EAGAIN), "i" (-EFAULT) \ + : "=&r" (res), "+r" (data), "=&r" (temp), "=&r" (temp2) \ + : "r" (addr), "i" (-EAGAIN), "i" (-EFAULT), \ + "i" (__SWP_LL_SC_LOOPS) \ : "memory") -#define __user_swp_asm(data, addr, res, temp) \ - __user_swpX_asm(data, addr, res, temp, "") -#define __user_swpb_asm(data, addr, res, temp) \ - __user_swpX_asm(data, addr, res, temp, "b") +#define __user_swp_asm(data, addr, res, temp, temp2) \ + __user_swpX_asm(data, addr, res, temp, temp2, "") +#define __user_swpb_asm(data, addr, res, temp, temp2) \ + __user_swpX_asm(data, addr, res, temp, temp2, "b") /* * Bit 22 of the instruction encoding distinguishes between @@ -328,12 +336,12 @@ static int emulate_swpX(unsigned int address, unsigned int *data, } while (1) { - unsigned long temp; + unsigned long temp, temp2; if (type == TYPE_SWPB) - __user_swpb_asm(*data, address, res, temp); + __user_swpb_asm(*data, address, res, temp, temp2); else - __user_swp_asm(*data, address, res, temp); + __user_swp_asm(*data, address, res, temp, temp2); if (likely(res != -EAGAIN) || signal_pending(current)) break; diff --git a/arch/arm64/kernel/cpu_errata.c b/arch/arm64/kernel/cpu_errata.c index 0150394f4cab..b75e917aac46 100644 --- a/arch/arm64/kernel/cpu_errata.c +++ b/arch/arm64/kernel/cpu_errata.c @@ -39,10 +39,11 @@ has_mismatched_cache_line_size(const struct arm64_cpu_capabilities *entry, (arm64_ftr_reg_ctrel0.sys_val & arm64_ftr_reg_ctrel0.strict_mask); } -static void cpu_enable_trap_ctr_access(void *__unused) +static int cpu_enable_trap_ctr_access(void *__unused) { /* Clear SCTLR_EL1.UCT */ config_sctlr_el1(SCTLR_EL1_UCT, 0); + return 0; } #define MIDR_RANGE(model, min, max) \ diff --git a/arch/arm64/kernel/cpufeature.c b/arch/arm64/kernel/cpufeature.c index d577f263cc4a..c02504ea304b 100644 --- a/arch/arm64/kernel/cpufeature.c +++ b/arch/arm64/kernel/cpufeature.c @@ -19,7 +19,9 @@ #define pr_fmt(fmt) "CPU features: " fmt #include <linux/bsearch.h> +#include <linux/cpumask.h> #include <linux/sort.h> +#include <linux/stop_machine.h> #include <linux/types.h> #include <asm/cpu.h> #include <asm/cpufeature.h> @@ -941,7 +943,13 @@ void __init enable_cpu_capabilities(const struct arm64_cpu_capabilities *caps) { for (; caps->matches; caps++) if (caps->enable && cpus_have_cap(caps->capability)) - on_each_cpu(caps->enable, NULL, true); + /* + * Use stop_machine() as it schedules the work allowing + * us to modify PSTATE, instead of on_each_cpu() which + * uses an IPI, giving us a PSTATE that disappears when + * we return. + */ + stop_machine(caps->enable, NULL, cpu_online_mask); } /* diff --git a/arch/arm64/kernel/head.S b/arch/arm64/kernel/head.S index 427f6d3f084c..332e33193ccf 100644 --- a/arch/arm64/kernel/head.S +++ b/arch/arm64/kernel/head.S @@ -586,8 +586,9 @@ CPU_LE( movk x0, #0x30d0, lsl #16 ) // Clear EE and E0E on LE systems b.lt 4f // Skip if no PMU present mrs x0, pmcr_el0 // Disable debug access traps ubfx x0, x0, #11, #5 // to EL2 and allow access to - msr mdcr_el2, x0 // all PMU counters from EL1 4: + csel x0, xzr, x0, lt // all PMU counters from EL1 + msr mdcr_el2, x0 // (if they exist) /* Stage-2 translation */ msr vttbr_el2, xzr diff --git a/arch/arm64/kernel/process.c b/arch/arm64/kernel/process.c index 27b2f1387df4..01753cd7d3f0 100644 --- a/arch/arm64/kernel/process.c +++ b/arch/arm64/kernel/process.c @@ -49,6 +49,7 @@ #include <asm/alternative.h> #include <asm/compat.h> #include <asm/cacheflush.h> +#include <asm/exec.h> #include <asm/fpsimd.h> #include <asm/mmu_context.h> #include <asm/processor.h> @@ -186,10 +187,19 @@ void __show_regs(struct pt_regs *regs) printk("pc : [<%016llx>] lr : [<%016llx>] pstate: %08llx\n", regs->pc, lr, regs->pstate); printk("sp : %016llx\n", sp); - for (i = top_reg; i >= 0; i--) { + + i = top_reg; + + while (i >= 0) { printk("x%-2d: %016llx ", i, regs->regs[i]); - if (i % 2 == 0) - printk("\n"); + i--; + + if (i % 2 == 0) { + pr_cont("x%-2d: %016llx ", i, regs->regs[i]); + i--; + } + + pr_cont("\n"); } printk("\n"); } @@ -301,7 +311,7 @@ static void tls_thread_switch(struct task_struct *next) } /* Restore the UAO state depending on next's addr_limit */ -static void uao_thread_switch(struct task_struct *next) +void uao_thread_switch(struct task_struct *next) { if (IS_ENABLED(CONFIG_ARM64_UAO)) { if (task_thread_info(next)->addr_limit == KERNEL_DS) diff --git a/arch/arm64/kernel/sleep.S b/arch/arm64/kernel/sleep.S index b8799e7c79de..1bec41b5fda3 100644 --- a/arch/arm64/kernel/sleep.S +++ b/arch/arm64/kernel/sleep.S @@ -135,7 +135,7 @@ ENTRY(_cpu_resume) #ifdef CONFIG_KASAN mov x0, sp - bl kasan_unpoison_remaining_stack + bl kasan_unpoison_task_stack_below #endif ldp x19, x20, [x29, #16] diff --git a/arch/arm64/kernel/smp.c b/arch/arm64/kernel/smp.c index d3f151cfd4a1..8507703dabe4 100644 --- a/arch/arm64/kernel/smp.c +++ b/arch/arm64/kernel/smp.c @@ -544,6 +544,7 @@ acpi_map_gic_cpu_interface(struct acpi_madt_generic_interrupt *processor) return; } bootcpu_valid = true; + early_map_cpu_to_node(0, acpi_numa_get_nid(0, hwid)); return; } diff --git a/arch/arm64/kernel/suspend.c b/arch/arm64/kernel/suspend.c index ad734142070d..bb0cd787a9d3 100644 --- a/arch/arm64/kernel/suspend.c +++ b/arch/arm64/kernel/suspend.c @@ -1,8 +1,11 @@ #include <linux/ftrace.h> #include <linux/percpu.h> #include <linux/slab.h> +#include <asm/alternative.h> #include <asm/cacheflush.h> +#include <asm/cpufeature.h> #include <asm/debug-monitors.h> +#include <asm/exec.h> #include <asm/pgtable.h> #include <asm/memory.h> #include <asm/mmu_context.h> @@ -50,6 +53,14 @@ void notrace __cpu_suspend_exit(void) set_my_cpu_offset(per_cpu_offset(cpu)); /* + * PSTATE was not saved over suspend/resume, re-enable any detected + * features that might not have been set correctly. + */ + asm(ALTERNATIVE("nop", SET_PSTATE_PAN(1), ARM64_HAS_PAN, + CONFIG_ARM64_PAN)); + uao_thread_switch(current); + + /* * Restore HW breakpoint registers to sane values * before debug exceptions are possibly reenabled * through local_dbg_restore. diff --git a/arch/arm64/kernel/traps.c b/arch/arm64/kernel/traps.c index 5ff020f8fb7f..c9986b3e0a96 100644 --- a/arch/arm64/kernel/traps.c +++ b/arch/arm64/kernel/traps.c @@ -428,24 +428,28 @@ asmlinkage void __exception do_undefinstr(struct pt_regs *regs) force_signal_inject(SIGILL, ILL_ILLOPC, regs, 0); } -void cpu_enable_cache_maint_trap(void *__unused) +int cpu_enable_cache_maint_trap(void *__unused) { config_sctlr_el1(SCTLR_EL1_UCI, 0); + return 0; } #define __user_cache_maint(insn, address, res) \ - asm volatile ( \ - "1: " insn ", %1\n" \ - " mov %w0, #0\n" \ - "2:\n" \ - " .pushsection .fixup,\"ax\"\n" \ - " .align 2\n" \ - "3: mov %w0, %w2\n" \ - " b 2b\n" \ - " .popsection\n" \ - _ASM_EXTABLE(1b, 3b) \ - : "=r" (res) \ - : "r" (address), "i" (-EFAULT) ) + if (untagged_addr(address) >= user_addr_max()) \ + res = -EFAULT; \ + else \ + asm volatile ( \ + "1: " insn ", %1\n" \ + " mov %w0, #0\n" \ + "2:\n" \ + " .pushsection .fixup,\"ax\"\n" \ + " .align 2\n" \ + "3: mov %w0, %w2\n" \ + " b 2b\n" \ + " .popsection\n" \ + _ASM_EXTABLE(1b, 3b) \ + : "=r" (res) \ + : "r" (address), "i" (-EFAULT) ) static void user_cache_maint_handler(unsigned int esr, struct pt_regs *regs) { diff --git a/arch/arm64/mm/fault.c b/arch/arm64/mm/fault.c index 53d9159662fe..0f8788374815 100644 --- a/arch/arm64/mm/fault.c +++ b/arch/arm64/mm/fault.c @@ -29,7 +29,9 @@ #include <linux/sched.h> #include <linux/highmem.h> #include <linux/perf_event.h> +#include <linux/preempt.h> +#include <asm/bug.h> #include <asm/cpufeature.h> #include <asm/exception.h> #include <asm/debug-monitors.h> @@ -670,9 +672,17 @@ asmlinkage int __exception do_debug_exception(unsigned long addr, NOKPROBE_SYMBOL(do_debug_exception); #ifdef CONFIG_ARM64_PAN -void cpu_enable_pan(void *__unused) +int cpu_enable_pan(void *__unused) { + /* + * We modify PSTATE. This won't work from irq context as the PSTATE + * is discarded once we return from the exception. + */ + WARN_ON_ONCE(in_interrupt()); + config_sctlr_el1(SCTLR_EL1_SPAN, 0); + asm(SET_PSTATE_PAN(1)); + return 0; } #endif /* CONFIG_ARM64_PAN */ @@ -683,8 +693,9 @@ void cpu_enable_pan(void *__unused) * We need to enable the feature at runtime (instead of adding it to * PSR_MODE_EL1h) as the feature may not be implemented by the cpu. */ -void cpu_enable_uao(void *__unused) +int cpu_enable_uao(void *__unused) { asm(SET_PSTATE_UAO(1)); + return 0; } #endif /* CONFIG_ARM64_UAO */ diff --git a/arch/arm64/mm/init.c b/arch/arm64/mm/init.c index 21c489bdeb4e..212c4d1e2f26 100644 --- a/arch/arm64/mm/init.c +++ b/arch/arm64/mm/init.c @@ -421,35 +421,35 @@ void __init mem_init(void) pr_notice("Virtual kernel memory layout:\n"); #ifdef CONFIG_KASAN - pr_cont(" kasan : 0x%16lx - 0x%16lx (%6ld GB)\n", + pr_notice(" kasan : 0x%16lx - 0x%16lx (%6ld GB)\n", MLG(KASAN_SHADOW_START, KASAN_SHADOW_END)); #endif - pr_cont(" modules : 0x%16lx - 0x%16lx (%6ld MB)\n", + pr_notice(" modules : 0x%16lx - 0x%16lx (%6ld MB)\n", MLM(MODULES_VADDR, MODULES_END)); - pr_cont(" vmalloc : 0x%16lx - 0x%16lx (%6ld GB)\n", + pr_notice(" vmalloc : 0x%16lx - 0x%16lx (%6ld GB)\n", MLG(VMALLOC_START, VMALLOC_END)); - pr_cont(" .text : 0x%p" " - 0x%p" " (%6ld KB)\n", + pr_notice(" .text : 0x%p" " - 0x%p" " (%6ld KB)\n", MLK_ROUNDUP(_text, _etext)); - pr_cont(" .rodata : 0x%p" " - 0x%p" " (%6ld KB)\n", + pr_notice(" .rodata : 0x%p" " - 0x%p" " (%6ld KB)\n", MLK_ROUNDUP(__start_rodata, __init_begin)); - pr_cont(" .init : 0x%p" " - 0x%p" " (%6ld KB)\n", + pr_notice(" .init : 0x%p" " - 0x%p" " (%6ld KB)\n", MLK_ROUNDUP(__init_begin, __init_end)); - pr_cont(" .data : 0x%p" " - 0x%p" " (%6ld KB)\n", + pr_notice(" .data : 0x%p" " - 0x%p" " (%6ld KB)\n", MLK_ROUNDUP(_sdata, _edata)); - pr_cont(" .bss : 0x%p" " - 0x%p" " (%6ld KB)\n", + pr_notice(" .bss : 0x%p" " - 0x%p" " (%6ld KB)\n", MLK_ROUNDUP(__bss_start, __bss_stop)); - pr_cont(" fixed : 0x%16lx - 0x%16lx (%6ld KB)\n", + pr_notice(" fixed : 0x%16lx - 0x%16lx (%6ld KB)\n", MLK(FIXADDR_START, FIXADDR_TOP)); - pr_cont(" PCI I/O : 0x%16lx - 0x%16lx (%6ld MB)\n", + pr_notice(" PCI I/O : 0x%16lx - 0x%16lx (%6ld MB)\n", MLM(PCI_IO_START, PCI_IO_END)); #ifdef CONFIG_SPARSEMEM_VMEMMAP - pr_cont(" vmemmap : 0x%16lx - 0x%16lx (%6ld GB maximum)\n", + pr_notice(" vmemmap : 0x%16lx - 0x%16lx (%6ld GB maximum)\n", MLG(VMEMMAP_START, VMEMMAP_START + VMEMMAP_SIZE)); - pr_cont(" 0x%16lx - 0x%16lx (%6ld MB actual)\n", + pr_notice(" 0x%16lx - 0x%16lx (%6ld MB actual)\n", MLM((unsigned long)phys_to_page(memblock_start_of_DRAM()), (unsigned long)virt_to_page(high_memory))); #endif - pr_cont(" memory : 0x%16lx - 0x%16lx (%6ld MB)\n", + pr_notice(" memory : 0x%16lx - 0x%16lx (%6ld MB)\n", MLM(__phys_to_virt(memblock_start_of_DRAM()), (unsigned long)high_memory)); diff --git a/arch/arm64/mm/numa.c b/arch/arm64/mm/numa.c index 778a985c8a70..4b32168cf91a 100644 --- a/arch/arm64/mm/numa.c +++ b/arch/arm64/mm/numa.c @@ -147,7 +147,7 @@ static int __init early_cpu_to_node(int cpu) static int __init pcpu_cpu_distance(unsigned int from, unsigned int to) { - return node_distance(from, to); + return node_distance(early_cpu_to_node(from), early_cpu_to_node(to)); } static void * __init pcpu_fc_alloc(unsigned int cpu, size_t size, @@ -223,8 +223,11 @@ static void __init setup_node_data(int nid, u64 start_pfn, u64 end_pfn) void *nd; int tnid; - pr_info("Initmem setup node %d [mem %#010Lx-%#010Lx]\n", - nid, start_pfn << PAGE_SHIFT, (end_pfn << PAGE_SHIFT) - 1); + if (start_pfn < end_pfn) + pr_info("Initmem setup node %d [mem %#010Lx-%#010Lx]\n", nid, + start_pfn << PAGE_SHIFT, (end_pfn << PAGE_SHIFT) - 1); + else + pr_info("Initmem setup node %d [<memory-less node>]\n", nid); nd_pa = memblock_alloc_try_nid(nd_size, SMP_CACHE_BYTES, nid); nd = __va(nd_pa); diff --git a/arch/blackfin/kernel/ptrace.c b/arch/blackfin/kernel/ptrace.c index 8b8fe671b1a6..8d79286ee4e8 100644 --- a/arch/blackfin/kernel/ptrace.c +++ b/arch/blackfin/kernel/ptrace.c @@ -271,7 +271,7 @@ long arch_ptrace(struct task_struct *child, long request, case BFIN_MEM_ACCESS_CORE: case BFIN_MEM_ACCESS_CORE_ONLY: copied = access_process_vm(child, addr, &tmp, - to_copy, 0); + to_copy, FOLL_FORCE); if (copied) break; @@ -324,7 +324,8 @@ long arch_ptrace(struct task_struct *child, long request, case BFIN_MEM_ACCESS_CORE: case BFIN_MEM_ACCESS_CORE_ONLY: copied = access_process_vm(child, addr, &data, - to_copy, 1); + to_copy, + FOLL_FORCE | FOLL_WRITE); break; case BFIN_MEM_ACCESS_DMA: if (safe_dma_memcpy(paddr, &data, to_copy)) diff --git a/arch/cris/arch-v32/drivers/cryptocop.c b/arch/cris/arch-v32/drivers/cryptocop.c index b5698c876fcc..0068fd411a84 100644 --- a/arch/cris/arch-v32/drivers/cryptocop.c +++ b/arch/cris/arch-v32/drivers/cryptocop.c @@ -2722,7 +2722,6 @@ static int cryptocop_ioctl_process(struct inode *inode, struct file *filp, unsig err = get_user_pages((unsigned long int)(oper.indata + prev_ix), noinpages, 0, /* read access only for in data */ - 0, /* no force */ inpages, NULL); @@ -2736,8 +2735,7 @@ static int cryptocop_ioctl_process(struct inode *inode, struct file *filp, unsig if (oper.do_cipher){ err = get_user_pages((unsigned long int)oper.cipher_outdata, nooutpages, - 1, /* write access for out data */ - 0, /* no force */ + FOLL_WRITE, /* write access for out data */ outpages, NULL); up_read(¤t->mm->mmap_sem); @@ -3151,7 +3149,7 @@ static void print_dma_descriptors(struct cryptocop_int_operation *iop) printk("print_dma_descriptors start\n"); printk("iop:\n"); - printk("\tsid: 0x%lld\n", iop->sid); + printk("\tsid: 0x%llx\n", iop->sid); printk("\tcdesc_out: 0x%p\n", iop->cdesc_out); printk("\tcdesc_in: 0x%p\n", iop->cdesc_in); diff --git a/arch/cris/arch-v32/kernel/ptrace.c b/arch/cris/arch-v32/kernel/ptrace.c index f085229cf870..f0df654ac6fc 100644 --- a/arch/cris/arch-v32/kernel/ptrace.c +++ b/arch/cris/arch-v32/kernel/ptrace.c @@ -147,7 +147,7 @@ long arch_ptrace(struct task_struct *child, long request, /* The trampoline page is globally mapped, no page table to traverse.*/ tmp = *(unsigned long*)addr; } else { - copied = access_process_vm(child, addr, &tmp, sizeof(tmp), 0); + copied = access_process_vm(child, addr, &tmp, sizeof(tmp), FOLL_FORCE); if (copied != sizeof(tmp)) break; @@ -279,7 +279,7 @@ static int insn_size(struct task_struct *child, unsigned long pc) int opsize = 0; /* Read the opcode at pc (do what PTRACE_PEEKTEXT would do). */ - copied = access_process_vm(child, pc, &opcode, sizeof(opcode), 0); + copied = access_process_vm(child, pc, &opcode, sizeof(opcode), FOLL_FORCE); if (copied != sizeof(opcode)) return 0; diff --git a/arch/h8300/include/asm/thread_info.h b/arch/h8300/include/asm/thread_info.h index b408fe660cf8..3cef06875f5c 100644 --- a/arch/h8300/include/asm/thread_info.h +++ b/arch/h8300/include/asm/thread_info.h @@ -31,7 +31,6 @@ struct thread_info { int cpu; /* cpu we're on */ int preempt_count; /* 0 => preemptable, <0 => BUG */ mm_segment_t addr_limit; - struct restart_block restart_block; }; /* @@ -44,9 +43,6 @@ struct thread_info { .cpu = 0, \ .preempt_count = INIT_PREEMPT_COUNT, \ .addr_limit = KERNEL_DS, \ - .restart_block = { \ - .fn = do_no_restart_syscall, \ - }, \ } #define init_thread_info (init_thread_union.thread_info) diff --git a/arch/h8300/kernel/signal.c b/arch/h8300/kernel/signal.c index ad1f81f574e5..7138303cbbf2 100644 --- a/arch/h8300/kernel/signal.c +++ b/arch/h8300/kernel/signal.c @@ -79,7 +79,7 @@ restore_sigcontext(struct sigcontext *usc, int *pd0) unsigned int er0; /* Always make any pending restarted system calls return -EINTR */ - current_thread_info()->restart_block.fn = do_no_restart_syscall; + current->restart_block.fn = do_no_restart_syscall; /* restore passed registers */ #define COPY(r) do { err |= get_user(regs->r, &usc->sc_##r); } while (0) diff --git a/arch/ia64/kernel/err_inject.c b/arch/ia64/kernel/err_inject.c index 09f845793d12..5ed0ea92c5bf 100644 --- a/arch/ia64/kernel/err_inject.c +++ b/arch/ia64/kernel/err_inject.c @@ -142,7 +142,7 @@ store_virtual_to_phys(struct device *dev, struct device_attribute *attr, u64 virt_addr=simple_strtoull(buf, NULL, 16); int ret; - ret = get_user_pages(virt_addr, 1, VM_READ, 0, NULL, NULL); + ret = get_user_pages(virt_addr, 1, FOLL_WRITE, NULL, NULL); if (ret<=0) { #ifdef ERR_INJ_DEBUG printk("Virtual address %lx is not existing.\n",virt_addr); diff --git a/arch/ia64/kernel/ptrace.c b/arch/ia64/kernel/ptrace.c index 6f54d511cc50..31aa8c0f68e1 100644 --- a/arch/ia64/kernel/ptrace.c +++ b/arch/ia64/kernel/ptrace.c @@ -453,7 +453,7 @@ ia64_peek (struct task_struct *child, struct switch_stack *child_stack, return 0; } } - copied = access_process_vm(child, addr, &ret, sizeof(ret), 0); + copied = access_process_vm(child, addr, &ret, sizeof(ret), FOLL_FORCE); if (copied != sizeof(ret)) return -EIO; *val = ret; @@ -489,7 +489,8 @@ ia64_poke (struct task_struct *child, struct switch_stack *child_stack, *ia64_rse_skip_regs(krbs, regnum) = val; } } - } else if (access_process_vm(child, addr, &val, sizeof(val), 1) + } else if (access_process_vm(child, addr, &val, sizeof(val), + FOLL_FORCE | FOLL_WRITE) != sizeof(val)) return -EIO; return 0; @@ -543,7 +544,8 @@ ia64_sync_user_rbs (struct task_struct *child, struct switch_stack *sw, ret = ia64_peek(child, sw, user_rbs_end, addr, &val); if (ret < 0) return ret; - if (access_process_vm(child, addr, &val, sizeof(val), 1) + if (access_process_vm(child, addr, &val, sizeof(val), + FOLL_FORCE | FOLL_WRITE) != sizeof(val)) return -EIO; } @@ -559,7 +561,8 @@ ia64_sync_kernel_rbs (struct task_struct *child, struct switch_stack *sw, /* now copy word for word from user rbs to kernel rbs: */ for (addr = user_rbs_start; addr < user_rbs_end; addr += 8) { - if (access_process_vm(child, addr, &val, sizeof(val), 0) + if (access_process_vm(child, addr, &val, sizeof(val), + FOLL_FORCE) != sizeof(val)) return -EIO; @@ -1156,7 +1159,8 @@ arch_ptrace (struct task_struct *child, long request, case PTRACE_PEEKTEXT: case PTRACE_PEEKDATA: /* read word at location addr */ - if (access_process_vm(child, addr, &data, sizeof(data), 0) + if (access_process_vm(child, addr, &data, sizeof(data), + FOLL_FORCE) != sizeof(data)) return -EIO; /* ensure return value is not mistaken for error code */ diff --git a/arch/m32r/kernel/ptrace.c b/arch/m32r/kernel/ptrace.c index 51f5e9aa4901..c145605a981f 100644 --- a/arch/m32r/kernel/ptrace.c +++ b/arch/m32r/kernel/ptrace.c @@ -493,7 +493,8 @@ unregister_all_debug_traps(struct task_struct *child) int i; for (i = 0; i < p->nr_trap; i++) - access_process_vm(child, p->addr[i], &p->insn[i], sizeof(p->insn[i]), 1); + access_process_vm(child, p->addr[i], &p->insn[i], sizeof(p->insn[i]), + FOLL_FORCE | FOLL_WRITE); p->nr_trap = 0; } @@ -537,7 +538,8 @@ embed_debug_trap(struct task_struct *child, unsigned long next_pc) unsigned long next_insn, code; unsigned long addr = next_pc & ~3; - if (access_process_vm(child, addr, &next_insn, sizeof(next_insn), 0) + if (access_process_vm(child, addr, &next_insn, sizeof(next_insn), + FOLL_FORCE) != sizeof(next_insn)) { return -1; /* error */ } @@ -546,7 +548,8 @@ embed_debug_trap(struct task_struct *child, unsigned long next_pc) if (register_debug_trap(child, next_pc, next_insn, &code)) { return -1; /* error */ } - if (access_process_vm(child, addr, &code, sizeof(code), 1) + if (access_process_vm(child, addr, &code, sizeof(code), + FOLL_FORCE | FOLL_WRITE) != sizeof(code)) { return -1; /* error */ } @@ -562,7 +565,8 @@ withdraw_debug_trap(struct pt_regs *regs) addr = (regs->bpc - 2) & ~3; regs->bpc -= 2; if (unregister_debug_trap(current, addr, &code)) { - access_process_vm(current, addr, &code, sizeof(code), 1); + access_process_vm(current, addr, &code, sizeof(code), + FOLL_FORCE | FOLL_WRITE); invalidate_cache(); } } @@ -589,7 +593,8 @@ void user_enable_single_step(struct task_struct *child) /* Compute next pc. */ pc = get_stack_long(child, PT_BPC); - if (access_process_vm(child, pc&~3, &insn, sizeof(insn), 0) + if (access_process_vm(child, pc&~3, &insn, sizeof(insn), + FOLL_FORCE) != sizeof(insn)) return; diff --git a/arch/mips/kernel/ptrace32.c b/arch/mips/kernel/ptrace32.c index 283b5a1967d1..7e71a4e0281b 100644 --- a/arch/mips/kernel/ptrace32.c +++ b/arch/mips/kernel/ptrace32.c @@ -70,7 +70,7 @@ long compat_arch_ptrace(struct task_struct *child, compat_long_t request, break; copied = access_process_vm(child, (u64)addrOthers, &tmp, - sizeof(tmp), 0); + sizeof(tmp), FOLL_FORCE); if (copied != sizeof(tmp)) break; ret = put_user(tmp, (u32 __user *) (unsigned long) data); @@ -179,7 +179,8 @@ long compat_arch_ptrace(struct task_struct *child, compat_long_t request, break; ret = 0; if (access_process_vm(child, (u64)addrOthers, &data, - sizeof(data), 1) == sizeof(data)) + sizeof(data), + FOLL_FORCE | FOLL_WRITE) == sizeof(data)) break; ret = -EIO; break; diff --git a/arch/mips/kvm/mips.c b/arch/mips/kvm/mips.c index ce961495b5e1..622037d851a3 100644 --- a/arch/mips/kvm/mips.c +++ b/arch/mips/kvm/mips.c @@ -14,6 +14,7 @@ #include <linux/err.h> #include <linux/kdebug.h> #include <linux/module.h> +#include <linux/uaccess.h> #include <linux/vmalloc.h> #include <linux/fs.h> #include <linux/bootmem.h> diff --git a/arch/mips/mm/gup.c b/arch/mips/mm/gup.c index 42d124fb6474..d8c3c159289a 100644 --- a/arch/mips/mm/gup.c +++ b/arch/mips/mm/gup.c @@ -287,7 +287,7 @@ slow_irqon: pages += nr; ret = get_user_pages_unlocked(start, (end - start) >> PAGE_SHIFT, - write, 0, pages); + pages, write ? FOLL_WRITE : 0); /* Have to be a bit careful with return values */ if (nr > 0) { diff --git a/arch/powerpc/boot/main.c b/arch/powerpc/boot/main.c index f7a184b6c35b..57d42d129033 100644 --- a/arch/powerpc/boot/main.c +++ b/arch/powerpc/boot/main.c @@ -32,9 +32,16 @@ static struct addr_range prep_kernel(void) void *addr = 0; struct elf_info ei; long len; + int uncompressed_image = 0; - partial_decompress(vmlinuz_addr, vmlinuz_size, + len = partial_decompress(vmlinuz_addr, vmlinuz_size, elfheader, sizeof(elfheader), 0); + /* assume uncompressed data if -1 is returned */ + if (len == -1) { + uncompressed_image = 1; + memcpy(elfheader, vmlinuz_addr, sizeof(elfheader)); + printf("No valid compressed data found, assume uncompressed data\n\r"); + } if (!parse_elf64(elfheader, &ei) && !parse_elf32(elfheader, &ei)) fatal("Error: not a valid PPC32 or PPC64 ELF file!\n\r"); @@ -67,6 +74,13 @@ static struct addr_range prep_kernel(void) "device tree\n\r"); } + if (uncompressed_image) { + memcpy(addr, vmlinuz_addr + ei.elfoffset, ei.loadsize); + printf("0x%lx bytes of uncompressed data copied\n\r", + ei.loadsize); + goto out; + } + /* Finally, decompress the kernel */ printf("Decompressing (0x%p <- 0x%p:0x%p)...\n\r", addr, vmlinuz_addr, vmlinuz_addr+vmlinuz_size); @@ -82,7 +96,7 @@ static struct addr_range prep_kernel(void) len, ei.loadsize); printf("Done! Decompressed 0x%lx bytes\n\r", len); - +out: flush_cache(addr, ei.loadsize); return (struct addr_range){addr, ei.memsize}; diff --git a/arch/powerpc/include/asm/cpuidle.h b/arch/powerpc/include/asm/cpuidle.h index 01b8a13f0224..3919332965af 100644 --- a/arch/powerpc/include/asm/cpuidle.h +++ b/arch/powerpc/include/asm/cpuidle.h @@ -26,7 +26,7 @@ extern u64 pnv_first_deep_stop_state; std r0,0(r1); \ ptesync; \ ld r0,0(r1); \ -1: cmp cr0,r0,r0; \ +1: cmpd cr0,r0,r0; \ bne 1b; \ IDLE_INST; \ b . diff --git a/arch/powerpc/include/asm/exception-64s.h b/arch/powerpc/include/asm/exception-64s.h index 2e4e7d878c8e..84d49b197c32 100644 --- a/arch/powerpc/include/asm/exception-64s.h +++ b/arch/powerpc/include/asm/exception-64s.h @@ -93,6 +93,10 @@ ld reg,PACAKBASE(r13); /* get high part of &label */ \ ori reg,reg,(FIXED_SYMBOL_ABS_ADDR(label))@l; +#define __LOAD_HANDLER(reg, label) \ + ld reg,PACAKBASE(r13); \ + ori reg,reg,(ABS_ADDR(label))@l; + /* Exception register prefixes */ #define EXC_HV H #define EXC_STD @@ -208,6 +212,18 @@ END_FTR_SECTION_NESTED(ftr,ftr,943) #define kvmppc_interrupt kvmppc_interrupt_pr #endif +#ifdef CONFIG_RELOCATABLE +#define BRANCH_TO_COMMON(reg, label) \ + __LOAD_HANDLER(reg, label); \ + mtctr reg; \ + bctr + +#else +#define BRANCH_TO_COMMON(reg, label) \ + b label + +#endif + #define __KVM_HANDLER_PROLOG(area, n) \ BEGIN_FTR_SECTION_NESTED(947) \ ld r10,area+EX_CFAR(r13); \ diff --git a/arch/powerpc/include/asm/tlb.h b/arch/powerpc/include/asm/tlb.h index f6f68f73e858..99e1397b71da 100644 --- a/arch/powerpc/include/asm/tlb.h +++ b/arch/powerpc/include/asm/tlb.h @@ -52,11 +52,23 @@ static inline int mm_is_core_local(struct mm_struct *mm) return cpumask_subset(mm_cpumask(mm), topology_sibling_cpumask(smp_processor_id())); } + +static inline int mm_is_thread_local(struct mm_struct *mm) +{ + return cpumask_equal(mm_cpumask(mm), + cpumask_of(smp_processor_id())); +} + #else static inline int mm_is_core_local(struct mm_struct *mm) { return 1; } + +static inline int mm_is_thread_local(struct mm_struct *mm) +{ + return 1; +} #endif #endif /* __KERNEL__ */ diff --git a/arch/powerpc/include/asm/unistd.h b/arch/powerpc/include/asm/unistd.h index cf12c580f6b2..e8cdfec8d512 100644 --- a/arch/powerpc/include/asm/unistd.h +++ b/arch/powerpc/include/asm/unistd.h @@ -16,6 +16,10 @@ #define __NR__exit __NR_exit +#define __IGNORE_pkey_mprotect +#define __IGNORE_pkey_alloc +#define __IGNORE_pkey_free + #ifndef __ASSEMBLY__ #include <linux/types.h> diff --git a/arch/powerpc/kernel/exceptions-64s.S b/arch/powerpc/kernel/exceptions-64s.S index f129408c6022..08ba447a4b3d 100644 --- a/arch/powerpc/kernel/exceptions-64s.S +++ b/arch/powerpc/kernel/exceptions-64s.S @@ -95,19 +95,35 @@ __start_interrupts: /* No virt vectors corresponding with 0x0..0x100 */ EXC_VIRT_NONE(0x4000, 0x4100) -EXC_REAL_BEGIN(system_reset, 0x100, 0x200) - SET_SCRATCH0(r13) + #ifdef CONFIG_PPC_P7_NAP -BEGIN_FTR_SECTION - /* Running native on arch 2.06 or later, check if we are - * waking up from nap/sleep/winkle. + /* + * If running native on arch 2.06 or later, check if we are waking up + * from nap/sleep/winkle, and branch to idle handler. */ - mfspr r13,SPRN_SRR1 - rlwinm. r13,r13,47-31,30,31 - beq 9f +#define IDLETEST(n) \ + BEGIN_FTR_SECTION ; \ + mfspr r10,SPRN_SRR1 ; \ + rlwinm. r10,r10,47-31,30,31 ; \ + beq- 1f ; \ + cmpwi cr3,r10,2 ; \ + BRANCH_TO_COMMON(r10, system_reset_idle_common) ; \ +1: \ + END_FTR_SECTION_IFSET(CPU_FTR_HVMODE | CPU_FTR_ARCH_206) +#else +#define IDLETEST NOTEST +#endif - cmpwi cr3,r13,2 - GET_PACA(r13) +EXC_REAL_BEGIN(system_reset, 0x100, 0x200) + SET_SCRATCH0(r13) + EXCEPTION_PROLOG_PSERIES(PACA_EXGEN, system_reset_common, EXC_STD, + IDLETEST, 0x100) + +EXC_REAL_END(system_reset, 0x100, 0x200) +EXC_VIRT_NONE(0x4100, 0x4200) + +#ifdef CONFIG_PPC_P7_NAP +EXC_COMMON_BEGIN(system_reset_idle_common) bl pnv_restore_hyp_resource li r0,PNV_THREAD_RUNNING @@ -130,14 +146,8 @@ BEGIN_FTR_SECTION blt cr3,2f b pnv_wakeup_loss 2: b pnv_wakeup_noloss +#endif -9: -END_FTR_SECTION_IFSET(CPU_FTR_HVMODE | CPU_FTR_ARCH_206) -#endif /* CONFIG_PPC_P7_NAP */ - EXCEPTION_PROLOG_PSERIES(PACA_EXGEN, system_reset_common, EXC_STD, - NOTEST, 0x100) -EXC_REAL_END(system_reset, 0x100, 0x200) -EXC_VIRT_NONE(0x4100, 0x4200) EXC_COMMON(system_reset_common, 0x100, system_reset_exception) #ifdef CONFIG_PPC_PSERIES @@ -817,10 +827,8 @@ EXC_VIRT(trap_0b, 0x4b00, 0x4c00, 0xb00) TRAMP_KVM(PACA_EXGEN, 0xb00) EXC_COMMON(trap_0b_common, 0xb00, unknown_exception) - -#define LOAD_SYSCALL_HANDLER(reg) \ - ld reg,PACAKBASE(r13); \ - ori reg,reg,(ABS_ADDR(system_call_common))@l; +#define LOAD_SYSCALL_HANDLER(reg) \ + __LOAD_HANDLER(reg, system_call_common) /* Syscall routine is used twice, in reloc-off and reloc-on paths */ #define SYSCALL_PSERIES_1 \ diff --git a/arch/powerpc/kernel/hw_breakpoint.c b/arch/powerpc/kernel/hw_breakpoint.c index 9781c69eae57..03d089b3ed72 100644 --- a/arch/powerpc/kernel/hw_breakpoint.c +++ b/arch/powerpc/kernel/hw_breakpoint.c @@ -275,7 +275,7 @@ int hw_breakpoint_handler(struct die_args *args) if (!stepped) { WARN(1, "Unable to handle hardware breakpoint. Breakpoint at " "0x%lx will be disabled.", info->address); - perf_event_disable(bp); + perf_event_disable_inatomic(bp); goto out; } /* diff --git a/arch/powerpc/kernel/idle_book3s.S b/arch/powerpc/kernel/idle_book3s.S index bd739fed26e3..72dac0b58061 100644 --- a/arch/powerpc/kernel/idle_book3s.S +++ b/arch/powerpc/kernel/idle_book3s.S @@ -90,6 +90,7 @@ ALT_FTR_SECTION_END_IFSET(CPU_FTR_ARCH_300) * Threads will spin in HMT_LOW until the lock bit is cleared. * r14 - pointer to core_idle_state * r15 - used to load contents of core_idle_state + * r9 - used as a temporary variable */ core_idle_lock_held: @@ -99,6 +100,8 @@ core_idle_lock_held: bne 3b HMT_MEDIUM lwarx r15,0,r14 + andi. r9,r15,PNV_CORE_IDLE_LOCK_BIT + bne core_idle_lock_held blr /* @@ -163,12 +166,6 @@ _GLOBAL(pnv_powersave_common) std r9,_MSR(r1) std r1,PACAR1(r13) -#ifdef CONFIG_KVM_BOOK3S_HV_POSSIBLE - /* Tell KVM we're entering idle */ - li r4,KVM_HWTHREAD_IN_IDLE - stb r4,HSTATE_HWTHREAD_STATE(r13) -#endif - /* * Go to real mode to do the nap, as required by the architecture. * Also, we need to be in real mode before setting hwthread_state, @@ -185,6 +182,26 @@ _GLOBAL(pnv_powersave_common) .globl pnv_enter_arch207_idle_mode pnv_enter_arch207_idle_mode: +#ifdef CONFIG_KVM_BOOK3S_HV_POSSIBLE + /* Tell KVM we're entering idle */ + li r4,KVM_HWTHREAD_IN_IDLE + /******************************************************/ + /* N O T E W E L L ! ! ! N O T E W E L L */ + /* The following store to HSTATE_HWTHREAD_STATE(r13) */ + /* MUST occur in real mode, i.e. with the MMU off, */ + /* and the MMU must stay off until we clear this flag */ + /* and test HSTATE_HWTHREAD_REQ(r13) in the system */ + /* reset interrupt vector in exceptions-64s.S. */ + /* The reason is that another thread can switch the */ + /* MMU to a guest context whenever this flag is set */ + /* to KVM_HWTHREAD_IN_IDLE, and if the MMU was on, */ + /* that would potentially cause this thread to start */ + /* executing instructions from guest memory in */ + /* hypervisor mode, leading to a host crash or data */ + /* corruption, or worse. */ + /******************************************************/ + stb r4,HSTATE_HWTHREAD_STATE(r13) +#endif stb r3,PACA_THREAD_IDLE_STATE(r13) cmpwi cr3,r3,PNV_THREAD_SLEEP bge cr3,2f @@ -250,6 +267,12 @@ enter_winkle: * r3 - requested stop state */ power_enter_stop: +#ifdef CONFIG_KVM_BOOK3S_HV_POSSIBLE + /* Tell KVM we're entering idle */ + li r4,KVM_HWTHREAD_IN_IDLE + /* DO THIS IN REAL MODE! See comment above. */ + stb r4,HSTATE_HWTHREAD_STATE(r13) +#endif /* * Check if the requested state is a deep idle state. */ diff --git a/arch/powerpc/kernel/process.c b/arch/powerpc/kernel/process.c index 9e7c10fe205f..ce6dc61b15b2 100644 --- a/arch/powerpc/kernel/process.c +++ b/arch/powerpc/kernel/process.c @@ -1012,7 +1012,7 @@ void restore_tm_state(struct pt_regs *regs) /* Ensure that restore_math() will restore */ if (msr_diff & MSR_FP) current->thread.load_fp = 1; -#ifdef CONFIG_ALIVEC +#ifdef CONFIG_ALTIVEC if (cpu_has_feature(CPU_FTR_ALTIVEC) && msr_diff & MSR_VEC) current->thread.load_vec = 1; #endif diff --git a/arch/powerpc/kernel/ptrace32.c b/arch/powerpc/kernel/ptrace32.c index f52b7db327c8..010b7b310237 100644 --- a/arch/powerpc/kernel/ptrace32.c +++ b/arch/powerpc/kernel/ptrace32.c @@ -74,7 +74,7 @@ long compat_arch_ptrace(struct task_struct *child, compat_long_t request, break; copied = access_process_vm(child, (u64)addrOthers, &tmp, - sizeof(tmp), 0); + sizeof(tmp), FOLL_FORCE); if (copied != sizeof(tmp)) break; ret = put_user(tmp, (u32 __user *)data); @@ -179,7 +179,8 @@ long compat_arch_ptrace(struct task_struct *child, compat_long_t request, break; ret = 0; if (access_process_vm(child, (u64)addrOthers, &tmp, - sizeof(tmp), 1) == sizeof(tmp)) + sizeof(tmp), + FOLL_FORCE | FOLL_WRITE) == sizeof(tmp)) break; ret = -EIO; break; diff --git a/arch/powerpc/kvm/book3s_hv_rm_xics.c b/arch/powerpc/kvm/book3s_hv_rm_xics.c index 82ff5de8b1e7..a0ea63ac2b52 100644 --- a/arch/powerpc/kvm/book3s_hv_rm_xics.c +++ b/arch/powerpc/kvm/book3s_hv_rm_xics.c @@ -23,6 +23,7 @@ #include <asm/ppc-opcode.h> #include <asm/pnv-pci.h> #include <asm/opal.h> +#include <asm/smp.h> #include "book3s_xics.h" diff --git a/arch/powerpc/mm/copro_fault.c b/arch/powerpc/mm/copro_fault.c index bb0354222b11..362954f98029 100644 --- a/arch/powerpc/mm/copro_fault.c +++ b/arch/powerpc/mm/copro_fault.c @@ -106,6 +106,8 @@ int copro_calculate_slb(struct mm_struct *mm, u64 ea, struct copro_slb *slb) switch (REGION_ID(ea)) { case USER_REGION_ID: pr_devel("%s: 0x%llx -- USER_REGION_ID\n", __func__, ea); + if (mm == NULL) + return 1; psize = get_slice_psize(mm, ea); ssize = user_segment_size(ea); vsid = get_vsid(mm->context.id, ea, ssize); diff --git a/arch/powerpc/mm/numa.c b/arch/powerpc/mm/numa.c index 75b9cd6150cc..a51c188b81f3 100644 --- a/arch/powerpc/mm/numa.c +++ b/arch/powerpc/mm/numa.c @@ -845,7 +845,7 @@ void __init dump_numa_cpu_topology(void) return; for_each_online_node(node) { - printk(KERN_DEBUG "Node %d CPUs:", node); + pr_info("Node %d CPUs:", node); count = 0; /* @@ -856,52 +856,18 @@ void __init dump_numa_cpu_topology(void) if (cpumask_test_cpu(cpu, node_to_cpumask_map[node])) { if (count == 0) - printk(" %u", cpu); + pr_cont(" %u", cpu); ++count; } else { if (count > 1) - printk("-%u", cpu - 1); + pr_cont("-%u", cpu - 1); count = 0; } } if (count > 1) - printk("-%u", nr_cpu_ids - 1); - printk("\n"); - } -} - -static void __init dump_numa_memory_topology(void) -{ - unsigned int node; - unsigned int count; - - if (min_common_depth == -1 || !numa_enabled) - return; - - for_each_online_node(node) { - unsigned long i; - - printk(KERN_DEBUG "Node %d Memory:", node); - - count = 0; - - for (i = 0; i < memblock_end_of_DRAM(); - i += (1 << SECTION_SIZE_BITS)) { - if (early_pfn_to_nid(i >> PAGE_SHIFT) == node) { - if (count == 0) - printk(" 0x%lx", i); - ++count; - } else { - if (count > 0) - printk("-0x%lx", i); - count = 0; - } - } - - if (count > 0) - printk("-0x%lx", i); - printk("\n"); + pr_cont("-%u", nr_cpu_ids - 1); + pr_cont("\n"); } } @@ -947,8 +913,6 @@ void __init initmem_init(void) if (parse_numa_properties()) setup_nonnuma(); - else - dump_numa_memory_topology(); memblock_dump_all(); diff --git a/arch/powerpc/mm/tlb-radix.c b/arch/powerpc/mm/tlb-radix.c index 0e49ec541ab5..bda8c43be78a 100644 --- a/arch/powerpc/mm/tlb-radix.c +++ b/arch/powerpc/mm/tlb-radix.c @@ -175,7 +175,7 @@ void radix__flush_tlb_mm(struct mm_struct *mm) if (unlikely(pid == MMU_NO_CONTEXT)) goto no_context; - if (!mm_is_core_local(mm)) { + if (!mm_is_thread_local(mm)) { int lock_tlbie = !mmu_has_feature(MMU_FTR_LOCKLESS_TLBIE); if (lock_tlbie) @@ -201,7 +201,7 @@ void radix__flush_tlb_pwc(struct mmu_gather *tlb, unsigned long addr) if (unlikely(pid == MMU_NO_CONTEXT)) goto no_context; - if (!mm_is_core_local(mm)) { + if (!mm_is_thread_local(mm)) { int lock_tlbie = !mmu_has_feature(MMU_FTR_LOCKLESS_TLBIE); if (lock_tlbie) @@ -226,7 +226,7 @@ void radix__flush_tlb_page_psize(struct mm_struct *mm, unsigned long vmaddr, pid = mm ? mm->context.id : 0; if (unlikely(pid == MMU_NO_CONTEXT)) goto bail; - if (!mm_is_core_local(mm)) { + if (!mm_is_thread_local(mm)) { int lock_tlbie = !mmu_has_feature(MMU_FTR_LOCKLESS_TLBIE); if (lock_tlbie) @@ -321,7 +321,7 @@ void radix__flush_tlb_range_psize(struct mm_struct *mm, unsigned long start, { unsigned long pid; unsigned long addr; - int local = mm_is_core_local(mm); + int local = mm_is_thread_local(mm); unsigned long ap = mmu_get_ap(psize); int lock_tlbie = !mmu_has_feature(MMU_FTR_LOCKLESS_TLBIE); unsigned long page_size = 1UL << mmu_psize_defs[psize].shift; diff --git a/arch/s390/include/asm/ftrace.h b/arch/s390/include/asm/ftrace.h index 64053d9ac3f2..836c56290499 100644 --- a/arch/s390/include/asm/ftrace.h +++ b/arch/s390/include/asm/ftrace.h @@ -12,9 +12,7 @@ #ifndef __ASSEMBLY__ -unsigned long return_address(int depth); - -#define ftrace_return_address(n) return_address(n) +#define ftrace_return_address(n) __builtin_return_address(n) void _mcount(void); void ftrace_caller(void); diff --git a/arch/s390/include/asm/processor.h b/arch/s390/include/asm/processor.h index 03323175de30..602af692efdc 100644 --- a/arch/s390/include/asm/processor.h +++ b/arch/s390/include/asm/processor.h @@ -192,7 +192,7 @@ struct task_struct; struct mm_struct; struct seq_file; -typedef int (*dump_trace_func_t)(void *data, unsigned long address); +typedef int (*dump_trace_func_t)(void *data, unsigned long address, int reliable); void dump_trace(dump_trace_func_t func, void *data, struct task_struct *task, unsigned long sp); diff --git a/arch/s390/include/asm/unistd.h b/arch/s390/include/asm/unistd.h index 02613bad8bbb..3066031a73fe 100644 --- a/arch/s390/include/asm/unistd.h +++ b/arch/s390/include/asm/unistd.h @@ -9,6 +9,9 @@ #include <uapi/asm/unistd.h> #define __IGNORE_time +#define __IGNORE_pkey_mprotect +#define __IGNORE_pkey_alloc +#define __IGNORE_pkey_free #define __ARCH_WANT_OLD_READDIR #define __ARCH_WANT_SYS_ALARM diff --git a/arch/s390/kernel/dis.c b/arch/s390/kernel/dis.c index 43446fa2a4e5..c74c59236f44 100644 --- a/arch/s390/kernel/dis.c +++ b/arch/s390/kernel/dis.c @@ -2014,12 +2014,12 @@ void show_code(struct pt_regs *regs) *ptr++ = '\t'; ptr += print_insn(ptr, code + start, addr); start += opsize; - printk("%s", buffer); + pr_cont("%s", buffer); ptr = buffer; ptr += sprintf(ptr, "\n "); hops++; } - printk("\n"); + pr_cont("\n"); } void print_fn_code(unsigned char *code, unsigned long len) diff --git a/arch/s390/kernel/dumpstack.c b/arch/s390/kernel/dumpstack.c index 6693383bc01b..55d4fe174fd9 100644 --- a/arch/s390/kernel/dumpstack.c +++ b/arch/s390/kernel/dumpstack.c @@ -38,10 +38,10 @@ __dump_trace(dump_trace_func_t func, void *data, unsigned long sp, if (sp < low || sp > high - sizeof(*sf)) return sp; sf = (struct stack_frame *) sp; + if (func(data, sf->gprs[8], 0)) + return sp; /* Follow the backchain. */ while (1) { - if (func(data, sf->gprs[8])) - return sp; low = sp; sp = sf->back_chain; if (!sp) @@ -49,6 +49,8 @@ __dump_trace(dump_trace_func_t func, void *data, unsigned long sp, if (sp <= low || sp > high - sizeof(*sf)) return sp; sf = (struct stack_frame *) sp; + if (func(data, sf->gprs[8], 1)) + return sp; } /* Zero backchain detected, check for interrupt frame. */ sp = (unsigned long) (sf + 1); @@ -56,7 +58,7 @@ __dump_trace(dump_trace_func_t func, void *data, unsigned long sp, return sp; regs = (struct pt_regs *) sp; if (!user_mode(regs)) { - if (func(data, regs->psw.addr)) + if (func(data, regs->psw.addr, 1)) return sp; } low = sp; @@ -85,33 +87,12 @@ void dump_trace(dump_trace_func_t func, void *data, struct task_struct *task, } EXPORT_SYMBOL_GPL(dump_trace); -struct return_address_data { - unsigned long address; - int depth; -}; - -static int __return_address(void *data, unsigned long address) -{ - struct return_address_data *rd = data; - - if (rd->depth--) - return 0; - rd->address = address; - return 1; -} - -unsigned long return_address(int depth) -{ - struct return_address_data rd = { .depth = depth + 2 }; - - dump_trace(__return_address, &rd, NULL, current_stack_pointer()); - return rd.address; -} -EXPORT_SYMBOL_GPL(return_address); - -static int show_address(void *data, unsigned long address) +static int show_address(void *data, unsigned long address, int reliable) { - printk("([<%016lx>] %pSR)\n", address, (void *)address); + if (reliable) + printk(" [<%016lx>] %pSR \n", address, (void *)address); + else + printk("([<%016lx>] %pSR)\n", address, (void *)address); return 0; } @@ -138,14 +119,14 @@ void show_stack(struct task_struct *task, unsigned long *sp) else stack = (unsigned long *)task->thread.ksp; } + printk(KERN_DEFAULT "Stack:\n"); for (i = 0; i < 20; i++) { if (((addr_t) stack & (THREAD_SIZE-1)) == 0) break; - if ((i * sizeof(long) % 32) == 0) - printk("%s ", i == 0 ? "" : "\n"); - printk("%016lx ", *stack++); + if (i % 4 == 0) + printk(KERN_DEFAULT " "); + pr_cont("%016lx%c", *stack++, i % 4 == 3 ? '\n' : ' '); } - printk("\n"); show_trace(task, (unsigned long)sp); } @@ -163,13 +144,13 @@ void show_registers(struct pt_regs *regs) mode = user_mode(regs) ? "User" : "Krnl"; printk("%s PSW : %p %p", mode, (void *)regs->psw.mask, (void *)regs->psw.addr); if (!user_mode(regs)) - printk(" (%pSR)", (void *)regs->psw.addr); - printk("\n"); + pr_cont(" (%pSR)", (void *)regs->psw.addr); + pr_cont("\n"); printk(" R:%x T:%x IO:%x EX:%x Key:%x M:%x W:%x " "P:%x AS:%x CC:%x PM:%x", psw->r, psw->t, psw->i, psw->e, psw->key, psw->m, psw->w, psw->p, psw->as, psw->cc, psw->pm); - printk(" RI:%x EA:%x", psw->ri, psw->eaba); - printk("\n%s GPRS: %016lx %016lx %016lx %016lx\n", mode, + pr_cont(" RI:%x EA:%x\n", psw->ri, psw->eaba); + printk("%s GPRS: %016lx %016lx %016lx %016lx\n", mode, regs->gprs[0], regs->gprs[1], regs->gprs[2], regs->gprs[3]); printk(" %016lx %016lx %016lx %016lx\n", regs->gprs[4], regs->gprs[5], regs->gprs[6], regs->gprs[7]); @@ -205,14 +186,14 @@ void die(struct pt_regs *regs, const char *str) printk("%s: %04x ilc:%d [#%d] ", str, regs->int_code & 0xffff, regs->int_code >> 17, ++die_counter); #ifdef CONFIG_PREEMPT - printk("PREEMPT "); + pr_cont("PREEMPT "); #endif #ifdef CONFIG_SMP - printk("SMP "); + pr_cont("SMP "); #endif if (debug_pagealloc_enabled()) - printk("DEBUG_PAGEALLOC"); - printk("\n"); + pr_cont("DEBUG_PAGEALLOC"); + pr_cont("\n"); notify_die(DIE_OOPS, str, regs, 0, regs->int_code & 0xffff, SIGSEGV); print_modules(); show_regs(regs); diff --git a/arch/s390/kernel/perf_event.c b/arch/s390/kernel/perf_event.c index 17431f63de00..955a7b6fa0a4 100644 --- a/arch/s390/kernel/perf_event.c +++ b/arch/s390/kernel/perf_event.c @@ -222,7 +222,7 @@ static int __init service_level_perf_register(void) } arch_initcall(service_level_perf_register); -static int __perf_callchain_kernel(void *data, unsigned long address) +static int __perf_callchain_kernel(void *data, unsigned long address, int reliable) { struct perf_callchain_entry_ctx *entry = data; diff --git a/arch/s390/kernel/stacktrace.c b/arch/s390/kernel/stacktrace.c index 44f84b23d4e5..355db9db8210 100644 --- a/arch/s390/kernel/stacktrace.c +++ b/arch/s390/kernel/stacktrace.c @@ -27,12 +27,12 @@ static int __save_address(void *data, unsigned long address, int nosched) return 1; } -static int save_address(void *data, unsigned long address) +static int save_address(void *data, unsigned long address, int reliable) { return __save_address(data, address, 0); } -static int save_address_nosched(void *data, unsigned long address) +static int save_address_nosched(void *data, unsigned long address, int reliable) { return __save_address(data, address, 1); } diff --git a/arch/s390/kvm/intercept.c b/arch/s390/kvm/intercept.c index 1cab8a177d0e..7a27eebab28a 100644 --- a/arch/s390/kvm/intercept.c +++ b/arch/s390/kvm/intercept.c @@ -119,8 +119,13 @@ static int handle_validity(struct kvm_vcpu *vcpu) vcpu->stat.exit_validity++; trace_kvm_s390_intercept_validity(vcpu, viwhy); - WARN_ONCE(true, "kvm: unhandled validity intercept 0x%x\n", viwhy); - return -EOPNOTSUPP; + KVM_EVENT(3, "validity intercept 0x%x for pid %u (kvm 0x%pK)", viwhy, + current->pid, vcpu->kvm); + + /* do not warn on invalid runtime instrumentation mode */ + WARN_ONCE(viwhy != 0x44, "kvm: unhandled validity intercept 0x%x\n", + viwhy); + return -EINVAL; } static int handle_instruction(struct kvm_vcpu *vcpu) diff --git a/arch/s390/mm/gup.c b/arch/s390/mm/gup.c index adb0c34bf431..18d4107e10ee 100644 --- a/arch/s390/mm/gup.c +++ b/arch/s390/mm/gup.c @@ -266,7 +266,8 @@ int get_user_pages_fast(unsigned long start, int nr_pages, int write, /* Try to get the remaining pages with get_user_pages */ start += nr << PAGE_SHIFT; pages += nr; - ret = get_user_pages_unlocked(start, nr_pages - nr, write, 0, pages); + ret = get_user_pages_unlocked(start, nr_pages - nr, pages, + write ? FOLL_WRITE : 0); /* Have to be a bit careful with return values */ if (nr > 0) ret = (ret < 0) ? nr : ret + nr; diff --git a/arch/s390/mm/hugetlbpage.c b/arch/s390/mm/hugetlbpage.c index cd404aa3931c..4a0c5bce3552 100644 --- a/arch/s390/mm/hugetlbpage.c +++ b/arch/s390/mm/hugetlbpage.c @@ -217,6 +217,7 @@ static __init int setup_hugepagesz(char *opt) } else if (MACHINE_HAS_EDAT2 && size == PUD_SIZE) { hugetlb_add_hstate(PUD_SHIFT - PAGE_SHIFT); } else { + hugetlb_bad_size(); pr_err("hugepagesz= specifies an unsupported page size %s\n", string); return 0; diff --git a/arch/s390/mm/init.c b/arch/s390/mm/init.c index f56a39bd8ba6..b3e9d18f2ec6 100644 --- a/arch/s390/mm/init.c +++ b/arch/s390/mm/init.c @@ -151,36 +151,40 @@ void __init free_initrd_mem(unsigned long start, unsigned long end) #ifdef CONFIG_MEMORY_HOTPLUG int arch_add_memory(int nid, u64 start, u64 size, bool for_device) { - unsigned long normal_end_pfn = PFN_DOWN(memblock_end_of_DRAM()); - unsigned long dma_end_pfn = PFN_DOWN(MAX_DMA_ADDRESS); + unsigned long zone_start_pfn, zone_end_pfn, nr_pages; unsigned long start_pfn = PFN_DOWN(start); unsigned long size_pages = PFN_DOWN(size); - unsigned long nr_pages; - int rc, zone_enum; + pg_data_t *pgdat = NODE_DATA(nid); + struct zone *zone; + int rc, i; rc = vmem_add_mapping(start, size); if (rc) return rc; - while (size_pages > 0) { - if (start_pfn < dma_end_pfn) { - nr_pages = (start_pfn + size_pages > dma_end_pfn) ? - dma_end_pfn - start_pfn : size_pages; - zone_enum = ZONE_DMA; - } else if (start_pfn < normal_end_pfn) { - nr_pages = (start_pfn + size_pages > normal_end_pfn) ? - normal_end_pfn - start_pfn : size_pages; - zone_enum = ZONE_NORMAL; + for (i = 0; i < MAX_NR_ZONES; i++) { + zone = pgdat->node_zones + i; + if (zone_idx(zone) != ZONE_MOVABLE) { + /* Add range within existing zone limits, if possible */ + zone_start_pfn = zone->zone_start_pfn; + zone_end_pfn = zone->zone_start_pfn + + zone->spanned_pages; } else { - nr_pages = size_pages; - zone_enum = ZONE_MOVABLE; + /* Add remaining range to ZONE_MOVABLE */ + zone_start_pfn = start_pfn; + zone_end_pfn = start_pfn + size_pages; } - rc = __add_pages(nid, NODE_DATA(nid)->node_zones + zone_enum, - start_pfn, size_pages); + if (start_pfn < zone_start_pfn || start_pfn >= zone_end_pfn) + continue; + nr_pages = (start_pfn + size_pages > zone_end_pfn) ? + zone_end_pfn - start_pfn : size_pages; + rc = __add_pages(nid, zone, start_pfn, nr_pages); if (rc) break; start_pfn += nr_pages; size_pages -= nr_pages; + if (!size_pages) + break; } if (rc) vmem_remove_mapping(start, size); diff --git a/arch/s390/oprofile/init.c b/arch/s390/oprofile/init.c index 16f4c3960b87..9a4de4599c7b 100644 --- a/arch/s390/oprofile/init.c +++ b/arch/s390/oprofile/init.c @@ -13,7 +13,7 @@ #include <linux/init.h> #include <asm/processor.h> -static int __s390_backtrace(void *data, unsigned long address) +static int __s390_backtrace(void *data, unsigned long address, int reliable) { unsigned int *depth = data; diff --git a/arch/score/kernel/ptrace.c b/arch/score/kernel/ptrace.c index 55836188b217..4f7314d5f334 100644 --- a/arch/score/kernel/ptrace.c +++ b/arch/score/kernel/ptrace.c @@ -131,7 +131,7 @@ read_tsk_long(struct task_struct *child, { int copied; - copied = access_process_vm(child, addr, res, sizeof(*res), 0); + copied = access_process_vm(child, addr, res, sizeof(*res), FOLL_FORCE); return copied != sizeof(*res) ? -EIO : 0; } @@ -142,7 +142,7 @@ read_tsk_short(struct task_struct *child, { int copied; - copied = access_process_vm(child, addr, res, sizeof(*res), 0); + copied = access_process_vm(child, addr, res, sizeof(*res), FOLL_FORCE); return copied != sizeof(*res) ? -EIO : 0; } @@ -153,7 +153,8 @@ write_tsk_short(struct task_struct *child, { int copied; - copied = access_process_vm(child, addr, &val, sizeof(val), 1); + copied = access_process_vm(child, addr, &val, sizeof(val), + FOLL_FORCE | FOLL_WRITE); return copied != sizeof(val) ? -EIO : 0; } @@ -164,7 +165,8 @@ write_tsk_long(struct task_struct *child, { int copied; - copied = access_process_vm(child, addr, &val, sizeof(val), 1); + copied = access_process_vm(child, addr, &val, sizeof(val), + FOLL_FORCE | FOLL_WRITE); return copied != sizeof(val) ? -EIO : 0; } diff --git a/arch/sh/Makefile b/arch/sh/Makefile index 00476662ac2c..336f33a419d9 100644 --- a/arch/sh/Makefile +++ b/arch/sh/Makefile @@ -31,7 +31,7 @@ isa-y := $(isa-y)-up endif cflags-$(CONFIG_CPU_SH2) := $(call cc-option,-m2,) -cflags-$(CONFIG_CPU_J2) := $(call cc-option,-mj2,) +cflags-$(CONFIG_CPU_J2) += $(call cc-option,-mj2,) cflags-$(CONFIG_CPU_SH2A) += $(call cc-option,-m2a,) \ $(call cc-option,-m2a-nofpu,) \ $(call cc-option,-m4-nofpu,) diff --git a/arch/sh/boards/Kconfig b/arch/sh/boards/Kconfig index e9c2c42031fe..4e21949593cf 100644 --- a/arch/sh/boards/Kconfig +++ b/arch/sh/boards/Kconfig @@ -22,6 +22,16 @@ config SH_DEVICE_TREE have sufficient driver coverage to use this option; do not select it if you are using original SuperH hardware. +config SH_JCORE_SOC + bool "J-Core SoC" + depends on SH_DEVICE_TREE && (CPU_SH2 || CPU_J2) + select CLKSRC_JCORE_PIT + select JCORE_AIC + default y if CPU_J2 + help + Select this option to include drivers core components of the + J-Core SoC, including interrupt controllers and timers. + config SH_SOLUTION_ENGINE bool "SolutionEngine" select SOLUTION_ENGINE diff --git a/arch/sh/configs/j2_defconfig b/arch/sh/configs/j2_defconfig index 94d1eca52f72..2eb81ebe3888 100644 --- a/arch/sh/configs/j2_defconfig +++ b/arch/sh/configs/j2_defconfig @@ -8,6 +8,7 @@ CONFIG_MEMORY_START=0x10000000 CONFIG_MEMORY_SIZE=0x04000000 CONFIG_CPU_BIG_ENDIAN=y CONFIG_SH_DEVICE_TREE=y +CONFIG_SH_JCORE_SOC=y CONFIG_HZ_100=y CONFIG_CMDLINE_OVERWRITE=y CONFIG_CMDLINE="console=ttyUL0 earlycon" @@ -20,6 +21,7 @@ CONFIG_INET=y CONFIG_DEVTMPFS=y CONFIG_DEVTMPFS_MOUNT=y CONFIG_NETDEVICES=y +CONFIG_SERIAL_EARLYCON=y CONFIG_SERIAL_UARTLITE=y CONFIG_SERIAL_UARTLITE_CONSOLE=y CONFIG_I2C=y diff --git a/arch/sh/mm/gup.c b/arch/sh/mm/gup.c index 40fa6c8adc43..063c298ba56c 100644 --- a/arch/sh/mm/gup.c +++ b/arch/sh/mm/gup.c @@ -258,7 +258,8 @@ slow_irqon: pages += nr; ret = get_user_pages_unlocked(start, - (end - start) >> PAGE_SHIFT, write, 0, pages); + (end - start) >> PAGE_SHIFT, pages, + write ? FOLL_WRITE : 0); /* Have to be a bit careful with return values */ if (nr > 0) { diff --git a/arch/sparc/kernel/ptrace_64.c b/arch/sparc/kernel/ptrace_64.c index 9ddc4928a089..ac082dd8c67d 100644 --- a/arch/sparc/kernel/ptrace_64.c +++ b/arch/sparc/kernel/ptrace_64.c @@ -127,7 +127,8 @@ static int get_from_target(struct task_struct *target, unsigned long uaddr, if (copy_from_user(kbuf, (void __user *) uaddr, len)) return -EFAULT; } else { - int len2 = access_process_vm(target, uaddr, kbuf, len, 0); + int len2 = access_process_vm(target, uaddr, kbuf, len, + FOLL_FORCE); if (len2 != len) return -EFAULT; } @@ -141,7 +142,8 @@ static int set_to_target(struct task_struct *target, unsigned long uaddr, if (copy_to_user((void __user *) uaddr, kbuf, len)) return -EFAULT; } else { - int len2 = access_process_vm(target, uaddr, kbuf, len, 1); + int len2 = access_process_vm(target, uaddr, kbuf, len, + FOLL_FORCE | FOLL_WRITE); if (len2 != len) return -EFAULT; } @@ -505,7 +507,8 @@ static int genregs32_get(struct task_struct *target, if (access_process_vm(target, (unsigned long) ®_window[pos], - k, sizeof(*k), 0) + k, sizeof(*k), + FOLL_FORCE) != sizeof(*k)) return -EFAULT; k++; @@ -531,12 +534,14 @@ static int genregs32_get(struct task_struct *target, if (access_process_vm(target, (unsigned long) ®_window[pos], - ®, sizeof(reg), 0) + ®, sizeof(reg), + FOLL_FORCE) != sizeof(reg)) return -EFAULT; if (access_process_vm(target, (unsigned long) u, - ®, sizeof(reg), 1) + ®, sizeof(reg), + FOLL_FORCE | FOLL_WRITE) != sizeof(reg)) return -EFAULT; pos++; @@ -615,7 +620,8 @@ static int genregs32_set(struct task_struct *target, (unsigned long) ®_window[pos], (void *) k, - sizeof(*k), 1) + sizeof(*k), + FOLL_FORCE | FOLL_WRITE) != sizeof(*k)) return -EFAULT; k++; @@ -642,13 +648,15 @@ static int genregs32_set(struct task_struct *target, if (access_process_vm(target, (unsigned long) u, - ®, sizeof(reg), 0) + ®, sizeof(reg), + FOLL_FORCE) != sizeof(reg)) return -EFAULT; if (access_process_vm(target, (unsigned long) ®_window[pos], - ®, sizeof(reg), 1) + ®, sizeof(reg), + FOLL_FORCE | FOLL_WRITE) != sizeof(reg)) return -EFAULT; pos++; diff --git a/arch/sparc/mm/gup.c b/arch/sparc/mm/gup.c index 4e06750a5d29..cd0e32bbcb1d 100644 --- a/arch/sparc/mm/gup.c +++ b/arch/sparc/mm/gup.c @@ -238,7 +238,8 @@ slow: pages += nr; ret = get_user_pages_unlocked(start, - (end - start) >> PAGE_SHIFT, write, 0, pages); + (end - start) >> PAGE_SHIFT, pages, + write ? FOLL_WRITE : 0); /* Have to be a bit careful with return values */ if (nr > 0) { diff --git a/arch/x86/entry/Makefile b/arch/x86/entry/Makefile index 77f28ce9c646..9976fcecd17e 100644 --- a/arch/x86/entry/Makefile +++ b/arch/x86/entry/Makefile @@ -5,8 +5,8 @@ OBJECT_FILES_NON_STANDARD_entry_$(BITS).o := y OBJECT_FILES_NON_STANDARD_entry_64_compat.o := y -CFLAGS_syscall_64.o += -Wno-override-init -CFLAGS_syscall_32.o += -Wno-override-init +CFLAGS_syscall_64.o += $(call cc-option,-Wno-override-init,) +CFLAGS_syscall_32.o += $(call cc-option,-Wno-override-init,) obj-y := entry_$(BITS).o thunk_$(BITS).o syscall_$(BITS).o obj-y += common.o diff --git a/arch/x86/entry/syscalls/syscall_32.tbl b/arch/x86/entry/syscalls/syscall_32.tbl index ff6ef7b30822..2b3618542544 100644 --- a/arch/x86/entry/syscalls/syscall_32.tbl +++ b/arch/x86/entry/syscalls/syscall_32.tbl @@ -389,5 +389,3 @@ 380 i386 pkey_mprotect sys_pkey_mprotect 381 i386 pkey_alloc sys_pkey_alloc 382 i386 pkey_free sys_pkey_free -#383 i386 pkey_get sys_pkey_get -#384 i386 pkey_set sys_pkey_set diff --git a/arch/x86/entry/syscalls/syscall_64.tbl b/arch/x86/entry/syscalls/syscall_64.tbl index 2f024d02511d..e93ef0b38db8 100644 --- a/arch/x86/entry/syscalls/syscall_64.tbl +++ b/arch/x86/entry/syscalls/syscall_64.tbl @@ -338,8 +338,6 @@ 329 common pkey_mprotect sys_pkey_mprotect 330 common pkey_alloc sys_pkey_alloc 331 common pkey_free sys_pkey_free -#332 common pkey_get sys_pkey_get -#333 common pkey_set sys_pkey_set # # x32-specific system call numbers start at 512 to avoid cache impact diff --git a/arch/x86/events/intel/core.c b/arch/x86/events/intel/core.c index a3a9eb84b5cf..a74a2dbc0180 100644 --- a/arch/x86/events/intel/core.c +++ b/arch/x86/events/intel/core.c @@ -3607,10 +3607,14 @@ __init int intel_pmu_init(void) /* * Quirk: v2 perfmon does not report fixed-purpose events, so - * assume at least 3 events: + * assume at least 3 events, when not running in a hypervisor: */ - if (version > 1) - x86_pmu.num_counters_fixed = max((int)edx.split.num_counters_fixed, 3); + if (version > 1) { + int assume = 3 * !boot_cpu_has(X86_FEATURE_HYPERVISOR); + + x86_pmu.num_counters_fixed = + max((int)edx.split.num_counters_fixed, assume); + } if (boot_cpu_has(X86_FEATURE_PDCM)) { u64 capabilities; @@ -3898,6 +3902,7 @@ __init int intel_pmu_init(void) break; case INTEL_FAM6_XEON_PHI_KNL: + case INTEL_FAM6_XEON_PHI_KNM: memcpy(hw_cache_event_ids, slm_hw_cache_event_ids, sizeof(hw_cache_event_ids)); memcpy(hw_cache_extra_regs, @@ -3912,7 +3917,7 @@ __init int intel_pmu_init(void) x86_pmu.flags |= PMU_FL_HAS_RSP_1; x86_pmu.flags |= PMU_FL_NO_HT_SHARING; - pr_cont("Knights Landing events, "); + pr_cont("Knights Landing/Mill events, "); break; case INTEL_FAM6_SKYLAKE_MOBILE: diff --git a/arch/x86/events/intel/cstate.c b/arch/x86/events/intel/cstate.c index 3ca87b5a8677..4f5ac726335f 100644 --- a/arch/x86/events/intel/cstate.c +++ b/arch/x86/events/intel/cstate.c @@ -48,7 +48,8 @@ * Scope: Core * MSR_CORE_C6_RESIDENCY: CORE C6 Residency Counter * perf code: 0x02 - * Available model: SLM,AMT,NHM,WSM,SNB,IVB,HSW,BDW,SKL + * Available model: SLM,AMT,NHM,WSM,SNB,IVB,HSW,BDW + * SKL,KNL * Scope: Core * MSR_CORE_C7_RESIDENCY: CORE C7 Residency Counter * perf code: 0x03 @@ -56,15 +57,16 @@ * Scope: Core * MSR_PKG_C2_RESIDENCY: Package C2 Residency Counter. * perf code: 0x00 - * Available model: SNB,IVB,HSW,BDW,SKL + * Available model: SNB,IVB,HSW,BDW,SKL,KNL * Scope: Package (physical package) * MSR_PKG_C3_RESIDENCY: Package C3 Residency Counter. * perf code: 0x01 - * Available model: NHM,WSM,SNB,IVB,HSW,BDW,SKL + * Available model: NHM,WSM,SNB,IVB,HSW,BDW,SKL,KNL * Scope: Package (physical package) * MSR_PKG_C6_RESIDENCY: Package C6 Residency Counter. * perf code: 0x02 - * Available model: SLM,AMT,NHM,WSM,SNB,IVB,HSW,BDW,SKL + * Available model: SLM,AMT,NHM,WSM,SNB,IVB,HSW,BDW + * SKL,KNL * Scope: Package (physical package) * MSR_PKG_C7_RESIDENCY: Package C7 Residency Counter. * perf code: 0x03 @@ -118,6 +120,7 @@ struct cstate_model { /* Quirk flags */ #define SLM_PKG_C6_USE_C7_MSR (1UL << 0) +#define KNL_CORE_C6_MSR (1UL << 1) struct perf_cstate_msr { u64 msr; @@ -488,6 +491,18 @@ static const struct cstate_model slm_cstates __initconst = { .quirks = SLM_PKG_C6_USE_C7_MSR, }; + +static const struct cstate_model knl_cstates __initconst = { + .core_events = BIT(PERF_CSTATE_CORE_C6_RES), + + .pkg_events = BIT(PERF_CSTATE_PKG_C2_RES) | + BIT(PERF_CSTATE_PKG_C3_RES) | + BIT(PERF_CSTATE_PKG_C6_RES), + .quirks = KNL_CORE_C6_MSR, +}; + + + #define X86_CSTATES_MODEL(model, states) \ { X86_VENDOR_INTEL, 6, model, X86_FEATURE_ANY, (unsigned long) &(states) } @@ -523,6 +538,8 @@ static const struct x86_cpu_id intel_cstates_match[] __initconst = { X86_CSTATES_MODEL(INTEL_FAM6_SKYLAKE_MOBILE, snb_cstates), X86_CSTATES_MODEL(INTEL_FAM6_SKYLAKE_DESKTOP, snb_cstates), + + X86_CSTATES_MODEL(INTEL_FAM6_XEON_PHI_KNL, knl_cstates), { }, }; MODULE_DEVICE_TABLE(x86cpu, intel_cstates_match); @@ -558,6 +575,11 @@ static int __init cstate_probe(const struct cstate_model *cm) if (cm->quirks & SLM_PKG_C6_USE_C7_MSR) pkg_msr[PERF_CSTATE_PKG_C6_RES].msr = MSR_PKG_C7_RESIDENCY; + /* KNL has different MSR for CORE C6 */ + if (cm->quirks & KNL_CORE_C6_MSR) + pkg_msr[PERF_CSTATE_CORE_C6_RES].msr = MSR_KNL_CORE_C6_RESIDENCY; + + has_cstate_core = cstate_probe_msr(cm->core_events, PERF_CSTATE_CORE_EVENT_MAX, core_msr, core_events_attrs); diff --git a/arch/x86/events/intel/lbr.c b/arch/x86/events/intel/lbr.c index fc6cf21c535e..81b321ace8e0 100644 --- a/arch/x86/events/intel/lbr.c +++ b/arch/x86/events/intel/lbr.c @@ -458,8 +458,8 @@ void intel_pmu_lbr_del(struct perf_event *event) if (!x86_pmu.lbr_nr) return; - if (branch_user_callstack(cpuc->br_sel) && event->ctx && - event->ctx->task_ctx_data) { + if (branch_user_callstack(cpuc->br_sel) && + event->ctx->task_ctx_data) { task_ctx = event->ctx->task_ctx_data; task_ctx->lbr_callstack_users--; } diff --git a/arch/x86/events/intel/rapl.c b/arch/x86/events/intel/rapl.c index b0f0e835a770..0a535cea8ff3 100644 --- a/arch/x86/events/intel/rapl.c +++ b/arch/x86/events/intel/rapl.c @@ -763,6 +763,7 @@ static const struct x86_cpu_id rapl_cpu_match[] __initconst = { X86_RAPL_MODEL_MATCH(INTEL_FAM6_BROADWELL_XEON_D, hsw_rapl_init), X86_RAPL_MODEL_MATCH(INTEL_FAM6_XEON_PHI_KNL, knl_rapl_init), + X86_RAPL_MODEL_MATCH(INTEL_FAM6_XEON_PHI_KNM, knl_rapl_init), X86_RAPL_MODEL_MATCH(INTEL_FAM6_SKYLAKE_MOBILE, skl_rapl_init), X86_RAPL_MODEL_MATCH(INTEL_FAM6_SKYLAKE_DESKTOP, skl_rapl_init), diff --git a/arch/x86/events/intel/uncore.c b/arch/x86/events/intel/uncore.c index d9844cc74486..efca2685d876 100644 --- a/arch/x86/events/intel/uncore.c +++ b/arch/x86/events/intel/uncore.c @@ -1349,6 +1349,7 @@ static const struct x86_cpu_id intel_uncore_match[] __initconst = { X86_UNCORE_MODEL_MATCH(INTEL_FAM6_BROADWELL_X, bdx_uncore_init), X86_UNCORE_MODEL_MATCH(INTEL_FAM6_BROADWELL_XEON_D, bdx_uncore_init), X86_UNCORE_MODEL_MATCH(INTEL_FAM6_XEON_PHI_KNL, knl_uncore_init), + X86_UNCORE_MODEL_MATCH(INTEL_FAM6_XEON_PHI_KNM, knl_uncore_init), X86_UNCORE_MODEL_MATCH(INTEL_FAM6_SKYLAKE_DESKTOP,skl_uncore_init), X86_UNCORE_MODEL_MATCH(INTEL_FAM6_SKYLAKE_MOBILE, skl_uncore_init), X86_UNCORE_MODEL_MATCH(INTEL_FAM6_SKYLAKE_X, skx_uncore_init), diff --git a/arch/x86/include/asm/cpufeatures.h b/arch/x86/include/asm/cpufeatures.h index 1188bc849ee3..a39629206864 100644 --- a/arch/x86/include/asm/cpufeatures.h +++ b/arch/x86/include/asm/cpufeatures.h @@ -194,6 +194,8 @@ #define X86_FEATURE_PROC_FEEDBACK ( 7*32+ 9) /* AMD ProcFeedbackInterface */ #define X86_FEATURE_INTEL_PT ( 7*32+15) /* Intel Processor Trace */ +#define X86_FEATURE_AVX512_4VNNIW (7*32+16) /* AVX-512 Neural Network Instructions */ +#define X86_FEATURE_AVX512_4FMAPS (7*32+17) /* AVX-512 Multiply Accumulation Single precision */ /* Virtualization flags: Linux defined, word 8 */ #define X86_FEATURE_TPR_SHADOW ( 8*32+ 0) /* Intel TPR Shadow */ diff --git a/arch/x86/include/asm/intel-family.h b/arch/x86/include/asm/intel-family.h index 9ae5ab80a497..34a46dc076d3 100644 --- a/arch/x86/include/asm/intel-family.h +++ b/arch/x86/include/asm/intel-family.h @@ -64,5 +64,6 @@ /* Xeon Phi */ #define INTEL_FAM6_XEON_PHI_KNL 0x57 /* Knights Landing */ +#define INTEL_FAM6_XEON_PHI_KNM 0x85 /* Knights Mill */ #endif /* _ASM_X86_INTEL_FAMILY_H */ diff --git a/arch/x86/include/asm/io.h b/arch/x86/include/asm/io.h index de25aad07853..d34bd370074b 100644 --- a/arch/x86/include/asm/io.h +++ b/arch/x86/include/asm/io.h @@ -351,4 +351,10 @@ extern void arch_phys_wc_del(int handle); #define arch_phys_wc_add arch_phys_wc_add #endif +#ifdef CONFIG_X86_PAT +extern int arch_io_reserve_memtype_wc(resource_size_t start, resource_size_t size); +extern void arch_io_free_memtype_wc(resource_size_t start, resource_size_t size); +#define arch_io_reserve_memtype_wc arch_io_reserve_memtype_wc +#endif + #endif /* _ASM_X86_IO_H */ diff --git a/arch/x86/include/asm/msr-index.h b/arch/x86/include/asm/msr-index.h index 56f4c6676b29..78f3760ca1f2 100644 --- a/arch/x86/include/asm/msr-index.h +++ b/arch/x86/include/asm/msr-index.h @@ -88,7 +88,6 @@ #define MSR_IA32_RTIT_CTL 0x00000570 #define MSR_IA32_RTIT_STATUS 0x00000571 -#define MSR_IA32_RTIT_STATUS 0x00000571 #define MSR_IA32_RTIT_ADDR0_A 0x00000580 #define MSR_IA32_RTIT_ADDR0_B 0x00000581 #define MSR_IA32_RTIT_ADDR1_A 0x00000582 diff --git a/arch/x86/include/asm/rwsem.h b/arch/x86/include/asm/rwsem.h index 3d33a719f5c1..a34e0d4b957d 100644 --- a/arch/x86/include/asm/rwsem.h +++ b/arch/x86/include/asm/rwsem.h @@ -103,8 +103,10 @@ static inline bool __down_read_trylock(struct rw_semaphore *sem) ({ \ long tmp; \ struct rw_semaphore* ret; \ + register void *__sp asm(_ASM_SP); \ + \ asm volatile("# beginning down_write\n\t" \ - LOCK_PREFIX " xadd %1,(%3)\n\t" \ + LOCK_PREFIX " xadd %1,(%4)\n\t" \ /* adds 0xffff0001, returns the old value */ \ " test " __ASM_SEL(%w1,%k1) "," __ASM_SEL(%w1,%k1) "\n\t" \ /* was the active mask 0 before? */\ @@ -112,7 +114,7 @@ static inline bool __down_read_trylock(struct rw_semaphore *sem) " call " slow_path "\n" \ "1:\n" \ "# ending down_write" \ - : "+m" (sem->count), "=d" (tmp), "=a" (ret) \ + : "+m" (sem->count), "=d" (tmp), "=a" (ret), "+r" (__sp) \ : "a" (sem), "1" (RWSEM_ACTIVE_WRITE_BIAS) \ : "memory", "cc"); \ ret; \ diff --git a/arch/x86/include/asm/thread_info.h b/arch/x86/include/asm/thread_info.h index 2aaca53c0974..ad6f5eb07a95 100644 --- a/arch/x86/include/asm/thread_info.h +++ b/arch/x86/include/asm/thread_info.h @@ -52,6 +52,15 @@ struct task_struct; #include <asm/cpufeature.h> #include <linux/atomic.h> +struct thread_info { + unsigned long flags; /* low level flags */ +}; + +#define INIT_THREAD_INFO(tsk) \ +{ \ + .flags = 0, \ +} + #define init_stack (init_thread_union.stack) #else /* !__ASSEMBLY__ */ diff --git a/arch/x86/kernel/acpi/boot.c b/arch/x86/kernel/acpi/boot.c index 8a5abaa7d453..931ced8ca345 100644 --- a/arch/x86/kernel/acpi/boot.c +++ b/arch/x86/kernel/acpi/boot.c @@ -454,6 +454,7 @@ static void __init acpi_sci_ioapic_setup(u8 bus_irq, u16 polarity, u16 trigger, polarity = acpi_sci_flags & ACPI_MADT_POLARITY_MASK; mp_override_legacy_irq(bus_irq, polarity, trigger, gsi); + acpi_penalize_sci_irq(bus_irq, trigger, polarity); /* * stash over-ride to indicate we've been here diff --git a/arch/x86/kernel/cpu/microcode/amd.c b/arch/x86/kernel/cpu/microcode/amd.c index 620ab06bcf45..017bda12caae 100644 --- a/arch/x86/kernel/cpu/microcode/amd.c +++ b/arch/x86/kernel/cpu/microcode/amd.c @@ -429,7 +429,7 @@ int __init save_microcode_in_initrd_amd(void) * We need the physical address of the container for both bitness since * boot_params.hdr.ramdisk_image is a physical address. */ - cont = __pa(container); + cont = __pa_nodebug(container); cont_va = container; #endif diff --git a/arch/x86/kernel/cpu/scattered.c b/arch/x86/kernel/cpu/scattered.c index 8cb57df9398d..1db8dc490b66 100644 --- a/arch/x86/kernel/cpu/scattered.c +++ b/arch/x86/kernel/cpu/scattered.c @@ -32,6 +32,8 @@ void init_scattered_cpuid_features(struct cpuinfo_x86 *c) static const struct cpuid_bit cpuid_bits[] = { { X86_FEATURE_INTEL_PT, CR_EBX,25, 0x00000007, 0 }, + { X86_FEATURE_AVX512_4VNNIW, CR_EDX, 2, 0x00000007, 0 }, + { X86_FEATURE_AVX512_4FMAPS, CR_EDX, 3, 0x00000007, 0 }, { X86_FEATURE_APERFMPERF, CR_ECX, 0, 0x00000006, 0 }, { X86_FEATURE_EPB, CR_ECX, 3, 0x00000006, 0 }, { X86_FEATURE_HW_PSTATE, CR_EDX, 7, 0x80000007, 0 }, diff --git a/arch/x86/kernel/cpu/vmware.c b/arch/x86/kernel/cpu/vmware.c index 81160578b91a..5130985b758b 100644 --- a/arch/x86/kernel/cpu/vmware.c +++ b/arch/x86/kernel/cpu/vmware.c @@ -27,6 +27,7 @@ #include <asm/div64.h> #include <asm/x86_init.h> #include <asm/hypervisor.h> +#include <asm/timer.h> #include <asm/apic.h> #define CPUID_VMWARE_INFO_LEAF 0x40000000 @@ -94,6 +95,10 @@ static void __init vmware_platform_setup(void) } else { pr_warn("Failed to get TSC freq from the hypervisor\n"); } + +#ifdef CONFIG_X86_IO_APIC + no_timer_check = 1; +#endif } /* diff --git a/arch/x86/kernel/e820.c b/arch/x86/kernel/e820.c index b85fe5f91c3f..90e8dde3ec26 100644 --- a/arch/x86/kernel/e820.c +++ b/arch/x86/kernel/e820.c @@ -350,7 +350,7 @@ int __init sanitize_e820_map(struct e820entry *biosmap, int max_nr_map, * continue building up new bios map based on this * information */ - if (current_type != last_type) { + if (current_type != last_type || current_type == E820_PRAM) { if (last_type != 0) { new_bios[new_bios_entry].size = change_point[chgidx]->addr - last_addr; diff --git a/arch/x86/kernel/fpu/xstate.c b/arch/x86/kernel/fpu/xstate.c index 124aa5c593f8..095ef7ddd6ae 100644 --- a/arch/x86/kernel/fpu/xstate.c +++ b/arch/x86/kernel/fpu/xstate.c @@ -74,6 +74,8 @@ void fpu__xstate_clear_all_cpu_caps(void) setup_clear_cpu_cap(X86_FEATURE_MPX); setup_clear_cpu_cap(X86_FEATURE_XGETBV1); setup_clear_cpu_cap(X86_FEATURE_PKU); + setup_clear_cpu_cap(X86_FEATURE_AVX512_4VNNIW); + setup_clear_cpu_cap(X86_FEATURE_AVX512_4FMAPS); } /* diff --git a/arch/x86/kernel/kprobes/core.c b/arch/x86/kernel/kprobes/core.c index 28cee019209c..d9d8d16b69db 100644 --- a/arch/x86/kernel/kprobes/core.c +++ b/arch/x86/kernel/kprobes/core.c @@ -50,6 +50,7 @@ #include <linux/kallsyms.h> #include <linux/ftrace.h> #include <linux/frame.h> +#include <linux/kasan.h> #include <asm/text-patching.h> #include <asm/cacheflush.h> @@ -1057,9 +1058,10 @@ int setjmp_pre_handler(struct kprobe *p, struct pt_regs *regs) * tailcall optimization. So, to be absolutely safe * we also save and restore enough stack bytes to cover * the argument area. + * Use __memcpy() to avoid KASAN stack out-of-bounds reports as we copy + * raw stack chunk with redzones: */ - memcpy(kcb->jprobes_stack, (kprobe_opcode_t *)addr, - MIN_STACK_SIZE(addr)); + __memcpy(kcb->jprobes_stack, (kprobe_opcode_t *)addr, MIN_STACK_SIZE(addr)); regs->flags &= ~X86_EFLAGS_IF; trace_hardirqs_off(); regs->ip = (unsigned long)(jp->entry); @@ -1080,6 +1082,9 @@ void jprobe_return(void) { struct kprobe_ctlblk *kcb = get_kprobe_ctlblk(); + /* Unpoison stack redzones in the frames we are going to jump over. */ + kasan_unpoison_stack_above_sp_to(kcb->jprobe_saved_sp); + asm volatile ( #ifdef CONFIG_X86_64 " xchg %%rbx,%%rsp \n" @@ -1118,7 +1123,7 @@ int longjmp_break_handler(struct kprobe *p, struct pt_regs *regs) /* It's OK to start function graph tracing again */ unpause_graph_tracing(); *regs = kcb->jprobe_saved_regs; - memcpy(saved_sp, kcb->jprobes_stack, MIN_STACK_SIZE(saved_sp)); + __memcpy(saved_sp, kcb->jprobes_stack, MIN_STACK_SIZE(saved_sp)); preempt_enable_no_resched(); return 1; } diff --git a/arch/x86/kernel/mcount_64.S b/arch/x86/kernel/mcount_64.S index efe73aacf966..7b0d3da52fb4 100644 --- a/arch/x86/kernel/mcount_64.S +++ b/arch/x86/kernel/mcount_64.S @@ -18,8 +18,10 @@ #ifdef CC_USING_FENTRY # define function_hook __fentry__ +EXPORT_SYMBOL(__fentry__) #else # define function_hook mcount +EXPORT_SYMBOL(mcount) #endif /* All cases save the original rbp (8 bytes) */ @@ -295,7 +297,6 @@ trace: jmp fgraph_trace END(function_hook) #endif /* CONFIG_DYNAMIC_FTRACE */ -EXPORT_SYMBOL(function_hook) #endif /* CONFIG_FUNCTION_TRACER */ #ifdef CONFIG_FUNCTION_GRAPH_TRACER diff --git a/arch/x86/kernel/quirks.c b/arch/x86/kernel/quirks.c index 51402a7e4ca6..0bee04d41bed 100644 --- a/arch/x86/kernel/quirks.c +++ b/arch/x86/kernel/quirks.c @@ -625,8 +625,6 @@ static void amd_disable_seq_and_redirect_scrub(struct pci_dev *dev) DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_16H_NB_F3, amd_disable_seq_and_redirect_scrub); -#endif - #if defined(CONFIG_X86_64) && defined(CONFIG_X86_MCE) #include <linux/jump_label.h> #include <asm/string_64.h> @@ -657,3 +655,4 @@ DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, 0x2fc0, quirk_intel_brickland_xeon_ DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, 0x6fc0, quirk_intel_brickland_xeon_ras_cap); DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, 0x2083, quirk_intel_purley_xeon_ras_cap); #endif +#endif diff --git a/arch/x86/kernel/setup.c b/arch/x86/kernel/setup.c index bbfbca5fea0c..9c337b0e8ba7 100644 --- a/arch/x86/kernel/setup.c +++ b/arch/x86/kernel/setup.c @@ -1221,11 +1221,16 @@ void __init setup_arch(char **cmdline_p) */ get_smp_config(); + /* + * Systems w/o ACPI and mptables might not have it mapped the local + * APIC yet, but prefill_possible_map() might need to access it. + */ + init_apic_mappings(); + prefill_possible_map(); init_cpu_to_node(); - init_apic_mappings(); io_apic_init_mappings(); kvm_guest_init(); diff --git a/arch/x86/kernel/signal_compat.c b/arch/x86/kernel/signal_compat.c index 40df33753bae..ec1f756f9dc9 100644 --- a/arch/x86/kernel/signal_compat.c +++ b/arch/x86/kernel/signal_compat.c @@ -105,9 +105,6 @@ void sigaction_compat_abi(struct k_sigaction *act, struct k_sigaction *oact) /* Don't let flags to be set from userspace */ act->sa.sa_flags &= ~(SA_IA32_ABI | SA_X32_ABI); - if (user_64bit_mode(current_pt_regs())) - return; - if (in_ia32_syscall()) act->sa.sa_flags |= SA_IA32_ABI; if (in_x32_syscall()) diff --git a/arch/x86/kernel/smp.c b/arch/x86/kernel/smp.c index 68f8cc222f25..c00cb64bc0a1 100644 --- a/arch/x86/kernel/smp.c +++ b/arch/x86/kernel/smp.c @@ -261,8 +261,10 @@ static inline void __smp_reschedule_interrupt(void) __visible void smp_reschedule_interrupt(struct pt_regs *regs) { + irq_enter(); ack_APIC_irq(); __smp_reschedule_interrupt(); + irq_exit(); /* * KVM uses this interrupt to force a cpu out of guest mode */ diff --git a/arch/x86/kernel/smpboot.c b/arch/x86/kernel/smpboot.c index 951f093a96fe..42f5eb7b4f6c 100644 --- a/arch/x86/kernel/smpboot.c +++ b/arch/x86/kernel/smpboot.c @@ -1409,15 +1409,17 @@ __init void prefill_possible_map(void) /* No boot processor was found in mptable or ACPI MADT */ if (!num_processors) { - int apicid = boot_cpu_physical_apicid; - int cpu = hard_smp_processor_id(); + if (boot_cpu_has(X86_FEATURE_APIC)) { + int apicid = boot_cpu_physical_apicid; + int cpu = hard_smp_processor_id(); - pr_warn("Boot CPU (id %d) not listed by BIOS\n", cpu); + pr_warn("Boot CPU (id %d) not listed by BIOS\n", cpu); - /* Make sure boot cpu is enumerated */ - if (apic->cpu_present_to_apicid(0) == BAD_APICID && - apic->apic_id_valid(apicid)) - generic_processor_info(apicid, boot_cpu_apic_version); + /* Make sure boot cpu is enumerated */ + if (apic->cpu_present_to_apicid(0) == BAD_APICID && + apic->apic_id_valid(apicid)) + generic_processor_info(apicid, boot_cpu_apic_version); + } if (!num_processors) num_processors = 1; diff --git a/arch/x86/kernel/step.c b/arch/x86/kernel/step.c index c9a073866ca7..a23ce84a3f6c 100644 --- a/arch/x86/kernel/step.c +++ b/arch/x86/kernel/step.c @@ -57,7 +57,8 @@ static int is_setting_trap_flag(struct task_struct *child, struct pt_regs *regs) unsigned char opcode[15]; unsigned long addr = convert_ip_to_linear(child, regs); - copied = access_process_vm(child, addr, opcode, sizeof(opcode), 0); + copied = access_process_vm(child, addr, opcode, sizeof(opcode), + FOLL_FORCE); for (i = 0; i < copied; i++) { switch (opcode[i]) { /* popf and iret */ diff --git a/arch/x86/kernel/unwind_guess.c b/arch/x86/kernel/unwind_guess.c index 9298993dc8b7..2d721e533cf4 100644 --- a/arch/x86/kernel/unwind_guess.c +++ b/arch/x86/kernel/unwind_guess.c @@ -47,7 +47,14 @@ void __unwind_start(struct unwind_state *state, struct task_struct *task, get_stack_info(first_frame, state->task, &state->stack_info, &state->stack_mask); - if (!__kernel_text_address(*first_frame)) + /* + * The caller can provide the address of the first frame directly + * (first_frame) or indirectly (regs->sp) to indicate which stack frame + * to start unwinding at. Skip ahead until we reach it. + */ + if (!unwind_done(state) && + (!on_stack(&state->stack_info, first_frame, sizeof(long)) || + !__kernel_text_address(*first_frame))) unwind_next_frame(state); } EXPORT_SYMBOL_GPL(__unwind_start); diff --git a/arch/x86/kvm/ioapic.c b/arch/x86/kvm/ioapic.c index c7220ba94aa7..1a22de70f7f7 100644 --- a/arch/x86/kvm/ioapic.c +++ b/arch/x86/kvm/ioapic.c @@ -594,7 +594,7 @@ static void kvm_ioapic_reset(struct kvm_ioapic *ioapic) ioapic->irr = 0; ioapic->irr_delivered = 0; ioapic->id = 0; - memset(ioapic->irq_eoi, 0x00, IOAPIC_NUM_PINS); + memset(ioapic->irq_eoi, 0x00, sizeof(ioapic->irq_eoi)); rtc_irq_eoi_tracking_reset(ioapic); } diff --git a/arch/x86/kvm/x86.c b/arch/x86/kvm/x86.c index 6c633de84dd7..e375235d81c9 100644 --- a/arch/x86/kvm/x86.c +++ b/arch/x86/kvm/x86.c @@ -5733,13 +5733,13 @@ static int kvmclock_cpu_online(unsigned int cpu) static void kvm_timer_init(void) { - int cpu; - max_tsc_khz = tsc_khz; if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC)) { #ifdef CONFIG_CPU_FREQ struct cpufreq_policy policy; + int cpu; + memset(&policy, 0, sizeof(policy)); cpu = get_cpu(); cpufreq_get_policy(&policy, cpu); diff --git a/arch/x86/mm/gup.c b/arch/x86/mm/gup.c index b8b6a60b32cf..0d4fb3ebbbac 100644 --- a/arch/x86/mm/gup.c +++ b/arch/x86/mm/gup.c @@ -435,7 +435,7 @@ slow_irqon: ret = get_user_pages_unlocked(start, (end - start) >> PAGE_SHIFT, - write, 0, pages); + pages, write ? FOLL_WRITE : 0); /* Have to be a bit careful with return values */ if (nr > 0) { diff --git a/arch/x86/mm/kaslr.c b/arch/x86/mm/kaslr.c index ddd2661c4502..887e57182716 100644 --- a/arch/x86/mm/kaslr.c +++ b/arch/x86/mm/kaslr.c @@ -104,10 +104,10 @@ void __init kernel_randomize_memory(void) * consistent with the vaddr_start/vaddr_end variables. */ BUILD_BUG_ON(vaddr_start >= vaddr_end); - BUILD_BUG_ON(config_enabled(CONFIG_X86_ESPFIX64) && + BUILD_BUG_ON(IS_ENABLED(CONFIG_X86_ESPFIX64) && vaddr_end >= EFI_VA_START); - BUILD_BUG_ON((config_enabled(CONFIG_X86_ESPFIX64) || - config_enabled(CONFIG_EFI)) && + BUILD_BUG_ON((IS_ENABLED(CONFIG_X86_ESPFIX64) || + IS_ENABLED(CONFIG_EFI)) && vaddr_end >= __START_KERNEL_map); BUILD_BUG_ON(vaddr_end > __START_KERNEL_map); diff --git a/arch/x86/mm/mpx.c b/arch/x86/mm/mpx.c index 80476878eb4c..e4f800999b32 100644 --- a/arch/x86/mm/mpx.c +++ b/arch/x86/mm/mpx.c @@ -544,10 +544,9 @@ static int mpx_resolve_fault(long __user *addr, int write) { long gup_ret; int nr_pages = 1; - int force = 0; - gup_ret = get_user_pages((unsigned long)addr, nr_pages, write, - force, NULL, NULL); + gup_ret = get_user_pages((unsigned long)addr, nr_pages, + write ? FOLL_WRITE : 0, NULL, NULL); /* * get_user_pages() returns number of pages gotten. * 0 means we failed to fault in and get anything, diff --git a/arch/x86/mm/pat.c b/arch/x86/mm/pat.c index 170cc4ff057b..83e701f160a9 100644 --- a/arch/x86/mm/pat.c +++ b/arch/x86/mm/pat.c @@ -730,6 +730,20 @@ void io_free_memtype(resource_size_t start, resource_size_t end) free_memtype(start, end); } +int arch_io_reserve_memtype_wc(resource_size_t start, resource_size_t size) +{ + enum page_cache_mode type = _PAGE_CACHE_MODE_WC; + + return io_reserve_memtype(start, start + size, &type); +} +EXPORT_SYMBOL(arch_io_reserve_memtype_wc); + +void arch_io_free_memtype_wc(resource_size_t start, resource_size_t size) +{ + io_free_memtype(start, start + size); +} +EXPORT_SYMBOL(arch_io_free_memtype_wc); + pgprot_t phys_mem_access_prot(struct file *file, unsigned long pfn, unsigned long size, pgprot_t vma_prot) { diff --git a/arch/x86/platform/uv/bios_uv.c b/arch/x86/platform/uv/bios_uv.c index b4d5e95fe4df..4a6a5a26c582 100644 --- a/arch/x86/platform/uv/bios_uv.c +++ b/arch/x86/platform/uv/bios_uv.c @@ -40,7 +40,15 @@ s64 uv_bios_call(enum uv_bios_cmd which, u64 a1, u64 a2, u64 a3, u64 a4, u64 a5) */ return BIOS_STATUS_UNIMPLEMENTED; - ret = efi_call_virt_pointer(tab, function, (u64)which, a1, a2, a3, a4, a5); + /* + * If EFI_OLD_MEMMAP is set, we need to fall back to using our old EFI + * callback method, which uses efi_call() directly, with the kernel page tables: + */ + if (unlikely(test_bit(EFI_OLD_MEMMAP, &efi.flags))) + ret = efi_call((void *)__va(tab->function), (u64)which, a1, a2, a3, a4, a5); + else + ret = efi_call_virt_pointer(tab, function, (u64)which, a1, a2, a3, a4, a5); + return ret; } EXPORT_SYMBOL_GPL(uv_bios_call); diff --git a/arch/x86/um/ptrace_32.c b/arch/x86/um/ptrace_32.c index 5766ead6fdb9..60a5a5a85505 100644 --- a/arch/x86/um/ptrace_32.c +++ b/arch/x86/um/ptrace_32.c @@ -36,7 +36,8 @@ int is_syscall(unsigned long addr) * slow, but that doesn't matter, since it will be called only * in case of singlestepping, if copy_from_user failed. */ - n = access_process_vm(current, addr, &instr, sizeof(instr), 0); + n = access_process_vm(current, addr, &instr, sizeof(instr), + FOLL_FORCE); if (n != sizeof(instr)) { printk(KERN_ERR "is_syscall : failed to read " "instruction from 0x%lx\n", addr); diff --git a/arch/x86/um/ptrace_64.c b/arch/x86/um/ptrace_64.c index 0b5c184dd5b3..e30202b1716e 100644 --- a/arch/x86/um/ptrace_64.c +++ b/arch/x86/um/ptrace_64.c @@ -212,7 +212,8 @@ int is_syscall(unsigned long addr) * slow, but that doesn't matter, since it will be called only * in case of singlestepping, if copy_from_user failed. */ - n = access_process_vm(current, addr, &instr, sizeof(instr), 0); + n = access_process_vm(current, addr, &instr, sizeof(instr), + FOLL_FORCE); if (n != sizeof(instr)) { printk("is_syscall : failed to read instruction from " "0x%lx\n", addr); diff --git a/arch/x86/xen/enlighten.c b/arch/x86/xen/enlighten.c index c0fdd57da7aa..bdd855685403 100644 --- a/arch/x86/xen/enlighten.c +++ b/arch/x86/xen/enlighten.c @@ -1837,6 +1837,7 @@ static void __init init_hvm_pv_info(void) xen_domain_type = XEN_HVM_DOMAIN; } +#endif static int xen_cpu_up_prepare(unsigned int cpu) { @@ -1887,6 +1888,7 @@ static int xen_cpu_up_online(unsigned int cpu) return 0; } +#ifdef CONFIG_XEN_PVHVM #ifdef CONFIG_KEXEC_CORE static void xen_hvm_shutdown(void) { |