diff options
Diffstat (limited to 'arch/m68k/include/asm')
31 files changed, 478 insertions, 306 deletions
diff --git a/arch/m68k/include/asm/atariints.h b/arch/m68k/include/asm/atariints.h index f597892e43a0..656bbbf5a6ff 100644 --- a/arch/m68k/include/asm/atariints.h +++ b/arch/m68k/include/asm/atariints.h @@ -146,7 +146,7 @@ static inline void clear_mfp_bit( unsigned irq, int type ) /* * {en,dis}able_irq have the usual semantics of temporary blocking the - * interrupt, but not loosing requests that happen between disabling and + * interrupt, but not losing requests that happen between disabling and * enabling. This is done with the MFP mask registers. */ diff --git a/arch/m68k/include/asm/atarikb.h b/arch/m68k/include/asm/atarikb.h index 546e7da5804f..68f3622bf591 100644 --- a/arch/m68k/include/asm/atarikb.h +++ b/arch/m68k/include/asm/atarikb.h @@ -34,8 +34,6 @@ void ikbd_joystick_disable(void); /* Hook for MIDI serial driver */ extern void (*atari_MIDI_interrupt_hook) (void); -/* Hook for mouse driver */ -extern void (*atari_mouse_interrupt_hook) (char *); /* Hook for keyboard inputdev driver */ extern void (*atari_input_keyboard_interrupt_hook) (unsigned char, char); /* Hook for mouse inputdev driver */ diff --git a/arch/m68k/include/asm/bitops_mm.h b/arch/m68k/include/asm/bitops_mm.h index b4ecdaada520..e9020f88a748 100644 --- a/arch/m68k/include/asm/bitops_mm.h +++ b/arch/m68k/include/asm/bitops_mm.h @@ -181,14 +181,15 @@ static inline int find_first_zero_bit(const unsigned long *vaddr, { const unsigned long *p = vaddr; int res = 32; + unsigned int words; unsigned long num; if (!size) return 0; - size = (size + 31) >> 5; + words = (size + 31) >> 5; while (!(num = ~*p++)) { - if (!--size) + if (!--words) goto out; } @@ -196,7 +197,8 @@ static inline int find_first_zero_bit(const unsigned long *vaddr, : "=d" (res) : "d" (num & -num)); res ^= 31; out: - return ((long)p - (long)vaddr - 4) * 8 + res; + res += ((long)p - (long)vaddr - 4) * 8; + return res < size ? res : size; } static inline int find_next_zero_bit(const unsigned long *vaddr, int size, @@ -215,27 +217,32 @@ static inline int find_next_zero_bit(const unsigned long *vaddr, int size, /* Look for zero in first longword */ __asm__ __volatile__ ("bfffo %1{#0,#0},%0" : "=d" (res) : "d" (num & -num)); - if (res < 32) - return offset + (res ^ 31); + if (res < 32) { + offset += res ^ 31; + return offset < size ? offset : size; + } offset += 32; + + if (offset >= size) + return size; } /* No zero yet, search remaining full bytes for a zero */ - res = find_first_zero_bit(p, size - ((long)p - (long)vaddr) * 8); - return offset + res; + return offset + find_first_zero_bit(p, size - offset); } static inline int find_first_bit(const unsigned long *vaddr, unsigned size) { const unsigned long *p = vaddr; int res = 32; + unsigned int words; unsigned long num; if (!size) return 0; - size = (size + 31) >> 5; + words = (size + 31) >> 5; while (!(num = *p++)) { - if (!--size) + if (!--words) goto out; } @@ -243,7 +250,8 @@ static inline int find_first_bit(const unsigned long *vaddr, unsigned size) : "=d" (res) : "d" (num & -num)); res ^= 31; out: - return ((long)p - (long)vaddr - 4) * 8 + res; + res += ((long)p - (long)vaddr - 4) * 8; + return res < size ? res : size; } static inline int find_next_bit(const unsigned long *vaddr, int size, @@ -262,13 +270,17 @@ static inline int find_next_bit(const unsigned long *vaddr, int size, /* Look for one in first longword */ __asm__ __volatile__ ("bfffo %1{#0,#0},%0" : "=d" (res) : "d" (num & -num)); - if (res < 32) - return offset + (res ^ 31); + if (res < 32) { + offset += res ^ 31; + return offset < size ? offset : size; + } offset += 32; + + if (offset >= size) + return size; } /* No one yet, search remaining full bytes for a one */ - res = find_first_bit(p, size - ((long)p - (long)vaddr) * 8); - return offset + res; + return offset + find_first_bit(p, size - offset); } /* @@ -325,142 +337,157 @@ static inline int __fls(int x) #include <asm-generic/bitops/hweight.h> #include <asm-generic/bitops/lock.h> -/* Bitmap functions for the minix filesystem */ +/* Bitmap functions for the little endian bitmap. */ -static inline int minix_find_first_zero_bit(const void *vaddr, unsigned size) +static inline void __set_bit_le(int nr, void *addr) { - const unsigned short *p = vaddr, *addr = vaddr; - int res; - unsigned short num; - - if (!size) - return 0; - - size = (size >> 4) + ((size & 15) > 0); - while (*p++ == 0xffff) - { - if (--size == 0) - return (p - addr) << 4; - } + __set_bit(nr ^ 24, addr); +} - num = ~*--p; - __asm__ __volatile__ ("bfffo %1{#16,#16},%0" - : "=d" (res) : "d" (num & -num)); - return ((p - addr) << 4) + (res ^ 31); +static inline void __clear_bit_le(int nr, void *addr) +{ + __clear_bit(nr ^ 24, addr); } -#define minix_test_and_set_bit(nr, addr) __test_and_set_bit((nr) ^ 16, (unsigned long *)(addr)) -#define minix_set_bit(nr,addr) __set_bit((nr) ^ 16, (unsigned long *)(addr)) -#define minix_test_and_clear_bit(nr, addr) __test_and_clear_bit((nr) ^ 16, (unsigned long *)(addr)) +static inline int __test_and_set_bit_le(int nr, void *addr) +{ + return __test_and_set_bit(nr ^ 24, addr); +} -static inline int minix_test_bit(int nr, const void *vaddr) +static inline int test_and_set_bit_le(int nr, void *addr) { - const unsigned short *p = vaddr; - return (p[nr >> 4] & (1U << (nr & 15))) != 0; + return test_and_set_bit(nr ^ 24, addr); } -/* Bitmap functions for the ext2 filesystem. */ +static inline int __test_and_clear_bit_le(int nr, void *addr) +{ + return __test_and_clear_bit(nr ^ 24, addr); +} -#define ext2_set_bit(nr, addr) __test_and_set_bit((nr) ^ 24, (unsigned long *)(addr)) -#define ext2_set_bit_atomic(lock, nr, addr) test_and_set_bit((nr) ^ 24, (unsigned long *)(addr)) -#define ext2_clear_bit(nr, addr) __test_and_clear_bit((nr) ^ 24, (unsigned long *)(addr)) -#define ext2_clear_bit_atomic(lock, nr, addr) test_and_clear_bit((nr) ^ 24, (unsigned long *)(addr)) -#define ext2_find_next_zero_bit(addr, size, offset) \ - generic_find_next_zero_le_bit((unsigned long *)addr, size, offset) -#define ext2_find_next_bit(addr, size, offset) \ - generic_find_next_le_bit((unsigned long *)addr, size, offset) +static inline int test_and_clear_bit_le(int nr, void *addr) +{ + return test_and_clear_bit(nr ^ 24, addr); +} -static inline int ext2_test_bit(int nr, const void *vaddr) +static inline int test_bit_le(int nr, const void *vaddr) { const unsigned char *p = vaddr; return (p[nr >> 3] & (1U << (nr & 7))) != 0; } -static inline int ext2_find_first_zero_bit(const void *vaddr, unsigned size) +static inline int find_first_zero_bit_le(const void *vaddr, unsigned size) { const unsigned long *p = vaddr, *addr = vaddr; - int res; + int res = 0; + unsigned int words; if (!size) return 0; - size = (size >> 5) + ((size & 31) > 0); - while (*p++ == ~0UL) - { - if (--size == 0) - return (p - addr) << 5; + words = (size >> 5) + ((size & 31) > 0); + while (*p++ == ~0UL) { + if (--words == 0) + goto out; } --p; for (res = 0; res < 32; res++) - if (!ext2_test_bit (res, p)) + if (!test_bit_le(res, p)) break; - return (p - addr) * 32 + res; +out: + res += (p - addr) * 32; + return res < size ? res : size; } -static inline unsigned long generic_find_next_zero_le_bit(const unsigned long *addr, +static inline unsigned long find_next_zero_bit_le(const void *addr, unsigned long size, unsigned long offset) { - const unsigned long *p = addr + (offset >> 5); + const unsigned long *p = addr; int bit = offset & 31UL, res; if (offset >= size) return size; + p += offset >> 5; + if (bit) { + offset -= bit; /* Look for zero in first longword */ for (res = bit; res < 32; res++) - if (!ext2_test_bit (res, p)) - return (p - addr) * 32 + res; + if (!test_bit_le(res, p)) { + offset += res; + return offset < size ? offset : size; + } p++; + offset += 32; + + if (offset >= size) + return size; } /* No zero yet, search remaining full bytes for a zero */ - res = ext2_find_first_zero_bit (p, size - 32 * (p - addr)); - return (p - addr) * 32 + res; + return offset + find_first_zero_bit_le(p, size - offset); } -static inline int ext2_find_first_bit(const void *vaddr, unsigned size) +static inline int find_first_bit_le(const void *vaddr, unsigned size) { const unsigned long *p = vaddr, *addr = vaddr; - int res; + int res = 0; + unsigned int words; if (!size) return 0; - size = (size >> 5) + ((size & 31) > 0); + words = (size >> 5) + ((size & 31) > 0); while (*p++ == 0UL) { - if (--size == 0) - return (p - addr) << 5; + if (--words == 0) + goto out; } --p; for (res = 0; res < 32; res++) - if (ext2_test_bit(res, p)) + if (test_bit_le(res, p)) break; - return (p - addr) * 32 + res; +out: + res += (p - addr) * 32; + return res < size ? res : size; } -static inline unsigned long generic_find_next_le_bit(const unsigned long *addr, +static inline unsigned long find_next_bit_le(const void *addr, unsigned long size, unsigned long offset) { - const unsigned long *p = addr + (offset >> 5); + const unsigned long *p = addr; int bit = offset & 31UL, res; if (offset >= size) return size; + p += offset >> 5; + if (bit) { + offset -= bit; /* Look for one in first longword */ for (res = bit; res < 32; res++) - if (ext2_test_bit(res, p)) - return (p - addr) * 32 + res; + if (test_bit_le(res, p)) { + offset += res; + return offset < size ? offset : size; + } p++; + offset += 32; + + if (offset >= size) + return size; } /* No set bit yet, search remaining full bytes for a set bit */ - res = ext2_find_first_bit(p, size - 32 * (p - addr)); - return (p - addr) * 32 + res; + return offset + find_first_bit_le(p, size - offset); } +/* Bitmap functions for the ext2 filesystem. */ + +#define ext2_set_bit_atomic(lock, nr, addr) \ + test_and_set_bit_le(nr, addr) +#define ext2_clear_bit_atomic(lock, nr, addr) \ + test_and_clear_bit_le(nr, addr) + #endif /* __KERNEL__ */ #endif /* _M68K_BITOPS_H */ diff --git a/arch/m68k/include/asm/bitops_no.h b/arch/m68k/include/asm/bitops_no.h index 9d3cbe5fad1e..7d3779fdc5b6 100644 --- a/arch/m68k/include/asm/bitops_no.h +++ b/arch/m68k/include/asm/bitops_no.h @@ -196,7 +196,19 @@ static __inline__ int __test_bit(int nr, const volatile unsigned long * addr) #include <asm-generic/bitops/hweight.h> #include <asm-generic/bitops/lock.h> -static __inline__ int ext2_set_bit(int nr, volatile void * addr) +#define BITOP_LE_SWIZZLE ((BITS_PER_LONG-1) & ~0x7) + +static inline void __set_bit_le(int nr, void *addr) +{ + __set_bit(nr ^ BITOP_LE_SWIZZLE, addr); +} + +static inline void __clear_bit_le(int nr, void *addr) +{ + __clear_bit(nr ^ BITOP_LE_SWIZZLE, addr); +} + +static inline int __test_and_set_bit_le(int nr, volatile void *addr) { char retval; @@ -215,7 +227,7 @@ static __inline__ int ext2_set_bit(int nr, volatile void * addr) return retval; } -static __inline__ int ext2_clear_bit(int nr, volatile void * addr) +static inline int __test_and_clear_bit_le(int nr, volatile void *addr) { char retval; @@ -238,7 +250,7 @@ static __inline__ int ext2_clear_bit(int nr, volatile void * addr) ({ \ int ret; \ spin_lock(lock); \ - ret = ext2_set_bit((nr), (addr)); \ + ret = __test_and_set_bit_le((nr), (addr)); \ spin_unlock(lock); \ ret; \ }) @@ -247,12 +259,12 @@ static __inline__ int ext2_clear_bit(int nr, volatile void * addr) ({ \ int ret; \ spin_lock(lock); \ - ret = ext2_clear_bit((nr), (addr)); \ + ret = __test_and_clear_bit_le((nr), (addr)); \ spin_unlock(lock); \ ret; \ }) -static __inline__ int ext2_test_bit(int nr, const volatile void * addr) +static inline int test_bit_le(int nr, const volatile void *addr) { char retval; @@ -271,10 +283,10 @@ static __inline__ int ext2_test_bit(int nr, const volatile void * addr) return retval; } -#define ext2_find_first_zero_bit(addr, size) \ - ext2_find_next_zero_bit((addr), (size), 0) +#define find_first_zero_bit_le(addr, size) \ + find_next_zero_bit_le((addr), (size), 0) -static __inline__ unsigned long ext2_find_next_zero_bit(void *addr, unsigned long size, unsigned long offset) +static inline unsigned long find_next_zero_bit_le(void *addr, unsigned long size, unsigned long offset) { unsigned long *p = ((unsigned long *) addr) + (offset >> 5); unsigned long result = offset & ~31UL; @@ -324,10 +336,6 @@ found_middle: return result + ffz(__swab32(tmp)); } -#define ext2_find_next_bit(addr, size, off) \ - generic_find_next_le_bit((unsigned long *)(addr), (size), (off)) -#include <asm-generic/bitops/minix.h> - #endif /* __KERNEL__ */ #include <asm-generic/bitops/fls.h> diff --git a/arch/m68k/include/asm/bootstd.h b/arch/m68k/include/asm/bootstd.h index bdc1a4ac4fe9..e518f5a575b7 100644 --- a/arch/m68k/include/asm/bootstd.h +++ b/arch/m68k/include/asm/bootstd.h @@ -31,7 +31,7 @@ #define __BN_flash_write_range 20 /* Calling conventions compatible to (uC)linux/68k - * We use simmilar macros to call into the bootloader as for uClinux + * We use similar macros to call into the bootloader as for uClinux */ #define __bsc_return(type, res) \ diff --git a/arch/m68k/include/asm/coldfire.h b/arch/m68k/include/asm/coldfire.h index 213028cbe110..c94557b91448 100644 --- a/arch/m68k/include/asm/coldfire.h +++ b/arch/m68k/include/asm/coldfire.h @@ -14,39 +14,35 @@ /* - * Define master clock frequency. This is essentially done at config - * time now. No point enumerating dozens of possible clock options - * here. Also the peripheral clock (bus clock) divide ratio is set - * at config time too. + * Define master clock frequency. This is done at config time now. + * No point enumerating dozens of possible clock options here. And + * in any case new boards come along from time to time that have yet + * another different clocking frequency. */ #ifdef CONFIG_CLOCK_SET #define MCF_CLK CONFIG_CLOCK_FREQ -#define MCF_BUSCLK (CONFIG_CLOCK_FREQ / CONFIG_CLOCK_DIV) #else #error "Don't know what your ColdFire CPU clock frequency is??" #endif /* - * Define the processor support peripherals base address. - * This is generally setup by the boards start up code. + * Define the processor internal peripherals base address. + * + * The majority of ColdFire parts use an MBAR register to set + * the base address. Some have an IPSBAR register instead, and it + * has slightly different rules on its size and alignment. Some + * parts have fixed addresses and the internal peripherals cannot + * be relocated in the CPU address space. + * + * The value of MBAR or IPSBAR is config time selectable, we no + * longer hard define it here. No MBAR or IPSBAR will be defined if + * this part has a fixed peripheral address map. */ -#define MCF_MBAR 0x10000000 -#define MCF_MBAR2 0x80000000 -#if defined(CONFIG_M54xx) -#define MCF_IPSBAR MCF_MBAR -#elif defined(CONFIG_M520x) -#define MCF_IPSBAR 0xFC000000 -#else -#define MCF_IPSBAR 0x40000000 +#ifdef CONFIG_MBAR +#define MCF_MBAR CONFIG_MBAR #endif - -#if defined(CONFIG_M523x) || defined(CONFIG_M527x) || defined(CONFIG_M528x) || \ - defined(CONFIG_M520x) -#undef MCF_MBAR -#define MCF_MBAR MCF_IPSBAR -#elif defined(CONFIG_M532x) -#undef MCF_MBAR -#define MCF_MBAR 0x00000000 +#ifdef CONFIG_IPSBAR +#define MCF_IPSBAR CONFIG_IPSBAR #endif /****************************************************************************/ diff --git a/arch/m68k/include/asm/commproc.h b/arch/m68k/include/asm/commproc.h index edf5eb6c08d2..a73998528d26 100644 --- a/arch/m68k/include/asm/commproc.h +++ b/arch/m68k/include/asm/commproc.h @@ -88,7 +88,7 @@ typedef struct cpm_buf_desc { /* rx bd status/control bits */ -#define BD_SC_EMPTY ((ushort)0x8000) /* Recieve is empty */ +#define BD_SC_EMPTY ((ushort)0x8000) /* Receive is empty */ #define BD_SC_WRAP ((ushort)0x2000) /* Last buffer descriptor in table */ #define BD_SC_INTRPT ((ushort)0x1000) /* Interrupt on change */ #define BD_SC_LAST ((ushort)0x0800) /* Last buffer in frame OR control char */ @@ -96,7 +96,7 @@ typedef struct cpm_buf_desc { #define BD_SC_FIRST ((ushort)0x0400) /* 1st buffer in an HDLC frame */ #define BD_SC_ADDR ((ushort)0x0400) /* 1st byte is a multidrop address */ -#define BD_SC_CM ((ushort)0x0200) /* Continous mode */ +#define BD_SC_CM ((ushort)0x0200) /* Continuous mode */ #define BD_SC_ID ((ushort)0x0100) /* Received too many idles */ #define BD_SC_AM ((ushort)0x0080) /* Multidrop address match */ diff --git a/arch/m68k/include/asm/delay_no.h b/arch/m68k/include/asm/delay_no.h index 55cbd6294ab6..c3a0edc90f21 100644 --- a/arch/m68k/include/asm/delay_no.h +++ b/arch/m68k/include/asm/delay_no.h @@ -16,7 +16,7 @@ static inline void __delay(unsigned long loops) * long word alignment which is the faster version. * The 0x4a8e is of course a 'tstl %fp' instruction. This is better * than using a NOP (0x4e71) instruction because it executes in one - * cycle not three and doesn't allow for an arbitary delay waiting + * cycle not three and doesn't allow for an arbitrary delay waiting * for bus cycles to finish. Also fp/a6 isn't likely to cause a * stall waiting for the register to become valid if such is added * to the coldfire at some stage. diff --git a/arch/m68k/include/asm/gpio.h b/arch/m68k/include/asm/gpio.h index c64c7b74cf86..b2046839f4b2 100644 --- a/arch/m68k/include/asm/gpio.h +++ b/arch/m68k/include/asm/gpio.h @@ -31,7 +31,7 @@ * GPIOs in a single control area, others have some GPIOs implemented in * different modules. * - * This implementation attempts accomodate the differences while presenting + * This implementation attempts accommodate the differences while presenting * a generic interface that will optimize to as few instructions as possible. */ #if defined(CONFIG_M5206) || defined(CONFIG_M5206e) || \ diff --git a/arch/m68k/include/asm/m5206sim.h b/arch/m68k/include/asm/m5206sim.h index 561b03b5ddf8..9015eadd5c00 100644 --- a/arch/m68k/include/asm/m5206sim.h +++ b/arch/m68k/include/asm/m5206sim.h @@ -14,6 +14,7 @@ #define CPU_NAME "COLDFIRE(m5206)" #define CPU_INSTR_PER_JIFFY 3 +#define MCF_BUSCLK MCF_CLK #include <asm/m52xxacr.h> @@ -48,14 +49,14 @@ #define MCFSIM_SWIVR 0x42 /* SW Watchdog intr reg (r/w) */ #define MCFSIM_SWSR 0x43 /* SW Watchdog service (r/w) */ -#define MCFSIM_DCRR 0x46 /* DRAM Refresh reg (r/w) */ -#define MCFSIM_DCTR 0x4a /* DRAM Timing reg (r/w) */ -#define MCFSIM_DAR0 0x4c /* DRAM 0 Address reg(r/w) */ -#define MCFSIM_DMR0 0x50 /* DRAM 0 Mask reg (r/w) */ -#define MCFSIM_DCR0 0x57 /* DRAM 0 Control reg (r/w) */ -#define MCFSIM_DAR1 0x58 /* DRAM 1 Address reg (r/w) */ -#define MCFSIM_DMR1 0x5c /* DRAM 1 Mask reg (r/w) */ -#define MCFSIM_DCR1 0x63 /* DRAM 1 Control reg (r/w) */ +#define MCFSIM_DCRR (MCF_MBAR + 0x46) /* DRAM Refresh reg (r/w) */ +#define MCFSIM_DCTR (MCF_MBAR + 0x4a) /* DRAM Timing reg (r/w) */ +#define MCFSIM_DAR0 (MCF_MBAR + 0x4c) /* DRAM 0 Address reg(r/w) */ +#define MCFSIM_DMR0 (MCF_MBAR + 0x50) /* DRAM 0 Mask reg (r/w) */ +#define MCFSIM_DCR0 (MCF_MBAR + 0x57) /* DRAM 0 Control reg (r/w) */ +#define MCFSIM_DAR1 (MCF_MBAR + 0x58) /* DRAM 1 Address reg (r/w) */ +#define MCFSIM_DMR1 (MCF_MBAR + 0x5c) /* DRAM 1 Mask reg (r/w) */ +#define MCFSIM_DCR1 (MCF_MBAR + 0x63) /* DRAM 1 Control reg (r/w) */ #define MCFSIM_CSAR0 0x64 /* CS 0 Address 0 reg (r/w) */ #define MCFSIM_CSMR0 0x68 /* CS 0 Mask 0 reg (r/w) */ @@ -89,9 +90,15 @@ #define MCFSIM_PAR 0xcb /* Pin Assignment reg (r/w) */ #endif +#define MCFTIMER_BASE1 (MCF_MBAR + 0x100) /* Base of TIMER1 */ +#define MCFTIMER_BASE2 (MCF_MBAR + 0x120) /* Base of TIMER2 */ + #define MCFSIM_PADDR (MCF_MBAR + 0x1c5) /* Parallel Direction (r/w) */ #define MCFSIM_PADAT (MCF_MBAR + 0x1c9) /* Parallel Port Value (r/w) */ +#define MCFDMA_BASE0 (MCF_MBAR + 0x200) /* Base address DMA 0 */ +#define MCFDMA_BASE1 (MCF_MBAR + 0x240) /* Base address DMA 1 */ + #if defined(CONFIG_NETtel) #define MCFUART_BASE1 0x180 /* Base address of UART1 */ #define MCFUART_BASE2 0x140 /* Base address of UART2 */ diff --git a/arch/m68k/include/asm/m520xsim.h b/arch/m68k/include/asm/m520xsim.h index 88ed8239fe4e..b6bf2c518bac 100644 --- a/arch/m68k/include/asm/m520xsim.h +++ b/arch/m68k/include/asm/m520xsim.h @@ -13,13 +13,14 @@ #define CPU_NAME "COLDFIRE(m520x)" #define CPU_INSTR_PER_JIFFY 3 +#define MCF_BUSCLK (MCF_CLK / 2) #include <asm/m52xxacr.h> /* * Define the 520x SIM register set addresses. */ -#define MCFICM_INTC0 0x48000 /* Base for Interrupt Ctrl 0 */ +#define MCFICM_INTC0 0xFC048000 /* Base for Interrupt Ctrl 0 */ #define MCFINTC_IPRH 0x00 /* Interrupt pending 32-63 */ #define MCFINTC_IPRL 0x04 /* Interrupt pending 1-31 */ #define MCFINTC_IMRH 0x08 /* Interrupt mask 32-63 */ @@ -35,9 +36,9 @@ * address to the SIMR and CIMR registers (not offsets into IPSBAR). * The 520x family only has a single INTC unit. */ -#define MCFINTC0_SIMR (MCF_IPSBAR + MCFICM_INTC0 + MCFINTC_SIMR) -#define MCFINTC0_CIMR (MCF_IPSBAR + MCFICM_INTC0 + MCFINTC_CIMR) -#define MCFINTC0_ICR0 (MCF_IPSBAR + MCFICM_INTC0 + MCFINTC_ICR0) +#define MCFINTC0_SIMR (MCFICM_INTC0 + MCFINTC_SIMR) +#define MCFINTC0_CIMR (MCFICM_INTC0 + MCFINTC_CIMR) +#define MCFINTC0_ICR0 (MCFICM_INTC0 + MCFINTC_ICR0) #define MCFINTC1_SIMR (0) #define MCFINTC1_CIMR (0) #define MCFINTC1_ICR0 (0) @@ -52,19 +53,22 @@ /* * SDRAM configuration registers. */ -#define MCFSIM_SDMR 0x000a8000 /* SDRAM Mode/Extended Mode Register */ -#define MCFSIM_SDCR 0x000a8004 /* SDRAM Control Register */ -#define MCFSIM_SDCFG1 0x000a8008 /* SDRAM Configuration Register 1 */ -#define MCFSIM_SDCFG2 0x000a800c /* SDRAM Configuration Register 2 */ -#define MCFSIM_SDCS0 0x000a8110 /* SDRAM Chip Select 0 Configuration */ -#define MCFSIM_SDCS1 0x000a8114 /* SDRAM Chip Select 1 Configuration */ +#define MCFSIM_SDMR 0xFC0a8000 /* SDRAM Mode/Extended Mode Register */ +#define MCFSIM_SDCR 0xFC0a8004 /* SDRAM Control Register */ +#define MCFSIM_SDCFG1 0xFC0a8008 /* SDRAM Configuration Register 1 */ +#define MCFSIM_SDCFG2 0xFC0a800c /* SDRAM Configuration Register 2 */ +#define MCFSIM_SDCS0 0xFC0a8110 /* SDRAM Chip Select 0 Configuration */ +#define MCFSIM_SDCS1 0xFC0a8114 /* SDRAM Chip Select 1 Configuration */ /* * EPORT and GPIO registers. */ +#define MCFEPORT_EPPAR 0xFC088000 #define MCFEPORT_EPDDR 0xFC088002 +#define MCFEPORT_EPIER 0xFC088003 #define MCFEPORT_EPDR 0xFC088004 #define MCFEPORT_EPPDR 0xFC088005 +#define MCFEPORT_EPFR 0xFC088006 #define MCFGPIO_PODR_BUSCTL 0xFC0A4000 #define MCFGPIO_PODR_BE 0xFC0A4001 @@ -119,10 +123,10 @@ #define MCFGPIO_IRQ_MAX 8 #define MCFGPIO_IRQ_VECBASE MCFINT_VECBASE -#define MCF_GPIO_PAR_UART (0xA4036) -#define MCF_GPIO_PAR_FECI2C (0xA4033) -#define MCF_GPIO_PAR_QSPI (0xA4034) -#define MCF_GPIO_PAR_FEC (0xA4038) +#define MCF_GPIO_PAR_UART 0xFC0A4036 +#define MCF_GPIO_PAR_FECI2C 0xFC0A4033 +#define MCF_GPIO_PAR_QSPI 0xFC0A4034 +#define MCF_GPIO_PAR_FEC 0xFC0A4038 #define MCF_GPIO_PAR_UART_PAR_URXD0 (0x0001) #define MCF_GPIO_PAR_UART_PAR_UTXD0 (0x0002) @@ -134,14 +138,26 @@ #define MCF_GPIO_PAR_FECI2C_PAR_SCL_UTXD2 (0x04) /* + * PIT timer module. + */ +#define MCFPIT_BASE1 0xFC080000 /* Base address of TIMER1 */ +#define MCFPIT_BASE2 0xFC084000 /* Base address of TIMER2 */ + +/* * UART module. */ -#define MCFUART_BASE1 0x60000 /* Base address of UART1 */ -#define MCFUART_BASE2 0x64000 /* Base address of UART2 */ -#define MCFUART_BASE3 0x68000 /* Base address of UART2 */ +#define MCFUART_BASE1 0xFC060000 /* Base address of UART1 */ +#define MCFUART_BASE2 0xFC064000 /* Base address of UART2 */ +#define MCFUART_BASE3 0xFC068000 /* Base address of UART2 */ + +/* + * FEC module. + */ +#define MCFFEC_BASE 0xFC030000 /* Base of FEC ethernet */ +#define MCFFEC_SIZE 0x800 /* Register set size */ /* - * Reset Controll Unit. + * Reset Control Unit. */ #define MCF_RCR 0xFC0A0000 #define MCF_RSR 0xFC0A0001 diff --git a/arch/m68k/include/asm/m523xsim.h b/arch/m68k/include/asm/m523xsim.h index 4ad7a00257a8..6235921eca4e 100644 --- a/arch/m68k/include/asm/m523xsim.h +++ b/arch/m68k/include/asm/m523xsim.h @@ -13,14 +13,16 @@ #define CPU_NAME "COLDFIRE(m523x)" #define CPU_INSTR_PER_JIFFY 3 +#define MCF_BUSCLK (MCF_CLK / 2) #include <asm/m52xxacr.h> /* * Define the 523x SIM register set addresses. */ -#define MCFICM_INTC0 0x0c00 /* Base for Interrupt Ctrl 0 */ -#define MCFICM_INTC1 0x0d00 /* Base for Interrupt Ctrl 0 */ +#define MCFICM_INTC0 (MCF_IPSBAR + 0x0c00) /* Base for Interrupt Ctrl 0 */ +#define MCFICM_INTC1 (MCF_IPSBAR + 0x0d00) /* Base for Interrupt Ctrl 0 */ + #define MCFINTC_IPRH 0x00 /* Interrupt pending 32-63 */ #define MCFINTC_IPRL 0x04 /* Interrupt pending 1-31 */ #define MCFINTC_IMRH 0x08 /* Interrupt mask 32-63 */ @@ -39,14 +41,14 @@ /* * SDRAM configuration registers. */ -#define MCFSIM_DCR 0x44 /* SDRAM control */ -#define MCFSIM_DACR0 0x48 /* SDRAM base address 0 */ -#define MCFSIM_DMR0 0x4c /* SDRAM address mask 0 */ -#define MCFSIM_DACR1 0x50 /* SDRAM base address 1 */ -#define MCFSIM_DMR1 0x54 /* SDRAM address mask 1 */ +#define MCFSIM_DCR (MCF_IPSBAR + 0x44) /* Control */ +#define MCFSIM_DACR0 (MCF_IPSBAR + 0x48) /* Base address 0 */ +#define MCFSIM_DMR0 (MCF_IPSBAR + 0x4c) /* Address mask 0 */ +#define MCFSIM_DACR1 (MCF_IPSBAR + 0x50) /* Base address 1 */ +#define MCFSIM_DMR1 (MCF_IPSBAR + 0x54) /* Address mask 1 */ /* - * Reset Controll Unit (relative to IPSBAR). + * Reset Control Unit (relative to IPSBAR). */ #define MCF_RCR 0x110000 #define MCF_RSR 0x110001 @@ -57,10 +59,19 @@ /* * UART module. */ -#define MCFUART_BASE1 0x200 /* Base address of UART1 */ -#define MCFUART_BASE2 0x240 /* Base address of UART2 */ -#define MCFUART_BASE3 0x280 /* Base address of UART3 */ +#define MCFUART_BASE1 (MCF_IPSBAR + 0x200) +#define MCFUART_BASE2 (MCF_IPSBAR + 0x240) +#define MCFUART_BASE3 (MCF_IPSBAR + 0x280) + +/* + * FEC ethernet module. + */ +#define MCFFEC_BASE (MCF_IPSBAR + 0x1000) +#define MCFFEC_SIZE 0x800 +/* + * GPIO module. + */ #define MCFGPIO_PODR_ADDR (MCF_IPSBAR + 0x100000) #define MCFGPIO_PODR_DATAH (MCF_IPSBAR + 0x100001) #define MCFGPIO_PODR_DATAL (MCF_IPSBAR + 0x100002) @@ -118,12 +129,22 @@ #define MCFGPIO_PCLRR_ETPU (MCF_IPSBAR + 0x10003C) /* - * EPort + * PIT timer base addresses. */ +#define MCFPIT_BASE1 (MCF_IPSBAR + 0x150000) +#define MCFPIT_BASE2 (MCF_IPSBAR + 0x160000) +#define MCFPIT_BASE3 (MCF_IPSBAR + 0x170000) +#define MCFPIT_BASE4 (MCF_IPSBAR + 0x180000) +/* + * EPort + */ +#define MCFEPORT_EPPAR (MCF_IPSBAR + 0x130000) #define MCFEPORT_EPDDR (MCF_IPSBAR + 0x130002) +#define MCFEPORT_EPIER (MCF_IPSBAR + 0x130003) #define MCFEPORT_EPDR (MCF_IPSBAR + 0x130004) #define MCFEPORT_EPPDR (MCF_IPSBAR + 0x130005) +#define MCFEPORT_EPFR (MCF_IPSBAR + 0x130006) /* * Generic GPIO support @@ -143,5 +164,14 @@ */ #define MCFGPIO_PAR_QSPI (MCF_IPSBAR + 0x10004A) #define MCFGPIO_PAR_TIMER (MCF_IPSBAR + 0x10004C) + +/* + * DMA unit base addresses. + */ +#define MCFDMA_BASE0 (MCF_IPSBAR + 0x100) +#define MCFDMA_BASE1 (MCF_IPSBAR + 0x140) +#define MCFDMA_BASE2 (MCF_IPSBAR + 0x180) +#define MCFDMA_BASE3 (MCF_IPSBAR + 0x1C0) + /****************************************************************************/ #endif /* m523xsim_h */ diff --git a/arch/m68k/include/asm/m5249sim.h b/arch/m68k/include/asm/m5249sim.h index 4908b118f2fd..805714ca8d7d 100644 --- a/arch/m68k/include/asm/m5249sim.h +++ b/arch/m68k/include/asm/m5249sim.h @@ -13,10 +13,16 @@ #define CPU_NAME "COLDFIRE(m5249)" #define CPU_INSTR_PER_JIFFY 3 +#define MCF_BUSCLK (MCF_CLK / 2) #include <asm/m52xxacr.h> /* + * The 5249 has a second MBAR region, define its address. + */ +#define MCF_MBAR2 0x80000000 + +/* * Define the 5249 SIM register set addresses. */ #define MCFSIM_RSR 0x00 /* Reset Status reg (r/w) */ @@ -55,11 +61,17 @@ #define MCFSIM_CSMR3 0xa8 /* CS 3 Mask reg (r/w) */ #define MCFSIM_CSCR3 0xae /* CS 3 Control reg (r/w) */ -#define MCFSIM_DCR 0x100 /* DRAM Control reg (r/w) */ -#define MCFSIM_DACR0 0x108 /* DRAM 0 Addr and Ctrl (r/w) */ -#define MCFSIM_DMR0 0x10c /* DRAM 0 Mask reg (r/w) */ -#define MCFSIM_DACR1 0x110 /* DRAM 1 Addr and Ctrl (r/w) */ -#define MCFSIM_DMR1 0x114 /* DRAM 1 Mask reg (r/w) */ +#define MCFSIM_DCR (MCF_MBAR + 0x100) /* DRAM Control */ +#define MCFSIM_DACR0 (MCF_MBAR + 0x108) /* DRAM 0 Addr/Ctrl */ +#define MCFSIM_DMR0 (MCF_MBAR + 0x10c) /* DRAM 0 Mask */ +#define MCFSIM_DACR1 (MCF_MBAR + 0x110) /* DRAM 1 Addr/Ctrl */ +#define MCFSIM_DMR1 (MCF_MBAR + 0x114) /* DRAM 1 Mask */ + +/* + * Timer module. + */ +#define MCFTIMER_BASE1 (MCF_MBAR + 0x140) /* Base of TIMER1 */ +#define MCFTIMER_BASE2 (MCF_MBAR + 0x180) /* Base of TIMER2 */ /* * UART module. @@ -68,6 +80,14 @@ #define MCFUART_BASE2 0x200 /* Base address of UART2 */ /* + * DMA unit base addresses. + */ +#define MCFDMA_BASE0 (MCF_MBAR + 0x300) /* Base address DMA 0 */ +#define MCFDMA_BASE1 (MCF_MBAR + 0x340) /* Base address DMA 1 */ +#define MCFDMA_BASE2 (MCF_MBAR + 0x380) /* Base address DMA 2 */ +#define MCFDMA_BASE3 (MCF_MBAR + 0x3C0) /* Base address DMA 3 */ + +/* * Some symbol defines for the above... */ #define MCFSIM_SWDICR MCFSIM_ICR0 /* Watchdog timer ICR */ diff --git a/arch/m68k/include/asm/m5272sim.h b/arch/m68k/include/asm/m5272sim.h index b7cc50abc831..759c2b07a994 100644 --- a/arch/m68k/include/asm/m5272sim.h +++ b/arch/m68k/include/asm/m5272sim.h @@ -14,6 +14,7 @@ #define CPU_NAME "COLDFIRE(m5272)" #define CPU_INSTR_PER_JIFFY 3 +#define MCF_BUSCLK MCF_CLK #include <asm/m52xxacr.h> @@ -80,6 +81,13 @@ #define MCFSIM_PCDAT (MCF_MBAR + 0x96) /* Port C Data (r/w) */ #define MCFSIM_PDCNT (MCF_MBAR + 0x98) /* Port D Control (r/w) */ +#define MCFDMA_BASE0 (MCF_MBAR + 0xe0) /* Base address DMA 0 */ + +#define MCFTIMER_BASE1 (MCF_MBAR + 0x200) /* Base address TIMER1 */ +#define MCFTIMER_BASE2 (MCF_MBAR + 0x220) /* Base address TIMER2 */ +#define MCFTIMER_BASE3 (MCF_MBAR + 0x240) /* Base address TIMER4 */ +#define MCFTIMER_BASE4 (MCF_MBAR + 0x260) /* Base address TIMER3 */ + /* * Define system peripheral IRQ usage. */ diff --git a/arch/m68k/include/asm/m527xsim.h b/arch/m68k/include/asm/m527xsim.h index e8042e8bc003..758810ef91ec 100644 --- a/arch/m68k/include/asm/m527xsim.h +++ b/arch/m68k/include/asm/m527xsim.h @@ -13,14 +13,16 @@ #define CPU_NAME "COLDFIRE(m527x)" #define CPU_INSTR_PER_JIFFY 3 +#define MCF_BUSCLK (MCF_CLK / 2) #include <asm/m52xxacr.h> /* * Define the 5270/5271 SIM register set addresses. */ -#define MCFICM_INTC0 0x0c00 /* Base for Interrupt Ctrl 0 */ -#define MCFICM_INTC1 0x0d00 /* Base for Interrupt Ctrl 1 */ +#define MCFICM_INTC0 (MCF_IPSBAR + 0x0c00) /* Base for Interrupt Ctrl 0 */ +#define MCFICM_INTC1 (MCF_IPSBAR + 0x0d00) /* Base for Interrupt Ctrl 1 */ + #define MCFINTC_IPRH 0x00 /* Interrupt pending 32-63 */ #define MCFINTC_IPRL 0x04 /* Interrupt pending 1-31 */ #define MCFINTC_IMRH 0x08 /* Interrupt mask 32-63 */ @@ -42,29 +44,45 @@ * SDRAM configuration registers. */ #ifdef CONFIG_M5271 -#define MCFSIM_DCR 0x40 /* SDRAM control */ -#define MCFSIM_DACR0 0x48 /* SDRAM base address 0 */ -#define MCFSIM_DMR0 0x4c /* SDRAM address mask 0 */ -#define MCFSIM_DACR1 0x50 /* SDRAM base address 1 */ -#define MCFSIM_DMR1 0x54 /* SDRAM address mask 1 */ +#define MCFSIM_DCR (MCF_IPSBAR + 0x40) /* Control */ +#define MCFSIM_DACR0 (MCF_IPSBAR + 0x48) /* Base address 0 */ +#define MCFSIM_DMR0 (MCF_IPSBAR + 0x4c) /* Address mask 0 */ +#define MCFSIM_DACR1 (MCF_IPSBAR + 0x50) /* Base address 1 */ +#define MCFSIM_DMR1 (MCF_IPSBAR + 0x54) /* Address mask 1 */ #endif #ifdef CONFIG_M5275 -#define MCFSIM_DMR 0x40 /* SDRAM mode */ -#define MCFSIM_DCR 0x44 /* SDRAM control */ -#define MCFSIM_DCFG1 0x48 /* SDRAM configuration 1 */ -#define MCFSIM_DCFG2 0x4c /* SDRAM configuration 2 */ -#define MCFSIM_DBAR0 0x50 /* SDRAM base address 0 */ -#define MCFSIM_DMR0 0x54 /* SDRAM address mask 0 */ -#define MCFSIM_DBAR1 0x58 /* SDRAM base address 1 */ -#define MCFSIM_DMR1 0x5c /* SDRAM address mask 1 */ +#define MCFSIM_DMR (MCF_IPSBAR + 0x40) /* Mode */ +#define MCFSIM_DCR (MCF_IPSBAR + 0x44) /* Control */ +#define MCFSIM_DCFG1 (MCF_IPSBAR + 0x48) /* Configuration 1 */ +#define MCFSIM_DCFG2 (MCF_IPSBAR + 0x4c) /* Configuration 2 */ +#define MCFSIM_DBAR0 (MCF_IPSBAR + 0x50) /* Base address 0 */ +#define MCFSIM_DMR0 (MCF_IPSBAR + 0x54) /* Address mask 0 */ +#define MCFSIM_DBAR1 (MCF_IPSBAR + 0x58) /* Base address 1 */ +#define MCFSIM_DMR1 (MCF_IPSBAR + 0x5c) /* Address mask 1 */ #endif /* + * DMA unit base addresses. + */ +#define MCFDMA_BASE0 (MCF_IPSBAR + 0x100) +#define MCFDMA_BASE1 (MCF_IPSBAR + 0x140) +#define MCFDMA_BASE2 (MCF_IPSBAR + 0x180) +#define MCFDMA_BASE3 (MCF_IPSBAR + 0x1C0) + +/* * UART module. */ -#define MCFUART_BASE1 0x200 /* Base address of UART1 */ -#define MCFUART_BASE2 0x240 /* Base address of UART2 */ -#define MCFUART_BASE3 0x280 /* Base address of UART3 */ +#define MCFUART_BASE1 (MCF_IPSBAR + 0x200) +#define MCFUART_BASE2 (MCF_IPSBAR + 0x240) +#define MCFUART_BASE3 (MCF_IPSBAR + 0x280) + +/* + * FEC ethernet module. + */ +#define MCFFEC_BASE0 (MCF_IPSBAR + 0x1000) +#define MCFFEC_SIZE0 0x800 +#define MCFFEC_BASE1 (MCF_IPSBAR + 0x1800) +#define MCFFEC_SIZE1 0x800 #ifdef CONFIG_M5271 #define MCFGPIO_PODR_ADDR (MCF_IPSBAR + 0x100000) @@ -231,14 +249,22 @@ #endif /* - * EPort + * PIT timer base addresses. */ +#define MCFPIT_BASE1 (MCF_IPSBAR + 0x150000) +#define MCFPIT_BASE2 (MCF_IPSBAR + 0x160000) +#define MCFPIT_BASE3 (MCF_IPSBAR + 0x170000) +#define MCFPIT_BASE4 (MCF_IPSBAR + 0x180000) +/* + * EPort + */ +#define MCFEPORT_EPPAR (MCF_IPSBAR + 0x130000) #define MCFEPORT_EPDDR (MCF_IPSBAR + 0x130002) +#define MCFEPORT_EPIER (MCF_IPSBAR + 0x130003) #define MCFEPORT_EPDR (MCF_IPSBAR + 0x130004) #define MCFEPORT_EPPDR (MCF_IPSBAR + 0x130005) - - +#define MCFEPORT_EPFR (MCF_IPSBAR + 0x130006) /* * GPIO pins setups to enable the UARTs. @@ -257,7 +283,7 @@ #endif /* - * Reset Controll Unit (relative to IPSBAR). + * Reset Control Unit (relative to IPSBAR). */ #define MCF_RCR 0x110000 #define MCF_RSR 0x110001 diff --git a/arch/m68k/include/asm/m528xsim.h b/arch/m68k/include/asm/m528xsim.h index a6d2f4d9aaa0..d798bd5df56c 100644 --- a/arch/m68k/include/asm/m528xsim.h +++ b/arch/m68k/include/asm/m528xsim.h @@ -13,14 +13,16 @@ #define CPU_NAME "COLDFIRE(m528x)" #define CPU_INSTR_PER_JIFFY 3 +#define MCF_BUSCLK MCF_CLK #include <asm/m52xxacr.h> /* * Define the 5280/5282 SIM register set addresses. */ -#define MCFICM_INTC0 0x0c00 /* Base for Interrupt Ctrl 0 */ -#define MCFICM_INTC1 0x0d00 /* Base for Interrupt Ctrl 0 */ +#define MCFICM_INTC0 (MCF_IPSBAR + 0x0c00) /* Base for Interrupt Ctrl 0 */ +#define MCFICM_INTC1 (MCF_IPSBAR + 0x0d00) /* Base for Interrupt Ctrl 0 */ + #define MCFINTC_IPRH 0x00 /* Interrupt pending 32-63 */ #define MCFINTC_IPRL 0x04 /* Interrupt pending 1-31 */ #define MCFINTC_IMRH 0x08 /* Interrupt mask 32-63 */ @@ -39,18 +41,32 @@ /* * SDRAM configuration registers. */ -#define MCFSIM_DCR 0x44 /* SDRAM control */ -#define MCFSIM_DACR0 0x48 /* SDRAM base address 0 */ -#define MCFSIM_DMR0 0x4c /* SDRAM address mask 0 */ -#define MCFSIM_DACR1 0x50 /* SDRAM base address 1 */ -#define MCFSIM_DMR1 0x54 /* SDRAM address mask 1 */ +#define MCFSIM_DCR (MCF_IPSBAR + 0x00000044) /* Control */ +#define MCFSIM_DACR0 (MCF_IPSBAR + 0x00000048) /* Base address 0 */ +#define MCFSIM_DMR0 (MCF_IPSBAR + 0x0000004c) /* Address mask 0 */ +#define MCFSIM_DACR1 (MCF_IPSBAR + 0x00000050) /* Base address 1 */ +#define MCFSIM_DMR1 (MCF_IPSBAR + 0x00000054) /* Address mask 1 */ + +/* + * DMA unit base addresses. + */ +#define MCFDMA_BASE0 (MCF_IPSBAR + 0x00000100) +#define MCFDMA_BASE1 (MCF_IPSBAR + 0x00000140) +#define MCFDMA_BASE2 (MCF_IPSBAR + 0x00000180) +#define MCFDMA_BASE3 (MCF_IPSBAR + 0x000001C0) /* * UART module. */ -#define MCFUART_BASE1 0x200 /* Base address of UART1 */ -#define MCFUART_BASE2 0x240 /* Base address of UART2 */ -#define MCFUART_BASE3 0x280 /* Base address of UART3 */ +#define MCFUART_BASE1 (MCF_IPSBAR + 0x00000200) +#define MCFUART_BASE2 (MCF_IPSBAR + 0x00000240) +#define MCFUART_BASE3 (MCF_IPSBAR + 0x00000280) + +/* + * FEC ethernet module. + */ +#define MCFFEC_BASE (MCF_IPSBAR + 0x00001000) +#define MCFFEC_SIZE 0x800 /* * GPIO registers @@ -163,6 +179,14 @@ #define MCFGPIO_PUAPAR (MCF_IPSBAR + 0x0010005C) /* + * PIT timer base addresses. + */ +#define MCFPIT_BASE1 (MCF_IPSBAR + 0x00150000) +#define MCFPIT_BASE2 (MCF_IPSBAR + 0x00160000) +#define MCFPIT_BASE3 (MCF_IPSBAR + 0x00170000) +#define MCFPIT_BASE4 (MCF_IPSBAR + 0x00180000) + +/* * Edge Port registers */ #define MCFEPORT_EPPAR (MCF_IPSBAR + 0x00130000) diff --git a/arch/m68k/include/asm/m5307sim.h b/arch/m68k/include/asm/m5307sim.h index 0bf57397e7a9..8f8609fcc9b8 100644 --- a/arch/m68k/include/asm/m5307sim.h +++ b/arch/m68k/include/asm/m5307sim.h @@ -16,6 +16,7 @@ #define CPU_NAME "COLDFIRE(m5307)" #define CPU_INSTR_PER_JIFFY 3 +#define MCF_BUSCLK (MCF_CLK / 2) #include <asm/m53xxacr.h> @@ -28,7 +29,7 @@ #define MCFSIM_SWSR 0x03 /* SW Watchdog service (r/w) */ #define MCFSIM_PAR 0x04 /* Pin Assignment reg (r/w) */ #define MCFSIM_IRQPAR 0x06 /* Interrupt Assignment reg (r/w) */ -#define MCFSIM_PLLCR 0x08 /* PLL Controll Reg*/ +#define MCFSIM_PLLCR 0x08 /* PLL Control Reg*/ #define MCFSIM_MPARK 0x0C /* BUS Master Control Reg*/ #define MCFSIM_IPR 0x40 /* Interrupt Pend reg (r/w) */ #define MCFSIM_IMR 0x44 /* Interrupt Mask reg (r/w) */ @@ -89,16 +90,30 @@ #define MCFSIM_CSCR7 0xde /* CS 7 Control reg (r/w) */ #endif /* CONFIG_OLDMASK */ -#define MCFSIM_DCR 0x100 /* DRAM Control reg (r/w) */ -#define MCFSIM_DACR0 0x108 /* DRAM 0 Addr and Ctrl (r/w) */ -#define MCFSIM_DMR0 0x10c /* DRAM 0 Mask reg (r/w) */ -#define MCFSIM_DACR1 0x110 /* DRAM 1 Addr and Ctrl (r/w) */ -#define MCFSIM_DMR1 0x114 /* DRAM 1 Mask reg (r/w) */ +#define MCFSIM_DCR (MCF_MBAR + 0x100) /* DRAM Control */ +#define MCFSIM_DACR0 (MCF_MBAR + 0x108) /* DRAM Addr/Ctrl 0 */ +#define MCFSIM_DMR0 (MCF_MBAR + 0x10c) /* DRAM Mask 0 */ +#define MCFSIM_DACR1 (MCF_MBAR + 0x110) /* DRAM Addr/Ctrl 1 */ +#define MCFSIM_DMR1 (MCF_MBAR + 0x114) /* DRAM Mask 1 */ + +/* + * Timer module. + */ +#define MCFTIMER_BASE1 (MCF_MBAR + 0x140) /* Base of TIMER1 */ +#define MCFTIMER_BASE2 (MCF_MBAR + 0x180) /* Base of TIMER2 */ #define MCFSIM_PADDR (MCF_MBAR + 0x244) #define MCFSIM_PADAT (MCF_MBAR + 0x248) /* + * DMA unit base addresses. + */ +#define MCFDMA_BASE0 (MCF_MBAR + 0x300) /* Base address DMA 0 */ +#define MCFDMA_BASE1 (MCF_MBAR + 0x340) /* Base address DMA 1 */ +#define MCFDMA_BASE2 (MCF_MBAR + 0x380) /* Base address DMA 2 */ +#define MCFDMA_BASE3 (MCF_MBAR + 0x3C0) /* Base address DMA 3 */ + +/* * UART module. */ #if defined(CONFIG_NETtel) || defined(CONFIG_SECUREEDGEMP3) diff --git a/arch/m68k/include/asm/m532xsim.h b/arch/m68k/include/asm/m532xsim.h index e6470f8ca324..ba4cc784f574 100644 --- a/arch/m68k/include/asm/m532xsim.h +++ b/arch/m68k/include/asm/m532xsim.h @@ -11,6 +11,7 @@ #define CPU_NAME "COLDFIRE(m532x)" #define CPU_INSTR_PER_JIFFY 3 +#define MCF_BUSCLK (MCF_CLK / 3) #include <asm/m53xxacr.h> @@ -85,6 +86,14 @@ #define MCFUART_BASE2 0xFC064000 /* Base address of UART2 */ #define MCFUART_BASE3 0xFC068000 /* Base address of UART3 */ +/* + * Timer module. + */ +#define MCFTIMER_BASE1 0xFC070000 /* Base address of TIMER1 */ +#define MCFTIMER_BASE2 0xFC074000 /* Base address of TIMER2 */ +#define MCFTIMER_BASE3 0xFC078000 /* Base address of TIMER3 */ +#define MCFTIMER_BASE4 0xFC07C000 /* Base address of TIMER4 */ + /********************************************************************* * * Reset Controller Module diff --git a/arch/m68k/include/asm/m5407sim.h b/arch/m68k/include/asm/m5407sim.h index 75f5c28a551d..51e00b00b8a6 100644 --- a/arch/m68k/include/asm/m5407sim.h +++ b/arch/m68k/include/asm/m5407sim.h @@ -16,6 +16,7 @@ #define CPU_NAME "COLDFIRE(m5407)" #define CPU_INSTR_PER_JIFFY 3 +#define MCF_BUSCLK (MCF_CLK / 2) #include <asm/m54xxacr.h> @@ -28,7 +29,7 @@ #define MCFSIM_SWSR 0x03 /* SW Watchdog service (r/w) */ #define MCFSIM_PAR 0x04 /* Pin Assignment reg (r/w) */ #define MCFSIM_IRQPAR 0x06 /* Interrupt Assignment reg (r/w) */ -#define MCFSIM_PLLCR 0x08 /* PLL Controll Reg*/ +#define MCFSIM_PLLCR 0x08 /* PLL Control Reg*/ #define MCFSIM_MPARK 0x0C /* BUS Master Control Reg*/ #define MCFSIM_IPR 0x40 /* Interrupt Pend reg (r/w) */ #define MCFSIM_IMR 0x44 /* Interrupt Mask reg (r/w) */ @@ -72,11 +73,17 @@ #define MCFSIM_CSMR7 0xd8 /* CS 7 Mask reg (r/w) */ #define MCFSIM_CSCR7 0xde /* CS 7 Control reg (r/w) */ -#define MCFSIM_DCR 0x100 /* DRAM Control reg (r/w) */ -#define MCFSIM_DACR0 0x108 /* DRAM 0 Addr and Ctrl (r/w) */ -#define MCFSIM_DMR0 0x10c /* DRAM 0 Mask reg (r/w) */ -#define MCFSIM_DACR1 0x110 /* DRAM 1 Addr and Ctrl (r/w) */ -#define MCFSIM_DMR1 0x114 /* DRAM 1 Mask reg (r/w) */ +#define MCFSIM_DCR (MCF_MBAR + 0x100) /* DRAM Control */ +#define MCFSIM_DACR0 (MCF_MBAR + 0x108) /* DRAM 0 Addr/Ctrl */ +#define MCFSIM_DMR0 (MCF_MBAR + 0x10c) /* DRAM 0 Mask */ +#define MCFSIM_DACR1 (MCF_MBAR + 0x110) /* DRAM 1 Addr/Ctrl */ +#define MCFSIM_DMR1 (MCF_MBAR + 0x114) /* DRAM 1 Mask */ + +/* + * Timer module. + */ +#define MCFTIMER_BASE1 (MCF_MBAR + 0x140) /* Base of TIMER1 */ +#define MCFTIMER_BASE2 (MCF_MBAR + 0x180) /* Base of TIMER2 */ #define MCFUART_BASE1 0x1c0 /* Base address of UART1 */ #define MCFUART_BASE2 0x200 /* Base address of UART2 */ @@ -85,6 +92,14 @@ #define MCFSIM_PADAT (MCF_MBAR + 0x248) /* + * DMA unit base addresses. + */ +#define MCFDMA_BASE0 (MCF_MBAR + 0x300) /* Base address DMA 0 */ +#define MCFDMA_BASE1 (MCF_MBAR + 0x340) /* Base address DMA 1 */ +#define MCFDMA_BASE2 (MCF_MBAR + 0x380) /* Base address DMA 2 */ +#define MCFDMA_BASE3 (MCF_MBAR + 0x3C0) /* Base address DMA 3 */ + +/* * Generic GPIO support */ #define MCFGPIO_PIN_MAX 16 diff --git a/arch/m68k/include/asm/m54xxsim.h b/arch/m68k/include/asm/m54xxsim.h index 462ae5328441..1ed8bfb02772 100644 --- a/arch/m68k/include/asm/m54xxsim.h +++ b/arch/m68k/include/asm/m54xxsim.h @@ -7,6 +7,7 @@ #define CPU_NAME "COLDFIRE(m54xx)" #define CPU_INSTR_PER_JIFFY 2 +#define MCF_BUSCLK (MCF_CLK / 2) #include <asm/m54xxacr.h> @@ -15,7 +16,8 @@ /* * Interrupt Controller Registers */ -#define MCFICM_INTC0 0x0700 /* Base for Interrupt Ctrl 0 */ +#define MCFICM_INTC0 (MCF_MBAR + 0x700) /* Base for Interrupt Ctrl 0 */ + #define MCFINTC_IPRH 0x00 /* Interrupt pending 32-63 */ #define MCFINTC_IPRL 0x04 /* Interrupt pending 1-31 */ #define MCFINTC_IMRH 0x08 /* Interrupt mask 32-63 */ @@ -48,6 +50,16 @@ #define MCFGPIO_IRQ_VECBASE -1 /* + * EDGE Port support. + */ +#define MCFEPORT_EPPAR (MCF_MBAR + 0xf00) /* Pin assignment */ +#define MCFEPORT_EPDDR (MCF_MBAR + 0xf04) /* Data direction */ +#define MCFEPORT_EPIER (MCF_MBAR + 0xf05) /* Interrupt enable */ +#define MCFEPORT_EPDR (MCF_MBAR + 0xf08) /* Port data (w) */ +#define MCFEPORT_EPPDR (MCF_MBAR + 0xf09) /* Port data (r) */ +#define MCFEPORT_EPFR (MCF_MBAR + 0xf0c) /* Flags */ + +/* * Some PSC related definitions */ #define MCF_PAR_PSC(x) (0x000A4F-((x)&0x3)) diff --git a/arch/m68k/include/asm/m68360_quicc.h b/arch/m68k/include/asm/m68360_quicc.h index 6d40f4d18e10..59414cc108d3 100644 --- a/arch/m68k/include/asm/m68360_quicc.h +++ b/arch/m68k/include/asm/m68360_quicc.h @@ -32,7 +32,7 @@ struct user_data { /* BASE + 0x000: user data memory */ volatile unsigned char udata_bd_ucode[0x400]; /*user data bd's Ucode*/ volatile unsigned char udata_bd[0x200]; /*user data Ucode */ - volatile unsigned char ucode_ext[0x100]; /*Ucode Extention ram */ + volatile unsigned char ucode_ext[0x100]; /*Ucode Extension ram */ volatile unsigned char RESERVED1[0x500]; /* Reserved area */ }; #else diff --git a/arch/m68k/include/asm/mac_oss.h b/arch/m68k/include/asm/mac_oss.h index 7221f7251934..3cf2b6ed685a 100644 --- a/arch/m68k/include/asm/mac_oss.h +++ b/arch/m68k/include/asm/mac_oss.h @@ -61,7 +61,7 @@ /* * OSS Interrupt levels for various sub-systems * - * This mapping is layed out with two things in mind: first, we try to keep + * This mapping is laid out with two things in mind: first, we try to keep * things on their own levels to avoid having to do double-dispatches. Second, * the levels match as closely as possible the alternate IRQ mapping mode (aka * "A/UX mode") available on some VIA machines. diff --git a/arch/m68k/include/asm/mac_via.h b/arch/m68k/include/asm/mac_via.h index 39afb438b656..a59665e1d41b 100644 --- a/arch/m68k/include/asm/mac_via.h +++ b/arch/m68k/include/asm/mac_via.h @@ -204,7 +204,7 @@ #define vT2CL 0x1000 /* [VIA only] Timer two counter low. */ #define vT2CH 0x1200 /* [VIA only] Timer two counter high. */ #define vSR 0x1400 /* [VIA only] Shift register. */ -#define vACR 0x1600 /* [VIA only] Auxilary control register. */ +#define vACR 0x1600 /* [VIA only] Auxiliary control register. */ #define vPCR 0x1800 /* [VIA only] Peripheral control register. */ /* CHRP sez never ever to *write* this. * Mac family says never to *change* this. diff --git a/arch/m68k/include/asm/macintosh.h b/arch/m68k/include/asm/macintosh.h index 50db3591ca15..c2a1c5eac1a6 100644 --- a/arch/m68k/include/asm/macintosh.h +++ b/arch/m68k/include/asm/macintosh.h @@ -14,7 +14,7 @@ extern void mac_init_IRQ(void); extern int mac_irq_pending(unsigned int); /* - * Floppy driver magic hook - probably shouldnt be here + * Floppy driver magic hook - probably shouldn't be here */ extern void via1_set_head(int); diff --git a/arch/m68k/include/asm/mcfdma.h b/arch/m68k/include/asm/mcfdma.h index 705c52c79cd8..10bc7e391c14 100644 --- a/arch/m68k/include/asm/mcfdma.h +++ b/arch/m68k/include/asm/mcfdma.h @@ -11,29 +11,6 @@ #define mcfdma_h /****************************************************************************/ - -/* - * Get address specific defines for this Coldfire member. - */ -#if defined(CONFIG_M5206) || defined(CONFIG_M5206e) -#define MCFDMA_BASE0 0x200 /* Base address of DMA 0 */ -#define MCFDMA_BASE1 0x240 /* Base address of DMA 1 */ -#elif defined(CONFIG_M5272) -#define MCFDMA_BASE0 0x0e0 /* Base address of DMA 0 */ -#elif defined(CONFIG_M523x) || defined(CONFIG_M527x) || defined(CONFIG_M528x) -/* These are relative to the IPSBAR, not MBAR */ -#define MCFDMA_BASE0 0x100 /* Base address of DMA 0 */ -#define MCFDMA_BASE1 0x140 /* Base address of DMA 1 */ -#define MCFDMA_BASE2 0x180 /* Base address of DMA 2 */ -#define MCFDMA_BASE3 0x1C0 /* Base address of DMA 3 */ -#elif defined(CONFIG_M5249) || defined(CONFIG_M5307) || defined(CONFIG_M5407) -#define MCFDMA_BASE0 0x300 /* Base address of DMA 0 */ -#define MCFDMA_BASE1 0x340 /* Base address of DMA 1 */ -#define MCFDMA_BASE2 0x380 /* Base address of DMA 2 */ -#define MCFDMA_BASE3 0x3C0 /* Base address of DMA 3 */ -#endif - - #if !defined(CONFIG_M5272) /* diff --git a/arch/m68k/include/asm/mcfpit.h b/arch/m68k/include/asm/mcfpit.h index f570cf64fd29..9fd321ca0725 100644 --- a/arch/m68k/include/asm/mcfpit.h +++ b/arch/m68k/include/asm/mcfpit.h @@ -11,22 +11,8 @@ #define mcfpit_h /****************************************************************************/ - -/* - * Get address specific defines for the 5270/5271, 5280/5282, and 5208. - */ -#if defined(CONFIG_M520x) -#define MCFPIT_BASE1 0x00080000 /* Base address of TIMER1 */ -#define MCFPIT_BASE2 0x00084000 /* Base address of TIMER2 */ -#else -#define MCFPIT_BASE1 0x00150000 /* Base address of TIMER1 */ -#define MCFPIT_BASE2 0x00160000 /* Base address of TIMER2 */ -#define MCFPIT_BASE3 0x00170000 /* Base address of TIMER3 */ -#define MCFPIT_BASE4 0x00180000 /* Base address of TIMER4 */ -#endif - /* - * Define the PIT timer register set addresses. + * Define the PIT timer register address offsets. */ #define MCFPIT_PCSR 0x0 /* PIT control register */ #define MCFPIT_PMR 0x2 /* PIT modulus register */ diff --git a/arch/m68k/include/asm/mcftimer.h b/arch/m68k/include/asm/mcftimer.h index 0f90f6d2227a..351c27237874 100644 --- a/arch/m68k/include/asm/mcftimer.h +++ b/arch/m68k/include/asm/mcftimer.h @@ -12,29 +12,6 @@ #define mcftimer_h /****************************************************************************/ - -/* - * Get address specific defines for this ColdFire member. - */ -#if defined(CONFIG_M5206) || defined(CONFIG_M5206e) -#define MCFTIMER_BASE1 0x100 /* Base address of TIMER1 */ -#define MCFTIMER_BASE2 0x120 /* Base address of TIMER2 */ -#elif defined(CONFIG_M5272) -#define MCFTIMER_BASE1 0x200 /* Base address of TIMER1 */ -#define MCFTIMER_BASE2 0x220 /* Base address of TIMER2 */ -#define MCFTIMER_BASE3 0x240 /* Base address of TIMER4 */ -#define MCFTIMER_BASE4 0x260 /* Base address of TIMER3 */ -#elif defined(CONFIG_M5249) || defined(CONFIG_M5307) || defined(CONFIG_M5407) -#define MCFTIMER_BASE1 0x140 /* Base address of TIMER1 */ -#define MCFTIMER_BASE2 0x180 /* Base address of TIMER2 */ -#elif defined(CONFIG_M532x) -#define MCFTIMER_BASE1 0xfc070000 /* Base address of TIMER1 */ -#define MCFTIMER_BASE2 0xfc074000 /* Base address of TIMER2 */ -#define MCFTIMER_BASE3 0xfc078000 /* Base address of TIMER3 */ -#define MCFTIMER_BASE4 0xfc07c000 /* Base address of TIMER4 */ -#endif - - /* * Define the TIMER register set addresses. */ @@ -50,7 +27,7 @@ /* * Bit definitions for the Timer Mode Register (TMR). - * Register bit flags are common accross ColdFires. + * Register bit flags are common across ColdFires. */ #define MCFTIMER_TMR_PREMASK 0xff00 /* Prescalar mask */ #define MCFTIMER_TMR_DISCE 0x0000 /* Disable capture */ diff --git a/arch/m68k/include/asm/natfeat.h b/arch/m68k/include/asm/natfeat.h new file mode 100644 index 000000000000..a3521b80c3b9 --- /dev/null +++ b/arch/m68k/include/asm/natfeat.h @@ -0,0 +1,22 @@ +/* + * ARAnyM hardware support via Native Features (natfeats) + * + * Copyright (c) 2005 Petr Stehlik of ARAnyM dev team + * + * This software may be used and distributed according to the terms of + * the GNU General Public License (GPL), incorporated herein by reference. + */ + +#ifndef _NATFEAT_H +#define _NATFEAT_H + +long nf_get_id(const char *feature_name); +long nf_call(long id, ...); + +void nf_init(void); +void nf_shutdown(void); + +void nfprint(const char *fmt, ...) + __attribute__ ((format (printf, 1, 2))); + +# endif /* _NATFEAT_H */ diff --git a/arch/m68k/include/asm/processor.h b/arch/m68k/include/asm/processor.h index 278c69bad57a..f111b02b704f 100644 --- a/arch/m68k/include/asm/processor.h +++ b/arch/m68k/include/asm/processor.h @@ -113,6 +113,8 @@ static inline void start_thread(struct pt_regs * regs, unsigned long pc, wrusp(usp); } +extern int handle_kernel_fault(struct pt_regs *regs); + #else /* diff --git a/arch/m68k/include/asm/types.h b/arch/m68k/include/asm/types.h index 6441cb5f8e7c..b17fd115a4e7 100644 --- a/arch/m68k/include/asm/types.h +++ b/arch/m68k/include/asm/types.h @@ -23,15 +23,6 @@ typedef unsigned short umode_t; #define BITS_PER_LONG 32 -#ifndef __ASSEMBLY__ - -/* DMA addresses are always 32-bits wide */ - -typedef u32 dma_addr_t; -typedef u32 dma64_addr_t; - -#endif /* __ASSEMBLY__ */ - #endif /* __KERNEL__ */ #endif /* _M68K_TYPES_H */ diff --git a/arch/m68k/include/asm/unistd.h b/arch/m68k/include/asm/unistd.h index 26d851d385bb..f3b649de2a1b 100644 --- a/arch/m68k/include/asm/unistd.h +++ b/arch/m68k/include/asm/unistd.h @@ -22,7 +22,7 @@ #define __NR_mknod 14 #define __NR_chmod 15 #define __NR_chown 16 -#define __NR_break 17 +/*#define __NR_break 17*/ #define __NR_oldstat 18 #define __NR_lseek 19 #define __NR_getpid 20 @@ -36,11 +36,11 @@ #define __NR_oldfstat 28 #define __NR_pause 29 #define __NR_utime 30 -#define __NR_stty 31 -#define __NR_gtty 32 +/*#define __NR_stty 31*/ +/*#define __NR_gtty 32*/ #define __NR_access 33 #define __NR_nice 34 -#define __NR_ftime 35 +/*#define __NR_ftime 35*/ #define __NR_sync 36 #define __NR_kill 37 #define __NR_rename 38 @@ -49,7 +49,7 @@ #define __NR_dup 41 #define __NR_pipe 42 #define __NR_times 43 -#define __NR_prof 44 +/*#define __NR_prof 44*/ #define __NR_brk 45 #define __NR_setgid 46 #define __NR_getgid 47 @@ -58,13 +58,13 @@ #define __NR_getegid 50 #define __NR_acct 51 #define __NR_umount2 52 -#define __NR_lock 53 +/*#define __NR_lock 53*/ #define __NR_ioctl 54 #define __NR_fcntl 55 -#define __NR_mpx 56 +/*#define __NR_mpx 56*/ #define __NR_setpgid 57 -#define __NR_ulimit 58 -#define __NR_oldolduname 59 +/*#define __NR_ulimit 58*/ +/*#define __NR_oldolduname 59*/ #define __NR_umask 60 #define __NR_chroot 61 #define __NR_ustat 62 @@ -103,10 +103,10 @@ #define __NR_fchown 95 #define __NR_getpriority 96 #define __NR_setpriority 97 -#define __NR_profil 98 +/*#define __NR_profil 98*/ #define __NR_statfs 99 #define __NR_fstatfs 100 -#define __NR_ioperm 101 +/*#define __NR_ioperm 101*/ #define __NR_socketcall 102 #define __NR_syslog 103 #define __NR_setitimer 104 @@ -114,11 +114,11 @@ #define __NR_stat 106 #define __NR_lstat 107 #define __NR_fstat 108 -#define __NR_olduname 109 -#define __NR_iopl /* 110 */ not supported +/*#define __NR_olduname 109*/ +/*#define __NR_iopl 110*/ /* not supported */ #define __NR_vhangup 111 -#define __NR_idle /* 112 */ Obsolete -#define __NR_vm86 /* 113 */ not supported +/*#define __NR_idle 112*/ /* Obsolete */ +/*#define __NR_vm86 113*/ /* not supported */ #define __NR_wait4 114 #define __NR_swapoff 115 #define __NR_sysinfo 116 @@ -132,17 +132,17 @@ #define __NR_adjtimex 124 #define __NR_mprotect 125 #define __NR_sigprocmask 126 -#define __NR_create_module 127 +/*#define __NR_create_module 127*/ #define __NR_init_module 128 #define __NR_delete_module 129 -#define __NR_get_kernel_syms 130 +/*#define __NR_get_kernel_syms 130*/ #define __NR_quotactl 131 #define __NR_getpgid 132 #define __NR_fchdir 133 #define __NR_bdflush 134 #define __NR_sysfs 135 #define __NR_personality 136 -#define __NR_afs_syscall 137 /* Syscall for Andrew File System */ +/*#define __NR_afs_syscall 137*/ /* Syscall for Andrew File System */ #define __NR_setfsuid 138 #define __NR_setfsgid 139 #define __NR__llseek 140 @@ -172,7 +172,7 @@ #define __NR_setresuid 164 #define __NR_getresuid 165 #define __NR_getpagesize 166 -#define __NR_query_module 167 +/*#define __NR_query_module 167*/ #define __NR_poll 168 #define __NR_nfsservctl 169 #define __NR_setresgid 170 @@ -193,8 +193,8 @@ #define __NR_capset 185 #define __NR_sigaltstack 186 #define __NR_sendfile 187 -#define __NR_getpmsg 188 /* some people actually want streams */ -#define __NR_putpmsg 189 /* some people actually want streams */ +/*#define __NR_getpmsg 188*/ /* some people actually want streams */ +/*#define __NR_putpmsg 189*/ /* some people actually want streams */ #define __NR_vfork 190 #define __NR_ugetrlimit 191 #define __NR_mmap2 192 @@ -223,6 +223,8 @@ #define __NR_setfsuid32 215 #define __NR_setfsgid32 216 #define __NR_pivot_root 217 +/* 218*/ +/* 219*/ #define __NR_getdents64 220 #define __NR_gettid 221 #define __NR_tkill 222 @@ -281,7 +283,7 @@ #define __NR_mq_notify 275 #define __NR_mq_getsetattr 276 #define __NR_waitid 277 -#define __NR_vserver 278 +/*#define __NR_vserver 278*/ #define __NR_add_key 279 #define __NR_request_key 280 #define __NR_keyctl 281 @@ -343,10 +345,14 @@ #define __NR_fanotify_init 337 #define __NR_fanotify_mark 338 #define __NR_prlimit64 339 +#define __NR_name_to_handle_at 340 +#define __NR_open_by_handle_at 341 +#define __NR_clock_adjtime 342 +#define __NR_syncfs 343 #ifdef __KERNEL__ -#define NR_syscalls 340 +#define NR_syscalls 344 #define __ARCH_WANT_IPC_PARSE_VERSION #define __ARCH_WANT_OLD_READDIR |