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-rw-r--r--arch/arm64/kernel/head.S7
-rw-r--r--arch/arm64/kernel/setup.c3
2 files changed, 1 insertions, 9 deletions
diff --git a/arch/arm64/kernel/head.S b/arch/arm64/kernel/head.S
index ebb9e630230a..88f14a77eac0 100644
--- a/arch/arm64/kernel/head.S
+++ b/arch/arm64/kernel/head.S
@@ -244,7 +244,6 @@ ENTRY(stext)
bl el2_setup // Drop to EL1, w20=cpu_boot_mode
bl __calc_phys_offset // x24=PHYS_OFFSET, x28=PHYS_OFFSET-PAGE_OFFSET
bl set_cpu_boot_mode_flag
- mrs x22, midr_el1 // x22=cpuid
bl __vet_fdt
bl __create_page_tables // x25=TTBR0, x26=TTBR1
@@ -427,7 +426,6 @@ __switch_data:
.quad __mmap_switched
.quad __bss_start // x6
.quad __bss_stop // x7
- .quad processor_id // x4
.quad __fdt_pointer // x5
.quad memstart_addr // x6
.quad init_thread_union + THREAD_START_SP // sp
@@ -445,11 +443,10 @@ __mmap_switched:
str xzr, [x6], #8 // Clear BSS
b 1b
2:
- ldp x4, x5, [x3], #16
+ ldr x5, [x3], #8
ldr x6, [x3], #8
ldr x16, [x3]
mov sp, x16
- str x22, [x4] // Save processor ID
str x21, [x5] // Save FDT pointer
str x24, [x6] // Save PHYS_OFFSET
mov x29, #0
@@ -621,8 +618,6 @@ ENTRY(secondary_startup)
/*
* Common entry point for secondary CPUs.
*/
- mrs x22, midr_el1 // x22=cpuid
-
pgtbl x25, x26, x28 // x25=TTBR0, x26=TTBR1
bl __cpu_setup // initialise processor
diff --git a/arch/arm64/kernel/setup.c b/arch/arm64/kernel/setup.c
index 3852405d70b5..1783b38cf4c0 100644
--- a/arch/arm64/kernel/setup.c
+++ b/arch/arm64/kernel/setup.c
@@ -63,9 +63,6 @@
#include <asm/efi.h>
#include <asm/virt.h>
-unsigned int processor_id;
-EXPORT_SYMBOL(processor_id);
-
unsigned long elf_hwcap __read_mostly;
EXPORT_SYMBOL_GPL(elf_hwcap);