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authorStefan Popa <stefan.popa@analog.com>2019-02-04 12:30:15 +0200
committerJonathan Cameron <Jonathan.Cameron@huawei.com>2019-02-09 18:46:01 +0000
commite9517dffd1d5adf575a4ad9a231a68d48dcc5e6b (patch)
treec81b6ec52cd1bb7122112d34448830156d0db905 /samples/bpf/tcbpf1_kern.c
parentcbd5dd387afab8511e055d0487e1ef747e7f72b5 (diff)
iio: adc: ad7768-1: Add support for setting the sampling frequency
The AD7768-1 core ADC receives a master clock signal (MCLK). The MCLK frequency combined with the MCLK division and the digital filter decimation rates, determines the sampling frequency. Along with MCLK_DIV, the power mode is also configured according to datasheet recommendations. From user space, available sampling frequencies can be read. However, it is not required for an exact value to be entered, since the driver will look for the closest available match. When the device configuration changes (for example, if the filter decimation rate changes), a SYNC_IN pulse is required. Signed-off-by: Stefan Popa <stefan.popa@analog.com> Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
Diffstat (limited to 'samples/bpf/tcbpf1_kern.c')
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