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authorTodd Fujinaka <todd.fujinaka@intel.com>2014-07-10 01:47:15 -0700
committerDavid S. Miller <davem@davemloft.net>2014-07-10 01:48:28 -0700
commit948264879b6894dc389a44b99fae4f0b72932619 (patch)
treebcec9d0dd4a6ddca75038cbc44227fb25e05099e /lib/cordic.c
parentb4df480f68ae03b5dd4ab0db56536fbcec741705 (diff)
igb: Workaround for i210 Errata 25: Slow System Clock
On some devices, the internal PLL circuit occasionally provides the wrong clock frequency after power up. The probability of failure is less than one failure per 1000 power cycles. When the failure occurs, the internal clock frequency is around 1/20 of the correct frequency. Cc: stable <stable@vger.kernel.org> Signed-off-by: Todd Fujinaka <todd.fujinaka@intel.com> Tested-by: Aaron Brown <aaron.f.brown@intel.com> Signed-off-by: Jeff Kirsher <jeffrey.t.kirsher@intel.com> Signed-off-by: David S. Miller <davem@davemloft.net>
Diffstat (limited to 'lib/cordic.c')
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