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authorZhao Yakui <yakui.zhao@intel.com>2009-09-10 15:45:49 +0800
committerEric Anholt <eric@anholt.net>2009-09-10 11:31:04 -0700
commitbb66c5122b4300b475b585fffb811311f39f5431 (patch)
tree0d356b75e3d0e9002bf40df02b400bc137e8b4f3 /fs/reiserfs
parente270846fa7c350712553d767e61cf8b3bbfbd58a (diff)
drm/i915: Write zero to DPLL_MD Reg for non-SDVO output
When the output device is LVDS, maybe the pixel clock of adjusted_mode will be less than that in mode. In such case it will set the incorrect multipler factor in DPLL_MD register. So the dpll_md_reg will be reset when the output type is non-SDVO https://bugs.freedesktop.org/show_bug.cgi?id=22761 Signed-off-by: Zhao Yakui <yakui.zhao@intel.com> Reviewd-by: Eric Anholt <eric@anholt.net> Signed-off-by: Eric Anholt <eric@anholt.net>
Diffstat (limited to 'fs/reiserfs')
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