diff options
| author | Jonathan Marek <jonathan@marek.ca> | 2021-05-13 13:13:58 -0400 |
|---|---|---|
| committer | Rob Clark <robdclark@chromium.org> | 2021-06-08 11:26:45 -0700 |
| commit | b4387eaf3821a4c4241ac3a556e13244eb1fdaa5 (patch) | |
| tree | eb6b2b1811b0d5ac70d0fe67797a35196e3b4c20 /drivers | |
| parent | 408434036958699a7f50ddec984f7ba33e11a8f5 (diff) | |
drm/msm/a6xx: fix incorrectly set uavflagprd_inv field for A650
Value was shifted in the wrong direction, resulting in the field always
being zero, which is incorrect for A650.
Fixes: d0bac4e9cd66 ("drm/msm/a6xx: set ubwc config for A640 and A650")
Signed-off-by: Jonathan Marek <jonathan@marek.ca>
Reviewed-by: Akhil P Oommen <akhilpo@codeaurora.org>
Link: https://lore.kernel.org/r/20210513171431.18632-4-jonathan@marek.ca
Signed-off-by: Rob Clark <robdclark@chromium.org>
Diffstat (limited to 'drivers')
| -rw-r--r-- | drivers/gpu/drm/msm/adreno/a6xx_gpu.c | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c b/drivers/gpu/drm/msm/adreno/a6xx_gpu.c index 9702bec14310..37ba111601cd 100644 --- a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c +++ b/drivers/gpu/drm/msm/adreno/a6xx_gpu.c @@ -596,7 +596,7 @@ static void a6xx_set_ubwc_config(struct msm_gpu *gpu) rgb565_predicator << 11 | amsbc << 4 | lower_bit << 1); gpu_write(gpu, REG_A6XX_TPL1_NC_MODE_CNTL, lower_bit << 1); gpu_write(gpu, REG_A6XX_SP_NC_MODE_CNTL, - uavflagprd_inv >> 4 | lower_bit << 1); + uavflagprd_inv << 4 | lower_bit << 1); gpu_write(gpu, REG_A6XX_UCHE_MODE_CNTL, lower_bit << 21); } |