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authorPeter De Schrijver <pdeschrijver@nvidia.com>2013-04-03 17:40:36 +0300
committerStephen Warren <swarren@nvidia.com>2013-04-04 16:10:33 -0600
commitdba4072a4a20b2986562cced98ce04a887614528 (patch)
tree68bfcbd1b984799bed2b75d262abe5789f4d4d40 /drivers/video/sunxvr2500.c
parent6a676fa0af4e2bd11ab3950e277e81a959a9a198 (diff)
clk: tegra: Refactor PLL programming code
Refactor the PLL programming code to make it useable by the new PLL types introduced by Tegra114. The following changes were done: * Split programming the PLL into updating m,n,p and updating cpcon * Move locking from _update_pll_cpcon() to clk_pll_set_rate() * Introduce _get_pll_mnp() helper * Move check for identical m,n,p values to clk_pll_set_rate() * struct tegra_clk_pll_freq_table will always contain the values as defined by the hardware. * Simplify the arguments to clk_pll_wait_for_lock() * Split _tegra_clk_register_pll() Signed-off-by: Peter De Schrijver <pdeschrijver@nvidia.com> Acked-by: Mike Turquette <mturquette@linaro.org> Signed-off-by: Stephen Warren <swarren@nvidia.com>
Diffstat (limited to 'drivers/video/sunxvr2500.c')
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