diff options
| author | Daniel Cotey <puff65537@bansheeslibrary.com> | 2012-09-15 06:06:20 -0700 |
|---|---|---|
| committer | Greg Kroah-Hartman <gregkh@linuxfoundation.org> | 2012-09-17 05:37:56 -0700 |
| commit | d5b4f42f8f87ad2f58cea6fd8b3ce419056132ed (patch) | |
| tree | 6ce7e1c002db9e3da05118c583063eebeaebe203 /drivers/staging/silicom | |
| parent | 97ef0a461ba82cb641ae53314997ce44161b749a (diff) | |
Staging: silicom: bp_mod.h: checkpatch tab and space cleanup
eleventh chunk of bp_mod.h's cleanup
Signed-off-by: Daniel Cotey <puff65537@bansheeslibrary.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
Diffstat (limited to 'drivers/staging/silicom')
| -rw-r--r-- | drivers/staging/silicom/bp_mod.h | 44 |
1 files changed, 22 insertions, 22 deletions
diff --git a/drivers/staging/silicom/bp_mod.h b/drivers/staging/silicom/bp_mod.h index 2862c5790c28..f59c061660fe 100644 --- a/drivers/staging/silicom/bp_mod.h +++ b/drivers/staging/silicom/bp_mod.h @@ -463,28 +463,28 @@ static inline unsigned int jiffies_to_msecs(const unsigned long j) (pid == SILICOM_PE2G4BPFi35ZX_SSID)) #define BP10G9_IF_SERIES(pid) \ -((pid==INTEL_PE210G2SPI9_SSID)|| \ -(pid==SILICOM_M1E10G2BPI9CX4_SSID)|| \ -(pid==SILICOM_M1E10G2BPI9SR_SSID)|| \ -(pid==SILICOM_M1E10G2BPI9LR_SSID)|| \ -(pid==SILICOM_M1E10G2BPI9T_SSID)|| \ -(pid==SILICOM_M2E10G2BPI9CX4_SSID)|| \ -(pid==SILICOM_M2E10G2BPI9SR_SSID)|| \ -(pid==SILICOM_M2E10G2BPI9LR_SSID)|| \ -(pid==SILICOM_M2E10G2BPI9T_SSID)|| \ -(pid==SILICOM_PE210G2BPI9CX4_SSID)|| \ -(pid==SILICOM_PE210G2BPI9SR_SSID)|| \ -(pid==SILICOM_PE210G2BPI9LR_SSID)|| \ -(pid==SILICOM_PE210G2DBi9SR_SSID)|| \ -(pid==SILICOM_PE210G2DBi9SRRB_SSID)|| \ -(pid==SILICOM_PE210G2DBi9LR_SSID)|| \ -(pid==SILICOM_PE210G2DBi9LRRB_SSID)|| \ -(pid==SILICOM_PE310G4DBi940SR_SSID)|| \ -(pid==SILICOM_PEG2BISC6_SSID)|| \ -(pid==SILICOM_PE310G4BPi9T_SSID)|| \ -(pid==SILICOM_PE310G4BPi9SR_SSID)|| \ -(pid==SILICOM_PE310G4BPi9LR_SSID)|| \ -(pid==SILICOM_PE210G2BPI9T_SSID)) + ((pid == INTEL_PE210G2SPI9_SSID) || \ + (pid == SILICOM_M1E10G2BPI9CX4_SSID) || \ + (pid == SILICOM_M1E10G2BPI9SR_SSID) || \ + (pid == SILICOM_M1E10G2BPI9LR_SSID) || \ + (pid == SILICOM_M1E10G2BPI9T_SSID) || \ + (pid == SILICOM_M2E10G2BPI9CX4_SSID) || \ + (pid == SILICOM_M2E10G2BPI9SR_SSID) || \ + (pid == SILICOM_M2E10G2BPI9LR_SSID) || \ + (pid == SILICOM_M2E10G2BPI9T_SSID) || \ + (pid == SILICOM_PE210G2BPI9CX4_SSID) || \ + (pid == SILICOM_PE210G2BPI9SR_SSID) || \ + (pid == SILICOM_PE210G2BPI9LR_SSID) || \ + (pid == SILICOM_PE210G2DBi9SR_SSID) || \ + (pid == SILICOM_PE210G2DBi9SRRB_SSID) || \ + (pid == SILICOM_PE210G2DBi9LR_SSID) || \ + (pid == SILICOM_PE210G2DBi9LRRB_SSID) || \ + (pid == SILICOM_PE310G4DBi940SR_SSID) || \ + (pid == SILICOM_PEG2BISC6_SSID) || \ + (pid == SILICOM_PE310G4BPi9T_SSID) || \ + (pid == SILICOM_PE310G4BPi9SR_SSID) || \ + (pid == SILICOM_PE310G4BPi9LR_SSID) || \ + (pid == SILICOM_PE210G2BPI9T_SSID)) /*******************************************************/ /* 1G INTERFACE ****************************************/ |