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authorPan Bian <bianpan2016@163.com>2021-01-20 20:50:05 -0800
committerHans de Goede <hdegoede@redhat.com>2021-02-02 19:33:44 +0100
commit745ed17a04f966406c8c27c8f992544336c06013 (patch)
tree8a895e5e2f981e1e20f841327c11971dbbfa0f36 /drivers/platform
parenteabe533904cbcb6c7df530fd807cf2a3c3567d35 (diff)
platform/x86: amd-pmc: put device on error paths
Put the PCI device rdev on error paths to fix potential reference count leaks. Signed-off-by: Pan Bian <bianpan2016@163.com> Link: https://lore.kernel.org/r/20210121045005.73342-1-bianpan2016@163.com Reviewed-by: Hans de Goede <hdegoede@redhat.com> Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Diffstat (limited to 'drivers/platform')
-rw-r--r--drivers/platform/x86/amd-pmc.c14
1 files changed, 11 insertions, 3 deletions
diff --git a/drivers/platform/x86/amd-pmc.c b/drivers/platform/x86/amd-pmc.c
index ef8342572463..b9da58ee9b1e 100644
--- a/drivers/platform/x86/amd-pmc.c
+++ b/drivers/platform/x86/amd-pmc.c
@@ -210,31 +210,39 @@ static int amd_pmc_probe(struct platform_device *pdev)
dev->dev = &pdev->dev;
rdev = pci_get_domain_bus_and_slot(0, 0, PCI_DEVFN(0, 0));
- if (!rdev || !pci_match_id(pmc_pci_ids, rdev))
+ if (!rdev || !pci_match_id(pmc_pci_ids, rdev)) {
+ pci_dev_put(rdev);
return -ENODEV;
+ }
dev->cpu_id = rdev->device;
err = pci_write_config_dword(rdev, AMD_PMC_SMU_INDEX_ADDRESS, AMD_PMC_BASE_ADDR_LO);
if (err) {
dev_err(dev->dev, "error writing to 0x%x\n", AMD_PMC_SMU_INDEX_ADDRESS);
+ pci_dev_put(rdev);
return pcibios_err_to_errno(err);
}
err = pci_read_config_dword(rdev, AMD_PMC_SMU_INDEX_DATA, &val);
- if (err)
+ if (err) {
+ pci_dev_put(rdev);
return pcibios_err_to_errno(err);
+ }
base_addr_lo = val & AMD_PMC_BASE_ADDR_HI_MASK;
err = pci_write_config_dword(rdev, AMD_PMC_SMU_INDEX_ADDRESS, AMD_PMC_BASE_ADDR_HI);
if (err) {
dev_err(dev->dev, "error writing to 0x%x\n", AMD_PMC_SMU_INDEX_ADDRESS);
+ pci_dev_put(rdev);
return pcibios_err_to_errno(err);
}
err = pci_read_config_dword(rdev, AMD_PMC_SMU_INDEX_DATA, &val);
- if (err)
+ if (err) {
+ pci_dev_put(rdev);
return pcibios_err_to_errno(err);
+ }
base_addr_hi = val & AMD_PMC_BASE_ADDR_LO_MASK;
pci_dev_put(rdev);