diff options
| author | Maxime Chevallier <maxime.chevallier@bootlin.com> | 2019-02-15 09:33:47 +0100 |
|---|---|---|
| committer | David S. Miller <davem@davemloft.net> | 2019-02-17 15:33:53 -0800 |
| commit | 56425638839cfb038adeba3fb5ff6a4466ec37f9 (patch) | |
| tree | 2a7e071db10c3b1a72901098ef80b9e7fe63e026 /drivers/net | |
| parent | a0bc653b1d48671caa9d22a44ff98050f8efd3ea (diff) | |
net: phy: marvell10g: Don't explicitly set Pause and Asym_Pause
The PHY core expects PHY drivers not to set Pause and Asym_Pause bits,
unless the driver only wants to specify one of them due to HW
limitation. In the case of the Marvell10g driver, we don't need to set
them.
Signed-off-by: Maxime Chevallier <maxime.chevallier@bootlin.com>
Suggested-by: Andrew Lunn <andrew@lunn.ch>
Reviewed-by: Andrew Lunn <andrew@lunn.ch>
Signed-off-by: David S. Miller <davem@davemloft.net>
Diffstat (limited to 'drivers/net')
| -rw-r--r-- | drivers/net/phy/marvell10g.c | 3 |
1 files changed, 0 insertions, 3 deletions
diff --git a/drivers/net/phy/marvell10g.c b/drivers/net/phy/marvell10g.c index b83eb19cf8bb..f9e0a2fc0277 100644 --- a/drivers/net/phy/marvell10g.c +++ b/drivers/net/phy/marvell10g.c @@ -242,9 +242,6 @@ static int mv3310_config_init(struct phy_device *phydev) phydev->interface != PHY_INTERFACE_MODE_10GKR) return -ENODEV; - __set_bit(ETHTOOL_LINK_MODE_Pause_BIT, phydev->supported); - __set_bit(ETHTOOL_LINK_MODE_Asym_Pause_BIT, phydev->supported); - if (phydev->c45_ids.devices_in_package & MDIO_DEVS_AN) { val = phy_read_mmd(phydev, MDIO_MMD_AN, MDIO_STAT1); if (val < 0) |