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authorXiaolei Li <xiaolei.li@mediatek.com>2017-06-23 15:12:25 +0800
committerBoris Brezillon <boris.brezillon@free-electrons.com>2017-06-25 16:54:01 +0200
commit88404312556c10e4bcd1aeeb75b1b7e9e3226160 (patch)
treea5651ff28ea231e694d0e651212bdbe08853914d /drivers/mtd/nand/sharpsl.c
parent188986c70e09f0f3cd88e6fe14c89e439474e3ec (diff)
mtd: nand: mtk: disable ecc irq when writing page with hwecc
Currently, ecc encode irq is enabled when writing page with hwecc, but we actually do not wait for this irq done. Because NFI and ECC work in parallel, nfi irq and ecc irq almost come together. Now, there are two steps to check whether page data are totally written. First, wait for nfi irq INTR_AHB_DONE. This is to ensure all data in RAM are received by NFI. Second, polling the register NFI_ADDRCNTR till all data include ecc parity data runtime generated by ECC are sent to NAND device. So, it is redunant to enable ecc irq without waiting for it. Signed-off-by: Xiaolei Li <xiaolei.li@mediatek.com> Signed-off-by: Boris Brezillon <boris.brezillon@free-electrons.com>
Diffstat (limited to 'drivers/mtd/nand/sharpsl.c')
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