diff options
| author | Mauro Carvalho Chehab <mchehab+samsung@kernel.org> | 2019-08-22 11:06:32 -0300 |
|---|---|---|
| committer | Mauro Carvalho Chehab <mchehab+samsung@kernel.org> | 2019-08-26 14:08:50 -0300 |
| commit | cce8ccca80d8388982133192d0a6d9dc2e8ed712 (patch) | |
| tree | 4e37956f86eba2c619fe2a4d56af0b5c993411ae /drivers/media/pci | |
| parent | 093347abc7a4e0490e3c962ecbde2dc272a8f708 (diff) | |
media: use the BIT() macro
As warned by cppcheck:
[drivers/media/dvb-frontends/cx24123.c:434]: (error) Shifting signed 32-bit value by 31 bits is undefined behaviour
[drivers/media/pci/bt8xx/bttv-input.c:87]: (error) Shifting signed 32-bit value by 31 bits is undefined behaviour
[drivers/media/pci/bt8xx/bttv-input.c:98]: (error) Shifting signed 32-bit value by 31 bits is undefined behaviour
...
[drivers/media/v4l2-core/v4l2-ioctl.c:1391]: (error) Shifting signed 32-bit value by 31 bits is undefined behaviour
There are lots of places where we're doing 1 << 31. That's bad,
as, depending on the architecture, this has an undefined behavior.
The BIT() macro is already prepared to handle this, so, let's
just switch all "1 << number" macros by BIT(number) at the header files
with has 1 << 31.
Reviewed-by: Sylwester Nawrocki <s.nawrocki@samsung.com> # exynos4-is and s3c-camif
Reviewed-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com> # omap3isp, vsp1, xilinx, wl128x and ipu3
Reviewed-by: Benoit Parrot <bparrot@ti.com> # am437x and ti-vpe
Signed-off-by: Mauro Carvalho Chehab <mchehab+samsung@kernel.org>
Diffstat (limited to 'drivers/media/pci')
| -rw-r--r-- | drivers/media/pci/cobalt/cobalt-driver.h | 63 | ||||
| -rw-r--r-- | drivers/media/pci/ivtv/ivtv-irq.h | 28 | ||||
| -rw-r--r-- | drivers/media/pci/mantis/mantis_reg.h | 152 | ||||
| -rw-r--r-- | drivers/media/pci/solo6x10/solo6x10-regs.h | 286 |
4 files changed, 266 insertions, 263 deletions
diff --git a/drivers/media/pci/cobalt/cobalt-driver.h b/drivers/media/pci/cobalt/cobalt-driver.h index 429bee4ef79c..bca68572b324 100644 --- a/drivers/media/pci/cobalt/cobalt-driver.h +++ b/drivers/media/pci/cobalt/cobalt-driver.h @@ -11,6 +11,7 @@ #ifndef COBALT_DRIVER_H #define COBALT_DRIVER_H +#include <linux/bitops.h> #include <linux/module.h> #include <linux/pci.h> #include <linux/spinlock.h> @@ -61,37 +62,37 @@ #define COBALT_CLK 50000000 /* System status register */ -#define COBALT_SYSSTAT_DIP0_MSK (1 << 0) -#define COBALT_SYSSTAT_DIP1_MSK (1 << 1) -#define COBALT_SYSSTAT_HSMA_PRSNTN_MSK (1 << 2) -#define COBALT_SYSSTAT_FLASH_RDYBSYN_MSK (1 << 3) -#define COBALT_SYSSTAT_VI0_5V_MSK (1 << 4) -#define COBALT_SYSSTAT_VI0_INT1_MSK (1 << 5) -#define COBALT_SYSSTAT_VI0_INT2_MSK (1 << 6) -#define COBALT_SYSSTAT_VI0_LOST_DATA_MSK (1 << 7) -#define COBALT_SYSSTAT_VI1_5V_MSK (1 << 8) -#define COBALT_SYSSTAT_VI1_INT1_MSK (1 << 9) -#define COBALT_SYSSTAT_VI1_INT2_MSK (1 << 10) -#define COBALT_SYSSTAT_VI1_LOST_DATA_MSK (1 << 11) -#define COBALT_SYSSTAT_VI2_5V_MSK (1 << 12) -#define COBALT_SYSSTAT_VI2_INT1_MSK (1 << 13) -#define COBALT_SYSSTAT_VI2_INT2_MSK (1 << 14) -#define COBALT_SYSSTAT_VI2_LOST_DATA_MSK (1 << 15) -#define COBALT_SYSSTAT_VI3_5V_MSK (1 << 16) -#define COBALT_SYSSTAT_VI3_INT1_MSK (1 << 17) -#define COBALT_SYSSTAT_VI3_INT2_MSK (1 << 18) -#define COBALT_SYSSTAT_VI3_LOST_DATA_MSK (1 << 19) -#define COBALT_SYSSTAT_VIHSMA_5V_MSK (1 << 20) -#define COBALT_SYSSTAT_VIHSMA_INT1_MSK (1 << 21) -#define COBALT_SYSSTAT_VIHSMA_INT2_MSK (1 << 22) -#define COBALT_SYSSTAT_VIHSMA_LOST_DATA_MSK (1 << 23) -#define COBALT_SYSSTAT_VOHSMA_INT1_MSK (1 << 24) -#define COBALT_SYSSTAT_VOHSMA_PLL_LOCKED_MSK (1 << 25) -#define COBALT_SYSSTAT_VOHSMA_LOST_DATA_MSK (1 << 26) -#define COBALT_SYSSTAT_AUD_PLL_LOCKED_MSK (1 << 28) -#define COBALT_SYSSTAT_AUD_IN_LOST_DATA_MSK (1 << 29) -#define COBALT_SYSSTAT_AUD_OUT_LOST_DATA_MSK (1 << 30) -#define COBALT_SYSSTAT_PCIE_SMBCLK_MSK (1 << 31) +#define COBALT_SYSSTAT_DIP0_MSK BIT(0) +#define COBALT_SYSSTAT_DIP1_MSK BIT(1) +#define COBALT_SYSSTAT_HSMA_PRSNTN_MSK BIT(2) +#define COBALT_SYSSTAT_FLASH_RDYBSYN_MSK BIT(3) +#define COBALT_SYSSTAT_VI0_5V_MSK BIT(4) +#define COBALT_SYSSTAT_VI0_INT1_MSK BIT(5) +#define COBALT_SYSSTAT_VI0_INT2_MSK BIT(6) +#define COBALT_SYSSTAT_VI0_LOST_DATA_MSK BIT(7) +#define COBALT_SYSSTAT_VI1_5V_MSK BIT(8) +#define COBALT_SYSSTAT_VI1_INT1_MSK BIT(9) +#define COBALT_SYSSTAT_VI1_INT2_MSK BIT(10) +#define COBALT_SYSSTAT_VI1_LOST_DATA_MSK BIT(11) +#define COBALT_SYSSTAT_VI2_5V_MSK BIT(12) +#define COBALT_SYSSTAT_VI2_INT1_MSK BIT(13) +#define COBALT_SYSSTAT_VI2_INT2_MSK BIT(14) +#define COBALT_SYSSTAT_VI2_LOST_DATA_MSK BIT(15) +#define COBALT_SYSSTAT_VI3_5V_MSK BIT(16) +#define COBALT_SYSSTAT_VI3_INT1_MSK BIT(17) +#define COBALT_SYSSTAT_VI3_INT2_MSK BIT(18) +#define COBALT_SYSSTAT_VI3_LOST_DATA_MSK BIT(19) +#define COBALT_SYSSTAT_VIHSMA_5V_MSK BIT(20) +#define COBALT_SYSSTAT_VIHSMA_INT1_MSK BIT(21) +#define COBALT_SYSSTAT_VIHSMA_INT2_MSK BIT(22) +#define COBALT_SYSSTAT_VIHSMA_LOST_DATA_MSK BIT(23) +#define COBALT_SYSSTAT_VOHSMA_INT1_MSK BIT(24) +#define COBALT_SYSSTAT_VOHSMA_PLL_LOCKED_MSK BIT(25) +#define COBALT_SYSSTAT_VOHSMA_LOST_DATA_MSK BIT(26) +#define COBALT_SYSSTAT_AUD_PLL_LOCKED_MSK BIT(28) +#define COBALT_SYSSTAT_AUD_IN_LOST_DATA_MSK BIT(29) +#define COBALT_SYSSTAT_AUD_OUT_LOST_DATA_MSK BIT(30) +#define COBALT_SYSSTAT_PCIE_SMBCLK_MSK BIT(31) /* Cobalt memory map */ #define COBALT_I2C_0_BASE 0x0 diff --git a/drivers/media/pci/ivtv/ivtv-irq.h b/drivers/media/pci/ivtv/ivtv-irq.h index 7d2f45e2b83c..b8b0703a1c82 100644 --- a/drivers/media/pci/ivtv/ivtv-irq.h +++ b/drivers/media/pci/ivtv/ivtv-irq.h @@ -10,20 +10,20 @@ #ifndef IVTV_IRQ_H #define IVTV_IRQ_H -#define IVTV_IRQ_ENC_START_CAP (0x1 << 31) -#define IVTV_IRQ_ENC_EOS (0x1 << 30) -#define IVTV_IRQ_ENC_VBI_CAP (0x1 << 29) -#define IVTV_IRQ_ENC_VIM_RST (0x1 << 28) -#define IVTV_IRQ_ENC_DMA_COMPLETE (0x1 << 27) -#define IVTV_IRQ_ENC_PIO_COMPLETE (0x1 << 25) -#define IVTV_IRQ_DEC_AUD_MODE_CHG (0x1 << 24) -#define IVTV_IRQ_DEC_DATA_REQ (0x1 << 22) -#define IVTV_IRQ_DEC_DMA_COMPLETE (0x1 << 20) -#define IVTV_IRQ_DEC_VBI_RE_INSERT (0x1 << 19) -#define IVTV_IRQ_DMA_ERR (0x1 << 18) -#define IVTV_IRQ_DMA_WRITE (0x1 << 17) -#define IVTV_IRQ_DMA_READ (0x1 << 16) -#define IVTV_IRQ_DEC_VSYNC (0x1 << 10) +#define IVTV_IRQ_ENC_START_CAP BIT(31) +#define IVTV_IRQ_ENC_EOS BIT(30) +#define IVTV_IRQ_ENC_VBI_CAP BIT(29) +#define IVTV_IRQ_ENC_VIM_RST BIT(28) +#define IVTV_IRQ_ENC_DMA_COMPLETE BIT(27) +#define IVTV_IRQ_ENC_PIO_COMPLETE BIT(25) +#define IVTV_IRQ_DEC_AUD_MODE_CHG BIT(24) +#define IVTV_IRQ_DEC_DATA_REQ BIT(22) +#define IVTV_IRQ_DEC_DMA_COMPLETE BIT(20) +#define IVTV_IRQ_DEC_VBI_RE_INSERT BIT(19) +#define IVTV_IRQ_DMA_ERR BIT(18) +#define IVTV_IRQ_DMA_WRITE BIT(17) +#define IVTV_IRQ_DMA_READ BIT(16) +#define IVTV_IRQ_DEC_VSYNC BIT(10) /* IRQ Masks */ #define IVTV_IRQ_MASK_INIT (IVTV_IRQ_DMA_ERR|IVTV_IRQ_ENC_DMA_COMPLETE|\ diff --git a/drivers/media/pci/mantis/mantis_reg.h b/drivers/media/pci/mantis/mantis_reg.h index 67a80e42b5c7..a1e66ef6ac2f 100644 --- a/drivers/media/pci/mantis/mantis_reg.h +++ b/drivers/media/pci/mantis/mantis_reg.h @@ -14,44 +14,44 @@ #define MANTIS_INT_MASK 0x04 #define MANTIS_INT_RISCSTAT (0x0f << 28) -#define MANTIS_INT_RISCEN (0x01 << 27) -#define MANTIS_INT_I2CRACK (0x01 << 26) +#define MANTIS_INT_RISCEN BIT(27) +#define MANTIS_INT_I2CRACK BIT(26) /* #define MANTIS_INT_GPIF (0xff << 12) */ -#define MANTIS_INT_PCMCIA7 (0x01 << 19) -#define MANTIS_INT_PCMCIA6 (0x01 << 18) -#define MANTIS_INT_PCMCIA5 (0x01 << 17) -#define MANTIS_INT_PCMCIA4 (0x01 << 16) -#define MANTIS_INT_PCMCIA3 (0x01 << 15) -#define MANTIS_INT_PCMCIA2 (0x01 << 14) -#define MANTIS_INT_PCMCIA1 (0x01 << 13) -#define MANTIS_INT_PCMCIA0 (0x01 << 12) -#define MANTIS_INT_IRQ1 (0x01 << 11) -#define MANTIS_INT_IRQ0 (0x01 << 10) -#define MANTIS_INT_OCERR (0x01 << 8) -#define MANTIS_INT_PABORT (0x01 << 7) -#define MANTIS_INT_RIPERR (0x01 << 6) -#define MANTIS_INT_PPERR (0x01 << 5) -#define MANTIS_INT_FTRGT (0x01 << 3) -#define MANTIS_INT_RISCI (0x01 << 1) -#define MANTIS_INT_I2CDONE (0x01 << 0) +#define MANTIS_INT_PCMCIA7 BIT(19) +#define MANTIS_INT_PCMCIA6 BIT(18) +#define MANTIS_INT_PCMCIA5 BIT(17) +#define MANTIS_INT_PCMCIA4 BIT(16) +#define MANTIS_INT_PCMCIA3 BIT(15) +#define MANTIS_INT_PCMCIA2 BIT(14) +#define MANTIS_INT_PCMCIA1 BIT(13) +#define MANTIS_INT_PCMCIA0 BIT(12) +#define MANTIS_INT_IRQ1 BIT(11) +#define MANTIS_INT_IRQ0 BIT(10) +#define MANTIS_INT_OCERR BIT(8) +#define MANTIS_INT_PABORT BIT(7) +#define MANTIS_INT_RIPERR BIT(6) +#define MANTIS_INT_PPERR BIT(5) +#define MANTIS_INT_FTRGT BIT(3) +#define MANTIS_INT_RISCI BIT(1) +#define MANTIS_INT_I2CDONE BIT(0) /* DMA */ #define MANTIS_DMA_CTL 0x08 #define MANTIS_GPIF_RD (0xff << 24) #define MANTIS_GPIF_WR (0xff << 16) -#define MANTIS_CPU_DO (0x01 << 10) -#define MANTIS_DRV_DO (0x01 << 9) -#define MANTIS_I2C_RD (0x01 << 7) -#define MANTIS_I2C_WR (0x01 << 6) -#define MANTIS_DCAP_MODE (0x01 << 5) +#define MANTIS_CPU_DO BIT(10) +#define MANTIS_DRV_DO BIT(9) +#define MANTIS_I2C_RD BIT(7) +#define MANTIS_I2C_WR BIT(6) +#define MANTIS_DCAP_MODE BIT(5) #define MANTIS_FIFO_TP_4 (0x00 << 3) #define MANTIS_FIFO_TP_8 (0x01 << 3) #define MANTIS_FIFO_TP_16 (0x02 << 3) -#define MANTIS_FIFO_EN (0x01 << 2) -#define MANTIS_DCAP_EN (0x01 << 1) -#define MANTIS_RISC_EN (0x01 << 0) +#define MANTIS_FIFO_EN BIT(2) +#define MANTIS_DCAP_EN BIT(1) +#define MANTIS_RISC_EN BIT(0) /* DEBUG */ #define MANTIS_DEBUGREG 0x0c @@ -68,8 +68,8 @@ #define MANTIS_I2C_RATE_2 (0x01 << 6) #define MANTIS_I2C_RATE_3 (0x02 << 6) #define MANTIS_I2C_RATE_4 (0x03 << 6) -#define MANTIS_I2C_STOP (0x01 << 5) -#define MANTIS_I2C_PGMODE (0x01 << 3) +#define MANTIS_I2C_STOP BIT(5) +#define MANTIS_I2C_PGMODE BIT(3) /* DATA */ #define MANTIS_CMD_DATA_R1 0x20 @@ -85,77 +85,77 @@ #define MANTIS_CMD_DATA_4 (0xff << 0) #define MANTIS_CONTROL 0x28 -#define MANTIS_DET (0x01 << 7) -#define MANTIS_DAT_CF_EN (0x01 << 6) +#define MANTIS_DET BIT(7) +#define MANTIS_DAT_CF_EN BIT(6) #define MANTIS_ACS (0x03 << 4) -#define MANTIS_VCCEN (0x01 << 3) -#define MANTIS_BYPASS (0x01 << 2) -#define MANTIS_MRST (0x01 << 1) -#define MANTIS_CRST_INT (0x01 << 0) +#define MANTIS_VCCEN BIT(3) +#define MANTIS_BYPASS BIT(2) +#define MANTIS_MRST BIT(1) +#define MANTIS_CRST_INT BIT(0) #define MANTIS_GPIF_CFGSLA 0x84 #define MANTIS_GPIF_WAITSMPL (0x07 << 28) -#define MANTIS_GPIF_BYTEADDRSUB (0x01 << 25) -#define MANTIS_GPIF_WAITPOL (0x01 << 24) +#define MANTIS_GPIF_BYTEADDRSUB BIT(25) +#define MANTIS_GPIF_WAITPOL BIT(24) #define MANTIS_GPIF_NCDELAY (0x07 << 20) #define MANTIS_GPIF_RW2CSDELAY (0x07 << 16) -#define MANTIS_GPIF_SLFTIMEDMODE (0x01 << 15) +#define MANTIS_GPIF_SLFTIMEDMODE BIT(15) #define MANTIS_GPIF_SLFTIMEDDELY (0x7f << 8) #define MANTIS_GPIF_DEVTYPE (0x07 << 4) -#define MANTIS_GPIF_BIGENDIAN (0x01 << 3) +#define MANTIS_GPIF_BIGENDIAN BIT(3) #define MANTIS_GPIF_FETCHCMD (0x03 << 1) -#define MANTIS_GPIF_HWORDDEV (0x01 << 0) +#define MANTIS_GPIF_HWORDDEV BIT(0) #define MANTIS_GPIF_WSTOPER 0x90 -#define MANTIS_GPIF_WSTOPERWREN3 (0x01 << 31) -#define MANTIS_GPIF_PARBOOTN (0x01 << 29) +#define MANTIS_GPIF_WSTOPERWREN3 BIT(31) +#define MANTIS_GPIF_PARBOOTN BIT(29) #define MANTIS_GPIF_WSTOPERSLID3 (0x1f << 24) -#define MANTIS_GPIF_WSTOPERWREN2 (0x01 << 23) +#define MANTIS_GPIF_WSTOPERWREN2 BIT(23) #define MANTIS_GPIF_WSTOPERSLID2 (0x1f << 16) -#define MANTIS_GPIF_WSTOPERWREN1 (0x01 << 15) +#define MANTIS_GPIF_WSTOPERWREN1 BIT(15) #define MANTIS_GPIF_WSTOPERSLID1 (0x1f << 8) -#define MANTIS_GPIF_WSTOPERWREN0 (0x01 << 7) +#define MANTIS_GPIF_WSTOPERWREN0 BIT(7) #define MANTIS_GPIF_WSTOPERSLID0 (0x1f << 0) #define MANTIS_GPIF_CS2RW 0x94 -#define MANTIS_GPIF_CS2RWWREN3 (0x01 << 31) +#define MANTIS_GPIF_CS2RWWREN3 BIT(31) #define MANTIS_GPIF_CS2RWDELY3 (0x3f << 24) -#define MANTIS_GPIF_CS2RWWREN2 (0x01 << 23) +#define MANTIS_GPIF_CS2RWWREN2 BIT(23) #define MANTIS_GPIF_CS2RWDELY2 (0x3f << 16) -#define MANTIS_GPIF_CS2RWWREN1 (0x01 << 15) +#define MANTIS_GPIF_CS2RWWREN1 BIT(15) #define MANTIS_GPIF_CS2RWDELY1 (0x3f << 8) -#define MANTIS_GPIF_CS2RWWREN0 (0x01 << 7) +#define MANTIS_GPIF_CS2RWWREN0 BIT(7) #define MANTIS_GPIF_CS2RWDELY0 (0x3f << 0) #define MANTIS_GPIF_IRQCFG 0x98 -#define MANTIS_GPIF_IRQPOL (0x01 << 8) -#define MANTIS_MASK_WRACK (0x01 << 7) -#define MANTIS_MASK_BRRDY (0x01 << 6) -#define MANTIS_MASK_OVFLW (0x01 << 5) -#define MANTIS_MASK_OTHERR (0x01 << 4) -#define MANTIS_MASK_WSTO (0x01 << 3) -#define MANTIS_MASK_EXTIRQ (0x01 << 2) -#define MANTIS_MASK_PLUGIN (0x01 << 1) -#define MANTIS_MASK_PLUGOUT (0x01 << 0) +#define MANTIS_GPIF_IRQPOL BIT(8) +#define MANTIS_MASK_WRACK BIT(7) +#define MANTIS_MASK_BRRDY BIT(6) +#define MANTIS_MASK_OVFLW BIT(5) +#define MANTIS_MASK_OTHERR BIT(4) +#define MANTIS_MASK_WSTO BIT(3) +#define MANTIS_MASK_EXTIRQ BIT(2) +#define MANTIS_MASK_PLUGIN BIT(1) +#define MANTIS_MASK_PLUGOUT BIT(0) #define MANTIS_GPIF_STATUS 0x9c -#define MANTIS_SBUF_KILLOP (0x01 << 15) -#define MANTIS_SBUF_OPDONE (0x01 << 14) -#define MANTIS_SBUF_EMPTY (0x01 << 13) -#define MANTIS_GPIF_DETSTAT (0x01 << 9) -#define MANTIS_GPIF_INTSTAT (0x01 << 8) -#define MANTIS_GPIF_WRACK (0x01 << 7) -#define MANTIS_GPIF_BRRDY (0x01 << 6) -#define MANTIS_SBUF_OVFLW (0x01 << 5) -#define MANTIS_GPIF_OTHERR (0x01 << 4) -#define MANTIS_SBUF_WSTO (0x01 << 3) -#define MANTIS_GPIF_EXTIRQ (0x01 << 2) -#define MANTIS_CARD_PLUGIN (0x01 << 1) -#define MANTIS_CARD_PLUGOUT (0x01 << 0) +#define MANTIS_SBUF_KILLOP BIT(15) +#define MANTIS_SBUF_OPDONE BIT(14) +#define MANTIS_SBUF_EMPTY BIT(13) +#define MANTIS_GPIF_DETSTAT BIT(9) +#define MANTIS_GPIF_INTSTAT BIT(8) +#define MANTIS_GPIF_WRACK BIT(7) +#define MANTIS_GPIF_BRRDY BIT(6) +#define MANTIS_SBUF_OVFLW BIT(5) +#define MANTIS_GPIF_OTHERR BIT(4) +#define MANTIS_SBUF_WSTO BIT(3) +#define MANTIS_GPIF_EXTIRQ BIT(2) +#define MANTIS_CARD_PLUGIN BIT(1) +#define MANTIS_CARD_PLUGOUT BIT(0) #define MANTIS_GPIF_BRADDR 0xa0 -#define MANTIS_GPIF_PCMCIAREG (0x01 << 27) -#define MANTIS_GPIF_PCMCIAIOM (0x01 << 26) +#define MANTIS_GPIF_PCMCIAREG BIT(27) +#define MANTIS_GPIF_PCMCIAIOM BIT(26) #define MANTIS_GPIF_BR_ADDR (0xfffffff << 0) #define MANTIS_GPIF_BRBYTES 0xa4 @@ -167,9 +167,9 @@ #define MANTIS_CARD_RESET 0xac #define MANTIS_GPIF_ADDR 0xb0 -#define MANTIS_GPIF_HIFRDWRN (0x01 << 31) -#define MANTIS_GPIF_PCMCIAREG (0x01 << 27) -#define MANTIS_GPIF_PCMCIAIOM (0x01 << 26) +#define MANTIS_GPIF_HIFRDWRN BIT(31) +#define MANTIS_GPIF_PCMCIAREG BIT(27) +#define MANTIS_GPIF_PCMCIAIOM BIT(26) #define MANTIS_GPIF_HIFADDR (0xfffffff << 0) #define MANTIS_GPIF_DOUT 0xb4 diff --git a/drivers/media/pci/solo6x10/solo6x10-regs.h b/drivers/media/pci/solo6x10/solo6x10-regs.h index d88cc02d01d3..804505d01b25 100644 --- a/drivers/media/pci/solo6x10/solo6x10-regs.h +++ b/drivers/media/pci/solo6x10/solo6x10-regs.h @@ -12,6 +12,8 @@ #ifndef __SOLO6X10_REGISTERS_H #define __SOLO6X10_REGISTERS_H +#include <linux/bitops.h> + #include "solo6x10-offsets.h" /* Global 6010 system configuration */ @@ -32,17 +34,17 @@ #define SOLO_DMA_CTRL_REFRESH_CYCLE(n) ((n)<<8) /* 0=16/32MB, 1=32/64MB, 2=64/128MB, 3=128/256MB */ #define SOLO_DMA_CTRL_SDRAM_SIZE(n) ((n)<<6) -#define SOLO_DMA_CTRL_SDRAM_CLK_INVERT (1<<5) -#define SOLO_DMA_CTRL_STROBE_SELECT (1<<4) -#define SOLO_DMA_CTRL_READ_DATA_SELECT (1<<3) -#define SOLO_DMA_CTRL_READ_CLK_SELECT (1<<2) +#define SOLO_DMA_CTRL_SDRAM_CLK_INVERT BIT(5) +#define SOLO_DMA_CTRL_STROBE_SELECT BIT(4) +#define SOLO_DMA_CTRL_READ_DATA_SELECT BIT(3) +#define SOLO_DMA_CTRL_READ_CLK_SELECT BIT(2) #define SOLO_DMA_CTRL_LATENCY(n) ((n)<<0) /* Some things we set in this are undocumented. Why Softlogic?!?! */ #define SOLO_DMA_CTRL1 0x0008 #define SOLO_SYS_VCLK 0x000C -#define SOLO_VCLK_INVERT (1<<22) +#define SOLO_VCLK_INVERT BIT(22) /* 0=sys_clk/4, 1=sys_clk/2, 2=clk_in/2 of system input */ #define SOLO_VCLK_SELECT(n) ((n)<<20) #define SOLO_VCLK_VIN1415_DELAY(n) ((n)<<14) @@ -56,22 +58,22 @@ #define SOLO_IRQ_STAT 0x0010 #define SOLO_IRQ_MASK 0x0014 -#define SOLO_IRQ_P2M(n) (1<<((n)+17)) -#define SOLO_IRQ_GPIO (1<<16) -#define SOLO_IRQ_VIDEO_LOSS (1<<15) -#define SOLO_IRQ_VIDEO_IN (1<<14) -#define SOLO_IRQ_MOTION (1<<13) -#define SOLO_IRQ_ATA_CMD (1<<12) -#define SOLO_IRQ_ATA_DIR (1<<11) -#define SOLO_IRQ_PCI_ERR (1<<10) -#define SOLO_IRQ_PS2_1 (1<<9) -#define SOLO_IRQ_PS2_0 (1<<8) -#define SOLO_IRQ_SPI (1<<7) -#define SOLO_IRQ_IIC (1<<6) -#define SOLO_IRQ_UART(n) (1<<((n) + 4)) -#define SOLO_IRQ_G723 (1<<3) -#define SOLO_IRQ_DECODER (1<<1) -#define SOLO_IRQ_ENCODER (1<<0) +#define SOLO_IRQ_P2M(n) BIT((n) + 17) +#define SOLO_IRQ_GPIO BIT(16) +#define SOLO_IRQ_VIDEO_LOSS BIT(15) +#define SOLO_IRQ_VIDEO_IN BIT(14) +#define SOLO_IRQ_MOTION BIT(13) +#define SOLO_IRQ_ATA_CMD BIT(12) +#define SOLO_IRQ_ATA_DIR BIT(11) +#define SOLO_IRQ_PCI_ERR BIT(10) +#define SOLO_IRQ_PS2_1 BIT(9) +#define SOLO_IRQ_PS2_0 BIT(8) +#define SOLO_IRQ_SPI BIT(7) +#define SOLO_IRQ_IIC BIT(6) +#define SOLO_IRQ_UART(n) BIT((n) + 4) +#define SOLO_IRQ_G723 BIT(3) +#define SOLO_IRQ_DECODER BIT(1) +#define SOLO_IRQ_ENCODER BIT(0) #define SOLO_CHIP_OPTION 0x001C #define SOLO_CHIP_ID_MASK 0x00000007 @@ -79,11 +81,11 @@ #define SOLO_PLL_CONFIG 0x0020 /* 6110 Only */ #define SOLO_EEPROM_CTRL 0x0060 -#define SOLO_EEPROM_ACCESS_EN (1<<7) -#define SOLO_EEPROM_CS (1<<3) -#define SOLO_EEPROM_CLK (1<<2) -#define SOLO_EEPROM_DO (1<<1) -#define SOLO_EEPROM_DI (1<<0) +#define SOLO_EEPROM_ACCESS_EN BIT(7) +#define SOLO_EEPROM_CS BIT(3) +#define SOLO_EEPROM_CLK BIT(2) +#define SOLO_EEPROM_DO BIT(1) +#define SOLO_EEPROM_DI BIT(0) #define SOLO_EEPROM_ENABLE (SOLO_EEPROM_ACCESS_EN | SOLO_EEPROM_CS) #define SOLO_PCI_ERR 0x0070 @@ -102,13 +104,13 @@ #define SOLO_P2M_CONFIG(n) (0x0080 + ((n)*0x20)) #define SOLO_P2M_DMA_INTERVAL(n) ((n)<<6)/* N*32 clocks */ -#define SOLO_P2M_CSC_BYTE_REORDER (1<<5) /* BGR -> RGB */ +#define SOLO_P2M_CSC_BYTE_REORDER BIT(5) /* BGR -> RGB */ /* 0:r=[14:10] g=[9:5] b=[4:0], 1:r=[15:11] g=[10:5] b=[4:0] */ -#define SOLO_P2M_CSC_16BIT_565 (1<<4) -#define SOLO_P2M_UV_SWAP (1<<3) -#define SOLO_P2M_PCI_MASTER_MODE (1<<2) -#define SOLO_P2M_DESC_INTR_OPT (1<<1) /* 1:Empty, 0:Each */ -#define SOLO_P2M_DESC_MODE (1<<0) +#define SOLO_P2M_CSC_16BIT_565 BIT(4) +#define SOLO_P2M_UV_SWAP BIT(3) +#define SOLO_P2M_PCI_MASTER_MODE BIT(2) +#define SOLO_P2M_DESC_INTR_OPT BIT(1) /* 1:Empty, 0:Each */ +#define SOLO_P2M_DESC_MODE BIT(0) #define SOLO_P2M_DES_ADR(n) (0x0084 + ((n)*0x20)) @@ -116,7 +118,7 @@ #define SOLO_P2M_UPDATE_ID(n) ((n)<<0) #define SOLO_P2M_STATUS(n) (0x008C + ((n)*0x20)) -#define SOLO_P2M_COMMAND_DONE (1<<8) +#define SOLO_P2M_COMMAND_DONE BIT(8) #define SOLO_P2M_CURRENT_ID(stat) (0xff & (stat)) #define SOLO_P2M_CONTROL(n) (0x0090 + ((n)*0x20)) @@ -129,13 +131,13 @@ #define SOLO_P2M_BURST_128 2 #define SOLO_P2M_BURST_64 3 #define SOLO_P2M_BURST_32 4 -#define SOLO_P2M_CSC_16BIT (1<<6) /* 0:24bit, 1:16bit */ +#define SOLO_P2M_CSC_16BIT BIT(6) /* 0:24bit, 1:16bit */ /* 0:Y[0]<-0(OFF), 1:Y[0]<-1(ON), 2:Y[0]<-G[0], 3:Y[0]<-Bit[15] */ #define SOLO_P2M_ALPHA_MODE(n) ((n)<<4) -#define SOLO_P2M_CSC_ON (1<<3) -#define SOLO_P2M_INTERRUPT_REQ (1<<2) -#define SOLO_P2M_WRITE (1<<1) -#define SOLO_P2M_TRANS_ON (1<<0) +#define SOLO_P2M_CSC_ON BIT(3) +#define SOLO_P2M_INTERRUPT_REQ BIT(2) +#define SOLO_P2M_WRITE BIT(1) +#define SOLO_P2M_TRANS_ON BIT(0) #define SOLO_P2M_EXT_CFG(n) (0x0094 + ((n)*0x20)) #define SOLO_P2M_EXT_INC(n) ((n)<<20) @@ -157,9 +159,9 @@ #define SOLO_VI_PROG_MASK(n) ((n)<<0) #define SOLO_VI_FMT_CFG 0x0114 -#define SOLO_VI_FMT_CHECK_VCOUNT (1<<31) -#define SOLO_VI_FMT_CHECK_HCOUNT (1<<30) -#define SOLO_VI_FMT_TEST_SIGNAL (1<<28) +#define SOLO_VI_FMT_CHECK_VCOUNT BIT(31) +#define SOLO_VI_FMT_CHECK_HCOUNT BIT(30) +#define SOLO_VI_FMT_TEST_SIGNAL BIT(28) #define SOLO_VI_PAGE_SW 0x0118 #define SOLO_FI_INV_DISP_LIVE(n) ((n)<<8) @@ -171,7 +173,7 @@ #define SOLO_VI_ACT_I_P 0x011C #define SOLO_VI_ACT_I_S 0x0120 #define SOLO_VI_ACT_P 0x0124 -#define SOLO_VI_FI_INVERT (1<<31) +#define SOLO_VI_FI_INVERT BIT(31) #define SOLO_VI_H_START(n) ((n)<<21) #define SOLO_VI_V_START(n) ((n)<<11) #define SOLO_VI_V_STOP(n) ((n)<<0) @@ -184,8 +186,8 @@ #define DISP_PAGE(stat) ((stat) & 0x07) #define SOLO_VI_PB_CONFIG 0x0130 -#define SOLO_VI_PB_USER_MODE (1<<1) -#define SOLO_VI_PB_PAL (1<<0) +#define SOLO_VI_PB_USER_MODE BIT(1) +#define SOLO_VI_PB_PAL BIT(0) #define SOLO_VI_PB_RANGE_HV 0x0134 #define SOLO_VI_PB_HSIZE(h) ((h)<<12) #define SOLO_VI_PB_VSIZE(v) ((v)<<0) @@ -226,35 +228,35 @@ #define SOLO_VI_MOT_CTRL 0x0264 #define SOLO_VI_MOTION_FRAME_COUNT(n) ((n)<<24) #define SOLO_VI_MOTION_SAMPLE_LENGTH(n) ((n)<<16) -#define SOLO_VI_MOTION_INTR_START_STOP (1<<15) -#define SOLO_VI_MOTION_FREEZE_DATA (1<<14) +#define SOLO_VI_MOTION_INTR_START_STOP BIT(15) +#define SOLO_VI_MOTION_FREEZE_DATA BIT(14) #define SOLO_VI_MOTION_SAMPLE_COUNT(n) ((n)<<0) #define SOLO_VI_MOT_CLEAR 0x0268 #define SOLO_VI_MOT_STATUS 0x026C #define SOLO_VI_MOTION_CNT(n) ((n)<<0) #define SOLO_VI_MOTION_BORDER 0x0270 #define SOLO_VI_MOTION_BAR 0x0274 -#define SOLO_VI_MOTION_Y_SET (1<<29) -#define SOLO_VI_MOTION_Y_ADD (1<<28) -#define SOLO_VI_MOTION_CB_SET (1<<27) -#define SOLO_VI_MOTION_CB_ADD (1<<26) -#define SOLO_VI_MOTION_CR_SET (1<<25) -#define SOLO_VI_MOTION_CR_ADD (1<<24) +#define SOLO_VI_MOTION_Y_SET BIT(29) +#define SOLO_VI_MOTION_Y_ADD BIT(28) +#define SOLO_VI_MOTION_CB_SET BIT(27) +#define SOLO_VI_MOTION_CB_ADD BIT(26) +#define SOLO_VI_MOTION_CR_SET BIT(25) +#define SOLO_VI_MOTION_CR_ADD BIT(24) #define SOLO_VI_MOTION_Y_VALUE(v) ((v)<<16) #define SOLO_VI_MOTION_CB_VALUE(v) ((v)<<8) #define SOLO_VI_MOTION_CR_VALUE(v) ((v)<<0) #define SOLO_VO_FMT_ENC 0x0300 -#define SOLO_VO_SCAN_MODE_PROGRESSIVE (1<<31) -#define SOLO_VO_FMT_TYPE_PAL (1<<30) +#define SOLO_VO_SCAN_MODE_PROGRESSIVE BIT(31) +#define SOLO_VO_FMT_TYPE_PAL BIT(30) #define SOLO_VO_FMT_TYPE_NTSC 0 -#define SOLO_VO_USER_SET (1<<29) +#define SOLO_VO_USER_SET BIT(29) -#define SOLO_VO_FI_CHANGE (1<<20) -#define SOLO_VO_USER_COLOR_SET_VSYNC (1<<19) -#define SOLO_VO_USER_COLOR_SET_HSYNC (1<<18) -#define SOLO_VO_USER_COLOR_SET_NAH (1<<17) -#define SOLO_VO_USER_COLOR_SET_NAV (1<<16) +#define SOLO_VO_FI_CHANGE BIT(20) +#define SOLO_VO_USER_COLOR_SET_VSYNC BIT(19) +#define SOLO_VO_USER_COLOR_SET_HSYNC BIT(18) +#define SOLO_VO_USER_COLOR_SET_NAH BIT(17) +#define SOLO_VO_USER_COLOR_SET_NAV BIT(16) #define SOLO_VO_NA_COLOR_Y(Y) ((Y)<<8) #define SOLO_VO_NA_COLOR_CB(CB) (((CB)/16)<<4) #define SOLO_VO_NA_COLOR_CR(CR) (((CR)/16)<<0) @@ -270,32 +272,32 @@ #define SOLO_VO_V_STOP(n) ((n)<<0) #define SOLO_VO_RANGE_HV 0x030C -#define SOLO_VO_SYNC_INVERT (1<<24) -#define SOLO_VO_HSYNC_INVERT (1<<23) -#define SOLO_VO_VSYNC_INVERT (1<<22) +#define SOLO_VO_SYNC_INVERT BIT(24) +#define SOLO_VO_HSYNC_INVERT BIT(23) +#define SOLO_VO_VSYNC_INVERT BIT(22) #define SOLO_VO_H_LEN(n) ((n)<<11) #define SOLO_VO_V_LEN(n) ((n)<<0) #define SOLO_VO_DISP_CTRL 0x0310 -#define SOLO_VO_DISP_ON (1<<31) +#define SOLO_VO_DISP_ON BIT(31) #define SOLO_VO_DISP_ERASE_COUNT(n) ((n&0xf)<<24) -#define SOLO_VO_DISP_DOUBLE_SCAN (1<<22) -#define SOLO_VO_DISP_SINGLE_PAGE (1<<21) +#define SOLO_VO_DISP_DOUBLE_SCAN BIT(22) +#define SOLO_VO_DISP_SINGLE_PAGE BIT(21) #define SOLO_VO_DISP_BASE(n) (((n)>>16) & 0xffff) #define SOLO_VO_DISP_ERASE 0x0314 -#define SOLO_VO_DISP_ERASE_ON (1<<0) +#define SOLO_VO_DISP_ERASE_ON BIT(0) #define SOLO_VO_ZOOM_CTRL 0x0318 -#define SOLO_VO_ZOOM_VER_ON (1<<24) -#define SOLO_VO_ZOOM_HOR_ON (1<<23) -#define SOLO_VO_ZOOM_V_COMP (1<<22) +#define SOLO_VO_ZOOM_VER_ON BIT(24) +#define SOLO_VO_ZOOM_HOR_ON BIT(23) +#define SOLO_VO_ZOOM_V_COMP BIT(22) #define SOLO_VO_ZOOM_SX(h) (((h)/2)<<11) #define SOLO_VO_ZOOM_SY(v) (((v)/2)<<0) #define SOLO_VO_FREEZE_CTRL 0x031C -#define SOLO_VO_FREEZE_ON (1<<1) -#define SOLO_VO_FREEZE_INTERPOLATION (1<<0) +#define SOLO_VO_FREEZE_ON BIT(1) +#define SOLO_VO_FREEZE_INTERPOLATION BIT(0) #define SOLO_VO_BKG_COLOR 0x0320 #define SOLO_BG_Y(y) ((y)<<16) @@ -334,8 +336,8 @@ #define SOLO_VO_EXPANSION(id) (0x0250+((id)*4)) #define SOLO_OSG_CONFIG 0x03E0 -#define SOLO_VO_OSG_ON (1<<31) -#define SOLO_VO_OSG_COLOR_MUTE (1<<28) +#define SOLO_VO_OSG_ON BIT(31) +#define SOLO_VO_OSG_COLOR_MUTE BIT(28) #define SOLO_VO_OSG_ALPHA_RATE(n) ((n)<<22) #define SOLO_VO_OSG_ALPHA_BG_RATE(n) ((n)<<16) #define SOLO_VO_OSG_BASE(offset) (((offset)>>16)&0xffff) @@ -345,8 +347,8 @@ #define SOLO_OSG_ERASE_OFF (0x00) #define SOLO_VO_OSG_BLINK 0x03E8 -#define SOLO_VO_OSG_BLINK_ON (1<<1) -#define SOLO_VO_OSG_BLINK_INTREVAL18 (1<<0) +#define SOLO_VO_OSG_BLINK_ON BIT(1) +#define SOLO_VO_OSG_BLINK_INTREVAL18 BIT(0) #define SOLO_CAP_BASE 0x0400 #define SOLO_CAP_MAX_PAGE(n) ((n)<<16) @@ -374,19 +376,19 @@ #define SOLO_VE_CFG0 0x0610 -#define SOLO_VE_TWO_PAGE_MODE (1<<31) +#define SOLO_VE_TWO_PAGE_MODE BIT(31) #define SOLO_VE_INTR_CTRL(n) ((n)<<24) #define SOLO_VE_BLOCK_SIZE(n) ((n)<<16) #define SOLO_VE_BLOCK_BASE(n) ((n)<<0) #define SOLO_VE_CFG1 0x0614 #define SOLO_VE_BYTE_ALIGN(n) ((n)<<24) -#define SOLO_VE_INSERT_INDEX (1<<18) +#define SOLO_VE_INSERT_INDEX BIT(18) #define SOLO_VE_MOTION_MODE(n) ((n)<<16) #define SOLO_VE_MOTION_BASE(n) ((n)<<0) #define SOLO_VE_MPEG_SIZE_H(n) ((n)<<28) /* 6110 Only */ #define SOLO_VE_JPEG_SIZE_H(n) ((n)<<20) /* 6110 Only */ -#define SOLO_VE_INSERT_INDEX_JPEG (1<<19) /* 6110 Only */ +#define SOLO_VE_INSERT_INDEX_JPEG BIT(19) /* 6110 Only */ #define SOLO_VE_WMRK_POLY 0x061C #define SOLO_VE_VMRK_INIT_KEY 0x0620 @@ -394,8 +396,8 @@ #define SOLO_VE_ENCRYP_POLY 0x0628 #define SOLO_VE_ENCRYP_INIT 0x062C #define SOLO_VE_ATTR 0x0630 -#define SOLO_VE_LITTLE_ENDIAN (1<<31) -#define SOLO_COMP_ATTR_RN (1<<30) +#define SOLO_VE_LITTLE_ENDIAN BIT(31) +#define SOLO_COMP_ATTR_RN BIT(30) #define SOLO_COMP_ATTR_FCODE(n) ((n)<<27) #define SOLO_COMP_TIME_INC(n) ((n)<<25) #define SOLO_COMP_TIME_WIDTH(n) ((n)<<21) @@ -416,9 +418,9 @@ #define SOLO_VE_OSD_BASE 0x0694 #define SOLO_VE_OSD_CLR 0x0698 #define SOLO_VE_OSD_OPT 0x069C -#define SOLO_VE_OSD_V_DOUBLE (1<<16) /* 6110 Only */ -#define SOLO_VE_OSD_H_SHADOW (1<<15) -#define SOLO_VE_OSD_V_SHADOW (1<<14) +#define SOLO_VE_OSD_V_DOUBLE BIT(16) /* 6110 Only */ +#define SOLO_VE_OSD_H_SHADOW BIT(15) +#define SOLO_VE_OSD_V_SHADOW BIT(14) #define SOLO_VE_OSD_H_OFFSET(n) ((n & 0x7f)<<7) #define SOLO_VE_OSD_V_OFFSET(n) (n & 0x7f) @@ -435,18 +437,18 @@ #define SOLO_VE_JPEG_QUE(n) (0x0A04+((n)*8)) #define SOLO_VD_CFG0 0x0900 -#define SOLO_VD_CFG_NO_WRITE_NO_WINDOW (1<<24) -#define SOLO_VD_CFG_BUSY_WIAT_CODE (1<<23) -#define SOLO_VD_CFG_BUSY_WIAT_REF (1<<22) -#define SOLO_VD_CFG_BUSY_WIAT_RES (1<<21) -#define SOLO_VD_CFG_BUSY_WIAT_MS (1<<20) -#define SOLO_VD_CFG_SINGLE_MODE (1<<18) -#define SOLO_VD_CFG_SCAL_MANUAL (1<<17) -#define SOLO_VD_CFG_USER_PAGE_CTRL (1<<16) -#define SOLO_VD_CFG_LITTLE_ENDIAN (1<<15) -#define SOLO_VD_CFG_START_FI (1<<14) -#define SOLO_VD_CFG_ERR_LOCK (1<<13) -#define SOLO_VD_CFG_ERR_INT_ENA (1<<12) +#define SOLO_VD_CFG_NO_WRITE_NO_WINDOW BIT(24) +#define SOLO_VD_CFG_BUSY_WIAT_CODE BIT(23) +#define SOLO_VD_CFG_BUSY_WIAT_REF BIT(22) +#define SOLO_VD_CFG_BUSY_WIAT_RES BIT(21) +#define SOLO_VD_CFG_BUSY_WIAT_MS BIT(20) +#define SOLO_VD_CFG_SINGLE_MODE BIT(18) +#define SOLO_VD_CFG_SCAL_MANUAL BIT(17) +#define SOLO_VD_CFG_USER_PAGE_CTRL BIT(16) +#define SOLO_VD_CFG_LITTLE_ENDIAN BIT(15) +#define SOLO_VD_CFG_START_FI BIT(14) +#define SOLO_VD_CFG_ERR_LOCK BIT(13) +#define SOLO_VD_CFG_ERR_INT_ENA BIT(12) #define SOLO_VD_CFG_TIME_WIDTH(n) ((n)<<8) #define SOLO_VD_CFG_DCT_INTERVAL(n) ((n)<<0) @@ -459,37 +461,37 @@ #define SOLO_VD_CODE_ADR 0x090C #define SOLO_VD_CTRL 0x0910 -#define SOLO_VD_OPER_ON (1<<31) +#define SOLO_VD_OPER_ON BIT(31) #define SOLO_VD_MAX_ITEM(n) ((n)<<0) #define SOLO_VD_STATUS0 0x0920 -#define SOLO_VD_STATUS0_INTR_ACK (1<<22) -#define SOLO_VD_STATUS0_INTR_EMPTY (1<<21) -#define SOLO_VD_STATUS0_INTR_ERR (1<<20) +#define SOLO_VD_STATUS0_INTR_ACK BIT(22) +#define SOLO_VD_STATUS0_INTR_EMPTY BIT(21) +#define SOLO_VD_STATUS0_INTR_ERR BIT(20) #define SOLO_VD_STATUS1 0x0924 #define SOLO_VD_IDX0 0x0930 -#define SOLO_VD_IDX_INTERLACE (1<<30) +#define SOLO_VD_IDX_INTERLACE BIT(30) #define SOLO_VD_IDX_CHANNEL(n) ((n)<<24) #define SOLO_VD_IDX_SIZE(n) ((n)<<0) #define SOLO_VD_IDX1 0x0934 #define SOLO_VD_IDX_SRC_SCALE(n) ((n)<<28) #define SOLO_VD_IDX_WINDOW(n) ((n)<<24) -#define SOLO_VD_IDX_DEINTERLACE (1<<16) +#define SOLO_VD_IDX_DEINTERLACE BIT(16) #define SOLO_VD_IDX_H_BLOCK(n) ((n)<<8) #define SOLO_VD_IDX_V_BLOCK(n) ((n)<<0) #define SOLO_VD_IDX2 0x0938 -#define SOLO_VD_IDX_REF_BASE_SIDE (1<<31) +#define SOLO_VD_IDX_REF_BASE_SIDE BIT(31) #define SOLO_VD_IDX_REF_BASE(n) (((n)>>16)&0xffff) #define SOLO_VD_IDX3 0x093C #define SOLO_VD_IDX_DISP_SCALE(n) ((n)<<28) -#define SOLO_VD_IDX_INTERLACE_WR (1<<27) -#define SOLO_VD_IDX_INTERPOL (1<<26) -#define SOLO_VD_IDX_HOR2X (1<<25) +#define SOLO_VD_IDX_INTERLACE_WR BIT(27) +#define SOLO_VD_IDX_INTERPOL BIT(26) +#define SOLO_VD_IDX_HOR2X BIT(25) #define SOLO_VD_IDX_OFFSET_X(n) ((n)<<12) #define SOLO_VD_IDX_OFFSET_Y(n) ((n)<<0) @@ -511,21 +513,21 @@ #define SOLO_IIC_CFG 0x0B20 -#define SOLO_IIC_ENABLE (1<<8) +#define SOLO_IIC_ENABLE BIT(8) #define SOLO_IIC_PRESCALE(n) ((n)<<0) #define SOLO_IIC_CTRL 0x0B24 -#define SOLO_IIC_AUTO_CLEAR (1<<20) -#define SOLO_IIC_STATE_RX_ACK (1<<19) -#define SOLO_IIC_STATE_BUSY (1<<18) -#define SOLO_IIC_STATE_SIG_ERR (1<<17) -#define SOLO_IIC_STATE_TRNS (1<<16) +#define SOLO_IIC_AUTO_CLEAR BIT(20) +#define SOLO_IIC_STATE_RX_ACK BIT(19) +#define SOLO_IIC_STATE_BUSY BIT(18) +#define SOLO_IIC_STATE_SIG_ERR BIT(17) +#define SOLO_IIC_STATE_TRNS BIT(16) #define SOLO_IIC_CH_SET(n) ((n)<<5) -#define SOLO_IIC_ACK_EN (1<<4) -#define SOLO_IIC_START (1<<3) -#define SOLO_IIC_STOP (1<<2) -#define SOLO_IIC_READ (1<<1) -#define SOLO_IIC_WRITE (1<<0) +#define SOLO_IIC_ACK_EN BIT(4) +#define SOLO_IIC_START BIT(3) +#define SOLO_IIC_STOP BIT(2) +#define SOLO_IIC_READ BIT(1) +#define SOLO_IIC_WRITE BIT(0) #define SOLO_IIC_TXD 0x0B28 #define SOLO_IIC_RXD 0x0B2C @@ -535,15 +537,15 @@ */ #define SOLO_UART_CONTROL(n) (0x0BA0 + ((n)*0x20)) #define SOLO_UART_CLK_DIV(n) ((n)<<24) -#define SOLO_MODEM_CTRL_EN (1<<20) -#define SOLO_PARITY_ERROR_DROP (1<<18) -#define SOLO_IRQ_ERR_EN (1<<17) -#define SOLO_IRQ_RX_EN (1<<16) -#define SOLO_IRQ_TX_EN (1<<15) -#define SOLO_RX_EN (1<<14) -#define SOLO_TX_EN (1<<13) -#define SOLO_UART_HALF_DUPLEX (1<<12) -#define SOLO_UART_LOOPBACK (1<<11) +#define SOLO_MODEM_CTRL_EN BIT(20) +#define SOLO_PARITY_ERROR_DROP BIT(18) +#define SOLO_IRQ_ERR_EN BIT(17) +#define SOLO_IRQ_RX_EN BIT(16) +#define SOLO_IRQ_TX_EN BIT(15) +#define SOLO_RX_EN BIT(14) +#define SOLO_TX_EN BIT(13) +#define SOLO_UART_HALF_DUPLEX BIT(12) +#define SOLO_UART_LOOPBACK BIT(11) #define SOLO_BAUDRATE_230400 ((0<<9)|(0<<6)) #define SOLO_BAUDRATE_115200 ((0<<9)|(1<<6)) @@ -569,12 +571,12 @@ #define SOLO_UART_PARITY_ODD (3<<0) #define SOLO_UART_STATUS(n) (0x0BA4 + ((n)*0x20)) -#define SOLO_UART_CTS (1<<15) -#define SOLO_UART_RX_BUSY (1<<14) -#define SOLO_UART_OVERRUN (1<<13) -#define SOLO_UART_FRAME_ERR (1<<12) -#define SOLO_UART_PARITY_ERR (1<<11) -#define SOLO_UART_TX_BUSY (1<<5) +#define SOLO_UART_CTS BIT(15) +#define SOLO_UART_RX_BUSY BIT(14) +#define SOLO_UART_OVERRUN BIT(13) +#define SOLO_UART_FRAME_ERR BIT(12) +#define SOLO_UART_PARITY_ERR BIT(11) +#define SOLO_UART_TX_BUSY BIT(5) #define SOLO_UART_RX_BUFF_CNT(stat) (((stat)>>6) & 0x1f) #define SOLO_UART_RX_BUFF_SIZE 8 @@ -582,9 +584,9 @@ #define SOLO_UART_TX_BUFF_SIZE 8 #define SOLO_UART_TX_DATA(n) (0x0BA8 + ((n)*0x20)) -#define SOLO_UART_TX_DATA_PUSH (1<<8) +#define SOLO_UART_TX_DATA_PUSH BIT(8) #define SOLO_UART_RX_DATA(n) (0x0BAC + ((n)*0x20)) -#define SOLO_UART_RX_DATA_POP (1<<8) +#define SOLO_UART_RX_DATA_POP BIT(8) #define SOLO_TIMER_CLOCK_NUM 0x0be0 #define SOLO_TIMER_USEC 0x0be8 @@ -592,19 +594,19 @@ #define SOLO_TIMER_USEC_LSB 0x0d20 /* 6110 Only */ #define SOLO_AUDIO_CONTROL 0x0D00 -#define SOLO_AUDIO_ENABLE (1<<31) -#define SOLO_AUDIO_MASTER_MODE (1<<30) -#define SOLO_AUDIO_I2S_MODE (1<<29) -#define SOLO_AUDIO_I2S_LR_SWAP (1<<27) -#define SOLO_AUDIO_I2S_8BIT (1<<26) +#define SOLO_AUDIO_ENABLE BIT(31) +#define SOLO_AUDIO_MASTER_MODE BIT(30) +#define SOLO_AUDIO_I2S_MODE BIT(29) +#define SOLO_AUDIO_I2S_LR_SWAP BIT(27) +#define SOLO_AUDIO_I2S_8BIT BIT(26) #define SOLO_AUDIO_I2S_MULTI(n) ((n)<<24) -#define SOLO_AUDIO_MIX_9TO0 (1<<23) +#define SOLO_AUDIO_MIX_9TO0 BIT(23) #define SOLO_AUDIO_DEC_9TO0_VOL(n) ((n)<<20) -#define SOLO_AUDIO_MIX_19TO10 (1<<19) +#define SOLO_AUDIO_MIX_19TO10 BIT(19) #define SOLO_AUDIO_DEC_19TO10_VOL(n) ((n)<<16) #define SOLO_AUDIO_MODE(n) ((n)<<0) #define SOLO_AUDIO_SAMPLE 0x0D04 -#define SOLO_AUDIO_EE_MODE_ON (1<<30) +#define SOLO_AUDIO_EE_MODE_ON BIT(30) #define SOLO_AUDIO_EE_ENC_CH(ch) ((ch)<<25) #define SOLO_AUDIO_BITRATE(n) ((n)<<16) #define SOLO_AUDIO_CLK_DIV(n) ((n)<<0) |