diff options
| author | Fabrice Gasnier <fabrice.gasnier@st.com> | 2019-12-02 10:02:19 +0100 |
|---|---|---|
| committer | Jonathan Cameron <Jonathan.Cameron@huawei.com> | 2019-12-15 11:42:17 +0000 |
| commit | cc06e67d8fa55d000caeb4613e8873aed2c171ff (patch) | |
| tree | 7df9765b6012c65120a948b93710dfa922673633 /drivers/iio/adc/stm32-adc-core.h | |
| parent | 4cf01d6d4eea2e3841aeaa4cb977e73ab5efab10 (diff) | |
iio: adc: stm32-adc: Add check on overrun interrupt
Enable overrun interrupt on STM32 ADC. In case data register hasn't been
read (by CPU or DMA), overrun condition is detected when there's new
conversion data available. Stop grabbing data and log an error message.
Use a threaded irq to avoid printing the error message from hard irq
context.
Signed-off-by: Fabrice Gasnier <fabrice.gasnier@st.com>
Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
Diffstat (limited to 'drivers/iio/adc/stm32-adc-core.h')
| -rw-r--r-- | drivers/iio/adc/stm32-adc-core.h | 9 |
1 files changed, 9 insertions, 0 deletions
diff --git a/drivers/iio/adc/stm32-adc-core.h b/drivers/iio/adc/stm32-adc-core.h index 2579d514c2a3..2322809bfd2f 100644 --- a/drivers/iio/adc/stm32-adc-core.h +++ b/drivers/iio/adc/stm32-adc-core.h @@ -51,10 +51,12 @@ #define STM32F4_ADC_CCR (STM32_ADCX_COMN_OFFSET + 0x04) /* STM32F4_ADC_SR - bit fields */ +#define STM32F4_OVR BIT(5) #define STM32F4_STRT BIT(4) #define STM32F4_EOC BIT(1) /* STM32F4_ADC_CR1 - bit fields */ +#define STM32F4_OVRIE BIT(26) #define STM32F4_RES_SHIFT 24 #define STM32F4_RES_MASK GENMASK(25, 24) #define STM32F4_SCAN BIT(8) @@ -72,8 +74,11 @@ #define STM32F4_ADON BIT(0) /* STM32F4_ADC_CSR - bit fields */ +#define STM32F4_OVR3 BIT(21) #define STM32F4_EOC3 BIT(17) +#define STM32F4_OVR2 BIT(13) #define STM32F4_EOC2 BIT(9) +#define STM32F4_OVR1 BIT(5) #define STM32F4_EOC1 BIT(1) /* STM32F4_ADC_CCR - bit fields */ @@ -103,10 +108,12 @@ /* STM32H7_ADC_ISR - bit fields */ #define STM32MP1_VREGREADY BIT(12) +#define STM32H7_OVR BIT(4) #define STM32H7_EOC BIT(2) #define STM32H7_ADRDY BIT(0) /* STM32H7_ADC_IER - bit fields */ +#define STM32H7_OVRIE STM32H7_OVR #define STM32H7_EOCIE STM32H7_EOC /* STM32H7_ADC_CR - bit fields */ @@ -155,7 +162,9 @@ enum stm32h7_adc_dmngt { #define STM32H7_LINCALFACT_MASK GENMASK(29, 0) /* STM32H7_ADC_CSR - bit fields */ +#define STM32H7_OVR_SLV BIT(20) #define STM32H7_EOC_SLV BIT(18) +#define STM32H7_OVR_MST BIT(4) #define STM32H7_EOC_MST BIT(2) /* STM32H7_ADC_CCR - bit fields */ |