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authorArd Biesheuvel <ard.biesheuvel@linaro.org>2015-11-16 13:12:48 +0100
committerCatalin Marinas <catalin.marinas@arm.com>2015-11-18 12:09:08 +0000
commit08c6781cfaa196d4b257ec043c17e8746d9284e3 (patch)
treec5e8fe42b7c13894a9271f75fa0c775a44d4567a /drivers/hid/hid-speedlink.c
parent65da0a8e34a857f2ba9ccb91dc8f8f964cf938b7 (diff)
arm64: crypto: reduce priority of core AES cipher
The asynchronous, merged implementations of AES in CBC, CTR and XTS modes are preferred when available (i.e., when instantiating ablkciphers explicitly). However, the synchronous core AES cipher combined with the generic CBC mode implementation will produce a 'cbc(aes)' blkcipher that is callable asynchronously as well. To prevent this implementation from being used when the accelerated asynchronous implemenation is also available, lower its priority to 250 (i.e., below the asynchronous module's priority of 300). Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org> Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
Diffstat (limited to 'drivers/hid/hid-speedlink.c')
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