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authorAnson Huang <Anson.Huang@nxp.com>2018-08-31 15:53:15 +0800
committerStephen Boyd <sboyd@kernel.org>2018-10-17 11:15:44 -0700
commitaac7ff2048a881975fceb41ae6545730dee310d2 (patch)
treec79043e1f4575b792d210bbb51ea11e107aa5cd2 /drivers/clk/imx
parent891f30bf603ba49ac1cf1778fedef4e9d4ee3483 (diff)
clk: imx6sll: add mmdc1 ipg clock
i.MX6SLL has MMDC1 ipg clock in CCM CCGR, add it into clock tree for clock management. Signed-off-by: Anson Huang <Anson.Huang@nxp.com> Reviewed-by: Rob Herring <robh@kernel.org> Signed-off-by: Stephen Boyd <sboyd@kernel.org>
Diffstat (limited to 'drivers/clk/imx')
-rw-r--r--drivers/clk/imx/clk-imx6sll.c1
1 files changed, 1 insertions, 0 deletions
diff --git a/drivers/clk/imx/clk-imx6sll.c b/drivers/clk/imx/clk-imx6sll.c
index 52379ee49aec..3bd2044cf25c 100644
--- a/drivers/clk/imx/clk-imx6sll.c
+++ b/drivers/clk/imx/clk-imx6sll.c
@@ -293,6 +293,7 @@ static void __init imx6sll_clocks_init(struct device_node *ccm_node)
clks[IMX6SLL_CLK_WDOG1] = imx_clk_gate2("wdog1", "ipg", base + 0x74, 16);
clks[IMX6SLL_CLK_MMDC_P0_FAST] = imx_clk_gate_flags("mmdc_p0_fast", "mmdc_podf", base + 0x74, 20, CLK_IS_CRITICAL);
clks[IMX6SLL_CLK_MMDC_P0_IPG] = imx_clk_gate2_flags("mmdc_p0_ipg", "ipg", base + 0x74, 24, CLK_IS_CRITICAL);
+ clks[IMX6SLL_CLK_MMDC_P1_IPG] = imx_clk_gate2("mmdc_p1_ipg", "ipg", base + 0x74, 26);
clks[IMX6SLL_CLK_OCRAM] = imx_clk_gate_flags("ocram","ahb", base + 0x74, 28, CLK_IS_CRITICAL);
/* CCGR4 */