diff options
| author | Matthias Brugger <mbrugger@suse.com> | 2020-12-18 11:57:07 +0100 |
|---|---|---|
| committer | Herbert Xu <herbert@gondor.apana.org.au> | 2021-01-03 08:41:37 +1100 |
| commit | 96a6af540396ed93ba231d0ae2e6fe196dc22032 (patch) | |
| tree | 3e924d7e648e1830f32ac7fb516d4a347d446dfa /drivers/char | |
| parent | 5318d3db465d29efe97b0e18da29ad95156e6142 (diff) | |
hwrng: iproc-rng200 - Fix disable of the block.
When trying to disable the block we bitwise or the control
register with value zero. This is confusing as using bitwise or with
value zero doesn't have any effect at all. Drop this as we already set
the enable bit to zero by appling inverted RNG_RBGEN_MASK.
Signed-off-by: Matthias Brugger <mbrugger@suse.com>
Acked-by: Scott Branden <scott.branden@broadcom.com>
Acked-by: Florian Fainelli <f.fainelli@gmail.com>
Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
Diffstat (limited to 'drivers/char')
| -rw-r--r-- | drivers/char/hw_random/iproc-rng200.c | 3 |
1 files changed, 0 insertions, 3 deletions
diff --git a/drivers/char/hw_random/iproc-rng200.c b/drivers/char/hw_random/iproc-rng200.c index 01583faf9893..70cd818a0f31 100644 --- a/drivers/char/hw_random/iproc-rng200.c +++ b/drivers/char/hw_random/iproc-rng200.c @@ -28,7 +28,6 @@ #define RNG_CTRL_OFFSET 0x00 #define RNG_CTRL_RNG_RBGEN_MASK 0x00001FFF #define RNG_CTRL_RNG_RBGEN_ENABLE 0x00000001 -#define RNG_CTRL_RNG_RBGEN_DISABLE 0x00000000 #define RNG_SOFT_RESET_OFFSET 0x04 #define RNG_SOFT_RESET 0x00000001 @@ -61,7 +60,6 @@ static void iproc_rng200_restart(void __iomem *rng_base) /* Disable RBG */ val = ioread32(rng_base + RNG_CTRL_OFFSET); val &= ~RNG_CTRL_RNG_RBGEN_MASK; - val |= RNG_CTRL_RNG_RBGEN_DISABLE; iowrite32(val, rng_base + RNG_CTRL_OFFSET); /* Clear all interrupt status */ @@ -174,7 +172,6 @@ static void iproc_rng200_cleanup(struct hwrng *rng) /* Disable RNG hardware */ val = ioread32(priv->base + RNG_CTRL_OFFSET); val &= ~RNG_CTRL_RNG_RBGEN_MASK; - val |= RNG_CTRL_RNG_RBGEN_DISABLE; iowrite32(val, priv->base + RNG_CTRL_OFFSET); } |