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authorLoic Poulain <loic.poulain@linaro.org>2020-11-26 16:06:41 +0100
committerManivannan Sadhasivam <manivannan.sadhasivam@linaro.org>2021-01-21 13:05:53 +0530
commitf49b6aeb5c45dea3a1b6ee6a842599147dfd5929 (patch)
tree5b4991575ae1180a241988ff51f7062d2512947c /drivers/bus/mhi
parentec751369d6fbc9f84176e1530b11cbf387262b48 (diff)
bus: mhi: Ensure correct ring update ordering with memory barrier
The ring element data, though being part of coherent memory, still need to be performed before updating the ring context to point to this new element. That can be guaranteed with a memory barrier (dma_wmb). Signed-off-by: Loic Poulain <loic.poulain@linaro.org> Reviewed-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
Diffstat (limited to 'drivers/bus/mhi')
-rw-r--r--drivers/bus/mhi/core/main.c7
1 files changed, 7 insertions, 0 deletions
diff --git a/drivers/bus/mhi/core/main.c b/drivers/bus/mhi/core/main.c
index 9b425402767c..8576b0f03f2c 100644
--- a/drivers/bus/mhi/core/main.c
+++ b/drivers/bus/mhi/core/main.c
@@ -111,7 +111,14 @@ void mhi_ring_chan_db(struct mhi_controller *mhi_cntrl,
dma_addr_t db;
db = ring->iommu_base + (ring->wp - ring->base);
+
+ /*
+ * Writes to the new ring element must be visible to the hardware
+ * before letting h/w know there is new element to fetch.
+ */
+ dma_wmb();
*ring->ctxt_wp = db;
+
mhi_chan->db_cfg.process_db(mhi_cntrl, &mhi_chan->db_cfg,
ring->db_addr, db);
}