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authorUwe Kleine-König <u.kleine-koenig@pengutronix.de>2015-02-21 11:40:23 +0100
committerMichael Turquette <mturquette@linaro.org>2015-03-09 14:19:27 -0700
commitda321133b53caf7889ed3ca1dabe4cc368db2604 (patch)
tree8684dc2cedc502ebd6066418833d4a59ad4c6e2a /drivers/auxdisplay
parent2f7bf4af5c8177f6a27d9b67efdeb48f5bdbf821 (diff)
clk: divider: fix calculation of maximal parent rate for a given divider
The rate provided at the output of a clk-divider is calculated as: DIV_ROUND_UP(parent_rate, div) since commit b11d282dbea2 (clk: divider: fix rate calculation for fractional rates). So to yield a rate not bigger than r parent_rate must be <= r * div. The effect of choosing a parent rate that is too big as was done before this patch results in wrongly ruling out good dividers. Note that this is not a complete fix as __clk_round_rate might return a value >= its 2nd parameter. Also for dividers with CLK_DIVIDER_ROUND_CLOSEST set the calculation is not accurate. But this fixes the test case by Sascha Hauer that uses a chain of three dividers under a fixed clock. Fixes: b11d282dbea2 (clk: divider: fix rate calculation for fractional rates) Suggested-by: Sascha Hauer <s.hauer@pengutronix.de> Signed-off-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de> Acked-by: Sascha Hauer <s.hauer@pengutronix.de> Signed-off-by: Michael Turquette <mturquette@linaro.org>
Diffstat (limited to 'drivers/auxdisplay')
0 files changed, 0 insertions, 0 deletions