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authorA.s. Dong <aisheng.dong@nxp.com>2018-11-14 13:01:47 +0000
committerStephen Boyd <sboyd@kernel.org>2018-12-03 11:31:32 -0800
commit9fcb6be3b6c994f275761b22800e4244f610bdc5 (patch)
treec2519ef24df87c69edffa201947c55dcd3b6a098 /crypto/drbg.c
parentd9a8f950b296729b88d7139904cac5fd6d0a5261 (diff)
clk: imx: add pfdv2 support
The pfdv2 is designed for PLL Fractional Divide (PFD) observed in System Clock Generation (SCG) module in IMX ULP SoC series. e.g. i.MX7ULP. NOTE pfdv2 can only be operated when clk is gated. Cc: Stephen Boyd <sboyd@codeaurora.org> Cc: Michael Turquette <mturquette@baylibre.com> Cc: Shawn Guo <shawnguo@kernel.org> Cc: Anson Huang <Anson.Huang@nxp.com> Cc: Bai Ping <ping.bai@nxp.com> Signed-off-by: Dong Aisheng <aisheng.dong@nxp.com> [sboyd@kernel.org: Include clk.h for sparse warnings] Signed-off-by: Stephen Boyd <sboyd@kernel.org>
Diffstat (limited to 'crypto/drbg.c')
0 files changed, 0 insertions, 0 deletions