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authorAndrew Murray <andrew.murray@arm.com>2020-03-02 18:17:50 +0000
committerWill Deacon <will@kernel.org>2020-03-17 22:46:14 +0000
commit8e35aa642ee4dab01b16cc4b2df59d1936f3b3c2 (patch)
treeb58ce330f5e413d1065fd6b41267a04a496919d6 /block/elevator.c
parent29227d6ea1572b160e5bea45b3c93a0346444dfa (diff)
arm64: cpufeature: Extract capped perfmon fields
When emulating ID registers there is often a need to cap the version bits of a feature such that the guest will not use features that the host is not aware of. For example, when KVM mediates access to the PMU by emulating register accesses. Let's add a helper that extracts a performance monitors ID field and caps the version to a given value. Fields that identify the version of the Performance Monitors Extension do not follow the standard ID scheme, and instead follow the scheme described in ARM DDI 0487E.a page D13-2825 "Alternative ID scheme used for the Performance Monitors Extension version". The value 0xF means an IMPLEMENTATION DEFINED PMU is present, and values 0x0-OxE can be treated the same as an unsigned field with 0x0 meaning no PMU is present. Signed-off-by: Andrew Murray <andrew.murray@arm.com> Reviewed-by: Suzuki K Poulose <suzuki.poulose@arm.com> [Mark: rework to handle perfmon fields] Signed-off-by: Mark Rutland <mark.rutland@arm.com> Signed-off-by: Will Deacon <will@kernel.org>
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