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authorThierry Reding <treding@nvidia.com>2015-11-23 16:21:43 +0100
committerThierry Reding <treding@nvidia.com>2016-07-14 16:20:20 +0200
commit7596723ecd54456da4b8bc5afc4a961aa09bd34b (patch)
treeb07fd346e47ab4b4db44a76bb4a98ed5afb9970b /arch
parent6d5aef5b9517974a181d06b0bed4bc66b32f3660 (diff)
arm64: tegra: Add DSI panel on Jetson TX1
Some variants of the Jetson TX1 ship with a 8.0" WUXGA TFT LCD panel connected via four DSI lanes. Signed-off-by: Thierry Reding <treding@nvidia.com>
Diffstat (limited to 'arch')
-rw-r--r--arch/arm64/boot/dts/nvidia/tegra210-p2371-2180.dts45
-rw-r--r--arch/arm64/boot/dts/nvidia/tegra210-p2597.dtsi50
2 files changed, 95 insertions, 0 deletions
diff --git a/arch/arm64/boot/dts/nvidia/tegra210-p2371-2180.dts b/arch/arm64/boot/dts/nvidia/tegra210-p2371-2180.dts
index 683b339a980c..983775e637a4 100644
--- a/arch/arm64/boot/dts/nvidia/tegra210-p2371-2180.dts
+++ b/arch/arm64/boot/dts/nvidia/tegra210-p2371-2180.dts
@@ -6,4 +6,49 @@
/ {
model = "NVIDIA Jetson TX1 Developer Kit";
compatible = "nvidia,p2371-2180", "nvidia,tegra210";
+
+ host1x@50000000 {
+ dsi@54300000 {
+ status = "okay";
+
+ avdd-dsi-csi-supply = <&vdd_dsi_csi>;
+
+ panel@0 {
+ compatible = "auo,b080uan01";
+ reg = <0>;
+
+ enable-gpios = <&gpio TEGRA_GPIO(V, 2)
+ GPIO_ACTIVE_HIGH>;
+ power-supply = <&vdd_5v0_io>;
+ backlight = <&backlight>;
+ };
+ };
+ };
+
+ i2c@7000c400 {
+ backlight: backlight@2c {
+ compatible = "ti,lp8557";
+ reg = <0x2c>;
+
+ dev-ctrl = /bits/ 8 <0x80>;
+ init-brt = /bits/ 8 <0xff>;
+
+ pwm-period = <29334>;
+
+ pwms = <&pwm 0 29334>;
+ pwm-names = "lp8557";
+
+ /* 3 LED string */
+ rom_14h {
+ rom-addr = /bits/ 8 <0x14>;
+ rom-val = /bits/ 8 <0x87>;
+ };
+
+ /* boost frequency 1 MHz */
+ rom_13h {
+ rom-addr = /bits/ 8 <0x13>;
+ rom-val = /bits/ 8 <0x01>;
+ };
+ };
+ };
};
diff --git a/arch/arm64/boot/dts/nvidia/tegra210-p2597.dtsi b/arch/arm64/boot/dts/nvidia/tegra210-p2597.dtsi
index b28aff5e104d..78a16a57fec7 100644
--- a/arch/arm64/boot/dts/nvidia/tegra210-p2597.dtsi
+++ b/arch/arm64/boot/dts/nvidia/tegra210-p2597.dtsi
@@ -1261,6 +1261,23 @@
};
};
+ pwm@7000a000 {
+ status = "okay";
+ };
+
+ i2c@7000c400 {
+ status = "okay";
+ clock-frequency = <100000>;
+
+ exp1: gpio@74 {
+ compatible = "ti,tca9539";
+ reg = <0x74>;
+
+ #gpio-cells = <2>;
+ gpio-controller;
+ };
+ };
+
/* MMC/SD */
sdhci@700b0000 {
status = "okay";
@@ -1340,6 +1357,39 @@
regulator-enable-ramp-delay = <472>;
regulator-disable-ramp-delay = <4880>;
};
+
+ vdd_dsi_csi: regulator@5 {
+ compatible = "regulator-fixed";
+ reg = <5>;
+ regulator-name = "AVDD_DSI_CSI_1V2";
+ regulator-min-microvolt = <1200000>;
+ regulator-max-microvolt = <1200000>;
+ vin-supply = <&vdd_sys_1v2>;
+ };
+
+ vdd_3v3_dis: regulator@6 {
+ compatible = "regulator-fixed";
+ reg = <6>;
+ regulator-name = "VDD_DIS_3V3_LCD";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-always-on;
+ gpio = <&exp1 3 GPIO_ACTIVE_HIGH>;
+ enable-active-high;
+ vin-supply = <&vdd_3v3_sys>;
+ };
+
+ vdd_1v8_dis: regulator@7 {
+ compatible = "regulator-fixed";
+ reg = <7>;
+ regulator-name = "VDD_LCD_1V8_DIS";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-always-on;
+ gpio = <&exp1 14 GPIO_ACTIVE_HIGH>;
+ enable-active-high;
+ vin-supply = <&vdd_1v8>;
+ };
};
gpio-keys {