diff options
| author | Paul Burton <paul.burton@imgtec.com> | 2014-02-13 11:27:42 +0000 |
|---|---|---|
| committer | Ralf Baechle <ralf@linux-mips.org> | 2014-03-26 23:09:11 +0100 |
| commit | eec43a224cf198c7e3538fca16f689e4d17d4471 (patch) | |
| tree | 24d9236c0cd33dcf7862c09799910e8bbf5abde9 /arch/mips/include/uapi | |
| parent | a8ad136789b4256fa372d59daaddb91b72aa0753 (diff) | |
MIPS: Save/restore MSA context around signals
This patch extends sigcontext in order to hold the most significant 64
bits of each vector register in addition to the MSA control & status
register. The least significant 64 bits are already saved as the scalar
FP context. This makes things a little awkward since the least & most
significant 64 bits of each vector register are not contiguous in
memory. Thus the copy_u & insert instructions are used to transfer the
values of the most significant 64 bits via GP registers.
Signed-off-by: Paul Burton <paul.burton@imgtec.com>
Cc: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/6533/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
Diffstat (limited to 'arch/mips/include/uapi')
| -rw-r--r-- | arch/mips/include/uapi/asm/sigcontext.h | 8 |
1 files changed, 8 insertions, 0 deletions
diff --git a/arch/mips/include/uapi/asm/sigcontext.h b/arch/mips/include/uapi/asm/sigcontext.h index 6c9906f59c6e..681c17603a48 100644 --- a/arch/mips/include/uapi/asm/sigcontext.h +++ b/arch/mips/include/uapi/asm/sigcontext.h @@ -12,6 +12,10 @@ #include <linux/types.h> #include <asm/sgidefs.h> +/* Bits which may be set in sc_used_math */ +#define USEDMATH_FP (1 << 0) +#define USEDMATH_MSA (1 << 1) + #if _MIPS_SIM == _MIPS_SIM_ABI32 /* @@ -37,6 +41,8 @@ struct sigcontext { unsigned long sc_lo2; unsigned long sc_hi3; unsigned long sc_lo3; + unsigned long long sc_msaregs[32]; /* Most significant 64 bits */ + unsigned long sc_msa_csr; }; #endif /* _MIPS_SIM == _MIPS_SIM_ABI32 */ @@ -70,6 +76,8 @@ struct sigcontext { __u32 sc_used_math; __u32 sc_dsp; __u32 sc_reserved; + __u64 sc_msaregs[32]; + __u32 sc_msa_csr; }; |