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| author | Sergei Shtylyov <sergei.shtylyov@cogentembedded.com> | 2017-09-15 22:43:20 +0300 |
|---|---|---|
| committer | Simon Horman <horms+renesas@verge.net.au> | 2017-09-18 11:21:53 +0200 |
| commit | 41f4345a6111056341346742942df3f5d5be535d (patch) | |
| tree | 10414f64022e7b855647aaa8d7e0f7bafc8a86d7 /arch/microblaze/Makefile | |
| parent | f9ba0c4cfe6169b7cc9a2f9653c76b05316f0508 (diff) | |
arm64: dts: renesas: initial R8A77970 SoC device tree
The initial R8A77970 SoC device tree including Cortex-A53 CPU, GIC, timer,
CPG, RST, and SYSC.
Based on the original (and large) patch by Daisuke Matsushita
<daisuke.matsushita.ns@hitachi.com>.
Signed-off-by: Vladimir Barinov <vladimir.barinov@cogentembedded.com>
Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
Diffstat (limited to 'arch/microblaze/Makefile')
0 files changed, 0 insertions, 0 deletions