diff options
| author | Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> | 2019-05-03 11:15:07 +0200 |
|---|---|---|
| committer | Dinh Nguyen <dinguyen@kernel.org> | 2019-11-22 12:12:10 -0600 |
| commit | 716864586c6261b079a4d5ebc02f19adc8e6aa38 (patch) | |
| tree | c2808e19398c8f94f574727369294ece1beae4b2 /arch/arm | |
| parent | 54ecb8f7028c5eb3d740bb82b0f1d90f2df63c5c (diff) | |
arm: socfpga: execute cold reboot by default
This changes system reboot for socfpga to issue a cold reboot by
default instead of a warm reboot.
Warm reboot can still be used by setting reboot_mode to
REBOOT_WARM (e.g. via kernel command line 'reboot='), but this
patch ensures cold reboot is issued for both REBOOT_COLD and
REBOOT_HARD.
Also, cold reboot is more fail safe than warm reboot has some
issues at least fo CSEL=0 and BSEL=qspi, where the boot rom does
not set the qspi clock to a valid range.
Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
Signed-off-by: Dinh Nguyen <dinguyen@kernel.org>
Diffstat (limited to 'arch/arm')
| -rw-r--r-- | arch/arm/mach-socfpga/socfpga.c | 12 |
1 files changed, 6 insertions, 6 deletions
diff --git a/arch/arm/mach-socfpga/socfpga.c b/arch/arm/mach-socfpga/socfpga.c index 47ebcc8a5085..9e4cb2ffd580 100644 --- a/arch/arm/mach-socfpga/socfpga.c +++ b/arch/arm/mach-socfpga/socfpga.c @@ -73,10 +73,10 @@ static void socfpga_cyclone5_restart(enum reboot_mode mode, const char *cmd) temp = readl(rst_manager_base_addr + SOCFPGA_RSTMGR_CTRL); - if (mode == REBOOT_HARD) - temp |= RSTMGR_CTRL_SWCOLDRSTREQ; - else + if (mode == REBOOT_WARM) temp |= RSTMGR_CTRL_SWWARMRSTREQ; + else + temp |= RSTMGR_CTRL_SWCOLDRSTREQ; writel(temp, rst_manager_base_addr + SOCFPGA_RSTMGR_CTRL); } @@ -86,10 +86,10 @@ static void socfpga_arria10_restart(enum reboot_mode mode, const char *cmd) temp = readl(rst_manager_base_addr + SOCFPGA_A10_RSTMGR_CTRL); - if (mode == REBOOT_HARD) - temp |= RSTMGR_CTRL_SWCOLDRSTREQ; - else + if (mode == REBOOT_WARM) temp |= RSTMGR_CTRL_SWWARMRSTREQ; + else + temp |= RSTMGR_CTRL_SWCOLDRSTREQ; writel(temp, rst_manager_base_addr + SOCFPGA_A10_RSTMGR_CTRL); } |