diff options
| author | Johan Jonker <jbx6244@gmail.com> | 2020-04-28 22:30:03 +0200 |
|---|---|---|
| committer | Heiko Stuebner <heiko@sntech.de> | 2020-05-19 10:17:51 +0200 |
| commit | 2b99e6196663199409540fb95798dba464e34343 (patch) | |
| tree | e4735ec869fc3ca354456b5a13ad30cc5f6669a6 /arch/arm64/boot/dts/rockchip | |
| parent | fb0ab17f1ab750d9662ec6b9fb3aa541a8ac1f5c (diff) | |
arm64: dts: rockchip: fix pd_tcpc0 and pd_tcpc1 node position on rk3399
The pd_tcpc0 and pd_tcpc1 nodes are currently a sub node of pd_vio.
In the rk3399 TRM figure of the 'Power Domain Partition' and in the
table of 'Power Domain and Voltage Domain Summary' these power domains
are positioned directly under VD_LOGIC, so fix that in 'rk3399.dtsi'.
Signed-off-by: Johan Jonker <jbx6244@gmail.com>
Reviewed-by: Caesar Wang <wxt@rock-chips.com>
Link: https://lore.kernel.org/r/20200428203003.3318-2-jbx6244@gmail.com
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Diffstat (limited to 'arch/arm64/boot/dts/rockchip')
| -rw-r--r-- | arch/arm64/boot/dts/rockchip/rk3399.dtsi | 20 |
1 files changed, 10 insertions, 10 deletions
diff --git a/arch/arm64/boot/dts/rockchip/rk3399.dtsi b/arch/arm64/boot/dts/rockchip/rk3399.dtsi index 492a35221d3d..528dfe8eff36 100644 --- a/arch/arm64/boot/dts/rockchip/rk3399.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3399.dtsi @@ -1056,6 +1056,16 @@ clocks = <&cru HCLK_SDIO>; pm_qos = <&qos_sdioaudio>; }; + pd_tcpc0@RK3399_PD_TCPD0 { + reg = <RK3399_PD_TCPD0>; + clocks = <&cru SCLK_UPHY0_TCPDCORE>, + <&cru SCLK_UPHY0_TCPDPHY_REF>; + }; + pd_tcpc1@RK3399_PD_TCPD1 { + reg = <RK3399_PD_TCPD1>; + clocks = <&cru SCLK_UPHY1_TCPDCORE>, + <&cru SCLK_UPHY1_TCPDPHY_REF>; + }; pd_usb3@RK3399_PD_USB3 { reg = <RK3399_PD_USB3>; clocks = <&cru ACLK_USB3>; @@ -1088,16 +1098,6 @@ pm_qos = <&qos_isp1_m0>, <&qos_isp1_m1>; }; - pd_tcpc0@RK3399_PD_TCPD0 { - reg = <RK3399_PD_TCPD0>; - clocks = <&cru SCLK_UPHY0_TCPDCORE>, - <&cru SCLK_UPHY0_TCPDPHY_REF>; - }; - pd_tcpc1@RK3399_PD_TCPD1 { - reg = <RK3399_PD_TCPD1>; - clocks = <&cru SCLK_UPHY1_TCPDCORE>, - <&cru SCLK_UPHY1_TCPDPHY_REF>; - }; pd_vo@RK3399_PD_VO { reg = <RK3399_PD_VO>; #address-cells = <1>; |