diff options
| author | Gregory CLEMENT <gregory.clement@free-electrons.com> | 2013-01-07 11:27:14 +0100 |
|---|---|---|
| committer | Russell King <rmk+kernel@arm.linux.org.uk> | 2013-01-07 15:04:17 +0000 |
| commit | 8b827c60a1d984ef8c3ed175c99a33dd451348ff (patch) | |
| tree | 59aac11c91a9452a3985a261f4994cf4567a3f6e /arch/arm/mm/tlb-v7.S | |
| parent | d106de38ca927f2a53cd56ef94c506e8f6bd37e1 (diff) | |
ARM: 7615/1: cache-l2x0: aurora: Invalidate during clean operation with WT enable
This patch fixes a bug for Aurora L2 cache controller when the
write-through mode is enable. For the clean operation even if we don't
have to flush the lines we still need to invalidate them.
Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
Tested-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Acked-by: Jason Cooper <jason@lakedaemon.net>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
Diffstat (limited to 'arch/arm/mm/tlb-v7.S')
0 files changed, 0 insertions, 0 deletions