diff options
| author | Rajendra Nayak <rnayak@ti.com> | 2013-10-15 12:37:50 +0530 |
|---|---|---|
| committer | Benoit Cousson <bcousson@baylibre.com> | 2013-10-20 19:16:08 +0200 |
| commit | f12ecbe2ea3c01b61e93af815723939a27511abc (patch) | |
| tree | 09bbb65d1a84c4d3a24b574f7e4f75083171676f /arch/arm/boot | |
| parent | d2afcf09e6450e41b8987cf282ffde79c40ab401 (diff) | |
ARM: dts: omap: Add reset/idle on init bindings for OMAP
On OMAP we have co-processor IPs, memory controllers,
GPIOs which control regulators and power switches to
PMIC, and SoC internal Bus IPs, some or most of which
should either not be reset or idled or both at init.
(In some cases there are erratas which prevent an IP
from being reset)
Have a way to pass this information from DT.
Update the am33xx/omap4 and omap5 dtsi files with the
new bindings for modules which either should not be
idled. reset or both. A later patch would cleanup the
same information that exists today as part of the hwmod
data files.
Signed-off-by: Rajendra Nayak <rnayak@ti.com>
Signed-off-by: Benoit Cousson <bcousson@baylibre.com>
Diffstat (limited to 'arch/arm/boot')
| -rw-r--r-- | arch/arm/boot/dts/am33xx.dtsi | 2 | ||||
| -rw-r--r-- | arch/arm/boot/dts/omap4.dtsi | 3 | ||||
| -rw-r--r-- | arch/arm/boot/dts/omap5.dtsi | 2 |
3 files changed, 7 insertions, 0 deletions
diff --git a/arch/arm/boot/dts/am33xx.dtsi b/arch/arm/boot/dts/am33xx.dtsi index 7db3c81d1563..58cf5b91a118 100644 --- a/arch/arm/boot/dts/am33xx.dtsi +++ b/arch/arm/boot/dts/am33xx.dtsi @@ -674,6 +674,7 @@ reg = <0x44d00000 0x4000 /* M3 UMEM */ 0x44d80000 0x2000>; /* M3 DMEM */ ti,hwmods = "wkup_m3"; + ti,no-reset-on-init; }; elm: elm@48080000 { @@ -713,6 +714,7 @@ gpmc: gpmc@50000000 { compatible = "ti,am3352-gpmc"; ti,hwmods = "gpmc"; + ti,no-idle-on-init; reg = <0x50000000 0x2000>; interrupts = <100>; gpmc,num-cs = <7>; diff --git a/arch/arm/boot/dts/omap4.dtsi b/arch/arm/boot/dts/omap4.dtsi index 6be1f5678f1a..6ca45b0d346b 100644 --- a/arch/arm/boot/dts/omap4.dtsi +++ b/arch/arm/boot/dts/omap4.dtsi @@ -214,6 +214,7 @@ gpmc,num-cs = <8>; gpmc,num-waitpins = <4>; ti,hwmods = "gpmc"; + ti,no-idle-on-init; }; uart1: serial@4806a000 { @@ -492,6 +493,7 @@ reg = <0x4c000000 0x100>; interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>; ti,hwmods = "emif1"; + ti,no-idle-on-init; phy-type = <1>; hw-caps-read-idle-ctrl; hw-caps-ll-interface; @@ -503,6 +505,7 @@ reg = <0x4d000000 0x100>; interrupts = <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>; ti,hwmods = "emif2"; + ti,no-idle-on-init; phy-type = <1>; hw-caps-read-idle-ctrl; hw-caps-ll-interface; diff --git a/arch/arm/boot/dts/omap5.dtsi b/arch/arm/boot/dts/omap5.dtsi index 6a558cedffd6..f518ec6b6e49 100644 --- a/arch/arm/boot/dts/omap5.dtsi +++ b/arch/arm/boot/dts/omap5.dtsi @@ -606,6 +606,7 @@ emif1: emif@4c000000 { compatible = "ti,emif-4d5"; ti,hwmods = "emif1"; + ti,no-idle-on-init; phy-type = <2>; /* DDR PHY type: Intelli PHY */ reg = <0x4c000000 0x400>; interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>; @@ -617,6 +618,7 @@ emif2: emif@4d000000 { compatible = "ti,emif-4d5"; ti,hwmods = "emif2"; + ti,no-idle-on-init; phy-type = <2>; /* DDR PHY type: Intelli PHY */ reg = <0x4d000000 0x400>; interrupts = <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>; |