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authorGeert Uytterhoeven <geert+renesas@glider.be>2016-05-03 09:37:08 +0200
committerGeert Uytterhoeven <geert+renesas@glider.be>2016-06-06 11:58:23 +0200
commit1faf8692bdc2da1e12c7f2ecda3a9e629ac9b05b (patch)
treef0baeb075c90a68398eb7367133e0943b81d7297 /Documentation
parent1a695a905c18548062509178b98bc91e67510864 (diff)
clk: renesas: cpg-mssr: Document r8a7796 support
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Acked-by: Rob Herring <robh@kernel.org> Tested-by: Simon Horman <horms+renesas@verge.net.au>
Diffstat (limited to 'Documentation')
-rw-r--r--Documentation/devicetree/bindings/clock/renesas,cpg-mssr.txt7
1 files changed, 4 insertions, 3 deletions
diff --git a/Documentation/devicetree/bindings/clock/renesas,cpg-mssr.txt b/Documentation/devicetree/bindings/clock/renesas,cpg-mssr.txt
index fefb8023020f..394d725ac7e0 100644
--- a/Documentation/devicetree/bindings/clock/renesas,cpg-mssr.txt
+++ b/Documentation/devicetree/bindings/clock/renesas,cpg-mssr.txt
@@ -13,7 +13,8 @@ They provide the following functionalities:
Required Properties:
- compatible: Must be one of:
- - "renesas,r8a7795-cpg-mssr" for the r8a7795 SoC
+ - "renesas,r8a7795-cpg-mssr" for the r8a7795 SoC (R-Car H3)
+ - "renesas,r8a7796-cpg-mssr" for the r8a7796 SoC (R-Car M3-W)
- reg: Base address and length of the memory resource used by the CPG/MSSR
block
@@ -21,8 +22,8 @@ Required Properties:
- clocks: References to external parent clocks, one entry for each entry in
clock-names
- clock-names: List of external parent clock names. Valid names are:
- - "extal" (r8a7795)
- - "extalr" (r8a7795)
+ - "extal" (r8a7795, r8a7796)
+ - "extalr" (r8a7795, r8a7796)
- #clock-cells: Must be 2
- For CPG core clocks, the two clock specifier cells must be "CPG_CORE"