diff options
| author | Stephen Boyd <sboyd@kernel.org> | 2020-06-01 13:00:56 -0700 |
|---|---|---|
| committer | Stephen Boyd <sboyd@kernel.org> | 2020-06-01 13:00:56 -0700 |
| commit | 166e4b4841974465d73d650468895b725023c81e (patch) | |
| tree | dfbfb063d0d43826da5e99a96950333213713120 /Documentation/devicetree | |
| parent | 5debcd01e28f34f0c212ed8d60f257630bec0588 (diff) | |
| parent | d63ed4ff41bb2d1f0738f801bcd9ff60dfc1eb7f (diff) | |
| parent | 56fbeefe366e5920802f60f26b6b59b365c0569b (diff) | |
| parent | 571cfadcc628dd5591444f7289e27445ea732f4c (diff) | |
| parent | 353afa3a8d2ef4a4b25db823ffd05d440b3530cb (diff) | |
Merge branches 'clk-vc5', 'clk-hsdk', 'clk-mediatek' and 'clk-baikal' into clk-next
- Support IDT VersaClock 5P49V5925
- Bunch of updates for HSDK clock generation unit (CGU) driver
- New clk driver for Baikal-T1 SoCs
* clk-vc5:
dt: Add bindings for IDT VersaClock 5P49V5925
clk: vc5: Add support for IDT VersaClock 5P49V6965
* clk-hsdk:
CLK: HSDK: CGU: add support for 148.5MHz clock
CLK: HSDK: CGU: support PLL bypassing
CLK: HSDK: CGU: check if PLL is bypassed first
* clk-mediatek:
clk: mediatek: assign the initial value to clk_init_data of mtk_mux
clk: mediatek: Add MT6765 clock support
clk: mediatek: add mt6765 clock IDs
dt-bindings: clock: mediatek: document clk bindings vcodecsys for Mediatek MT6765 SoC
dt-bindings: clock: mediatek: document clk bindings mipi0a for Mediatek MT6765 SoC
dt-bindings: clock: mediatek: document clk bindings for Mediatek MT6765 SoC
* clk-baikal:
clk: Add Baikal-T1 CCU Dividers driver
clk: Add Baikal-T1 CCU PLLs driver
dt-bindings: clk: Add Baikal-T1 CCU Dividers binding
dt-bindings: clk: Add Baikal-T1 CCU PLLs binding