diff options
| author | Rob Herring <robh@kernel.org> | 2020-05-12 15:45:43 -0500 |
|---|---|---|
| committer | Rob Herring <robh@kernel.org> | 2020-05-14 14:43:27 -0500 |
| commit | fba5618451d2b3af5e55f8af5ce9c5d3677ad9c4 (patch) | |
| tree | eb7b2e3f31c660bb1a332028319639a80a4e062b /Documentation/devicetree/bindings/phy | |
| parent | 1195b303a661f1dcfc5f97b6504d7d22a46289bc (diff) | |
dt-bindings: Fix incorrect 'reg' property sizes
The examples template is a 'simple-bus' with a size of 1 cell for
had between 2 and 4 cells which really only errors on I2C or SPI type
devices with a single cell.
The easiest fix in most cases is to change the 'reg' property to for 1 cell
address and size. In some cases with child devices having 2 cells, that
doesn't make sense so a bus node is needed.
Acked-by: Stephen Boyd <sboyd@kernel.org> # clk
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Acked-by: Geert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: Rob Herring <robh@kernel.org>
Diffstat (limited to 'Documentation/devicetree/bindings/phy')
4 files changed, 28 insertions, 22 deletions
diff --git a/Documentation/devicetree/bindings/phy/amlogic,meson-axg-mipi-pcie-analog.yaml b/Documentation/devicetree/bindings/phy/amlogic,meson-axg-mipi-pcie-analog.yaml index 88683db6cf81..18c1ec5e19ad 100644 --- a/Documentation/devicetree/bindings/phy/amlogic,meson-axg-mipi-pcie-analog.yaml +++ b/Documentation/devicetree/bindings/phy/amlogic,meson-axg-mipi-pcie-analog.yaml @@ -30,6 +30,6 @@ examples: - | mpphy: phy@0 { compatible = "amlogic,axg-mipi-pcie-analog-phy"; - reg = <0x0 0x0 0x0 0xc>; + reg = <0x0 0xc>; #phy-cells = <1>; }; diff --git a/Documentation/devicetree/bindings/phy/amlogic,meson-axg-pcie.yaml b/Documentation/devicetree/bindings/phy/amlogic,meson-axg-pcie.yaml index 086478aec946..45f3d72b1cca 100644 --- a/Documentation/devicetree/bindings/phy/amlogic,meson-axg-pcie.yaml +++ b/Documentation/devicetree/bindings/phy/amlogic,meson-axg-pcie.yaml @@ -44,7 +44,7 @@ examples: #include <dt-bindings/phy/phy.h> pcie_phy: pcie-phy@ff644000 { compatible = "amlogic,axg-pcie-phy"; - reg = <0x0 0xff644000 0x0 0x1c>; + reg = <0xff644000 0x1c>; resets = <&reset RESET_PCIE_PHY>; phys = <&mipi_analog_phy PHY_TYPE_PCIE>; phy-names = "analog"; diff --git a/Documentation/devicetree/bindings/phy/phy-cadence-torrent.yaml b/Documentation/devicetree/bindings/phy/phy-cadence-torrent.yaml index 256dd149698b..4071438be2ba 100644 --- a/Documentation/devicetree/bindings/phy/phy-cadence-torrent.yaml +++ b/Documentation/devicetree/bindings/phy/phy-cadence-torrent.yaml @@ -117,24 +117,30 @@ additionalProperties: false examples: - | #include <dt-bindings/phy/phy.h> - torrent_phy: torrent-phy@f0fb500000 { - compatible = "cdns,torrent-phy"; - reg = <0xf0 0xfb500000 0x0 0x00100000>, - <0xf0 0xfb030a00 0x0 0x00000040>; - reg-names = "torrent_phy", "dptx_phy"; - resets = <&phyrst 0>; - clocks = <&ref_clk>; - clock-names = "refclk"; - #address-cells = <1>; - #size-cells = <0>; - torrent_phy_dp: phy@0 { - reg = <0>; - resets = <&phyrst 1>, <&phyrst 2>, - <&phyrst 3>, <&phyrst 4>; - #phy-cells = <0>; - cdns,phy-type = <PHY_TYPE_DP>; - cdns,num-lanes = <4>; - cdns,max-bit-rate = <8100>; - }; + + bus { + #address-cells = <2>; + #size-cells = <2>; + + torrent-phy@f0fb500000 { + compatible = "cdns,torrent-phy"; + reg = <0xf0 0xfb500000 0x0 0x00100000>, + <0xf0 0xfb030a00 0x0 0x00000040>; + reg-names = "torrent_phy", "dptx_phy"; + resets = <&phyrst 0>; + clocks = <&ref_clk>; + clock-names = "refclk"; + #address-cells = <1>; + #size-cells = <0>; + phy@0 { + reg = <0>; + resets = <&phyrst 1>, <&phyrst 2>, + <&phyrst 3>, <&phyrst 4>; + #phy-cells = <0>; + cdns,phy-type = <PHY_TYPE_DP>; + cdns,num-lanes = <4>; + cdns,max-bit-rate = <8100>; + }; + }; }; ... diff --git a/Documentation/devicetree/bindings/phy/rockchip,px30-dsi-dphy.yaml b/Documentation/devicetree/bindings/phy/rockchip,px30-dsi-dphy.yaml index 72aca81e8959..8a3032a3bd73 100644 --- a/Documentation/devicetree/bindings/phy/rockchip,px30-dsi-dphy.yaml +++ b/Documentation/devicetree/bindings/phy/rockchip,px30-dsi-dphy.yaml @@ -59,7 +59,7 @@ examples: - | dsi_dphy: phy@ff2e0000 { compatible = "rockchip,px30-dsi-dphy"; - reg = <0x0 0xff2e0000 0x0 0x10000>; + reg = <0xff2e0000 0x10000>; clocks = <&pmucru 13>, <&cru 12>; clock-names = "ref", "pclk"; resets = <&cru 12>; |