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authorGrygorii Strashko <grygorii.strashko@ti.com>2020-03-03 18:00:26 +0200
committerKishon Vijay Abraham I <kishon@ti.com>2020-03-20 19:34:29 +0530
commit74e29703a78c120cd129e2b49ac8213713d2648c (patch)
tree6131881cbf838c435afc68ada92626b83b06fbce /Documentation/devicetree/bindings/phy/qcom-qusb2-phy.txt
parent6076967a500c4c6dad19d10d71863db1590a35ed (diff)
dt-bindings: phy: ti: gmii-sel: add support for am654x/j721e soc
TI AM654x/J721E SoCs have the same PHY interface selection mechanism for CPSWx subsystem as TI SoCs (AM3/4/5/DRA7), but registers and bit-fields placement is different. This patch adds corresponding compatible strings to enable support for TI AM654x/J721E SoCs. Signed-off-by: Grygorii Strashko <grygorii.strashko@ti.com> Acked-by: Rob Herring <robh@kernel.org> Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
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