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| author | Marcel Ziswiler <marcel.ziswiler@toradex.com> | 2018-02-22 15:38:25 +0100 |
|---|---|---|
| committer | Thierry Reding <treding@nvidia.com> | 2018-03-08 15:09:36 +0100 |
| commit | a7ca2a709dbce8ef712fc829f686672d0c0256bf (patch) | |
| tree | 935e5bd38659835421b570f8215c94c207106098 /Documentation/devicetree/bindings/phy/qcom-qmp-phy.txt | |
| parent | ff0286cbccacc300f4fb47c60a9e5629889dda04 (diff) | |
dt-bindings: phy: Clarify ULPI PHY source clock
cdev2 is not actually a clock on Tegra20 but rather a pinmux pad group.
PLL_P_OUT4 is the source clock for the ULPI PHY and is output to the
DAP_MCLK2 pad.
Signed-off-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>
Reviewed-by: Dmitry Osipenko <digetx@gmail.com>
Reviewed-by: Rob Herring <robh@kernel.org>
Signed-off-by: Thierry Reding <treding@nvidia.com>
Diffstat (limited to 'Documentation/devicetree/bindings/phy/qcom-qmp-phy.txt')
0 files changed, 0 insertions, 0 deletions