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| author | Wolfram Sang <wsa+renesas@sang-engineering.com> | 2019-12-17 12:40:33 +0100 |
|---|---|---|
| committer | Ulf Hansson <ulf.hansson@linaro.org> | 2020-03-24 14:35:38 +0100 |
| commit | 9b0d6855e756b60dd09c2a3d2a697130ffdc297d (patch) | |
| tree | 347d0be729e1baf89ab009dafd08bbe14868cd58 /Documentation/core-api/cachetlb.rst | |
| parent | 71cfc92751ac7a3185e73cffc43a673b73c39683 (diff) | |
mmc: renesas_sdhi: enforce manual correction for Gen3
HW engineers say that automatic tap correction cannot be used for HS400
in all R-Car Gen3 SoCs. So, check for that SDHI variant and disable it
when HS400 is about to be enabled.
Reviewed-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
Signed-off-by: Wolfram Sang <wsa+renesas@sang-engineering.com>
Link: https://lore.kernel.org/r/20191217114034.13290-5-wsa+renesas@sang-engineering.com
Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
Diffstat (limited to 'Documentation/core-api/cachetlb.rst')
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