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authorSowjanya Komatineni <skomatineni@nvidia.com>2020-12-21 13:17:31 -0800
committerMark Brown <broonie@kernel.org>2021-01-06 13:09:27 +0000
commitb499779761278d6f5339daa230938211d98861ef (patch)
treece8680a9c047ba4c5c2a89f7bb61dcf14eaba9d4
parent74523a5dae0c96d6503fe72da66ee37fd23eb8f5 (diff)
dt-bindings: clock: tegra: Add clock ID TEGRA210_CLK_QSPI_PM
Tegra210 QSPI clock output has divider DIV2_SEL which will be enabled when using DDR interface mode. This patch adds clock ID for this to dt-binding. Acked-by: Rob Herring <robh@kernel.org> Signed-off-by: Sowjanya Komatineni <skomatineni@nvidia.com> Link: https://lore.kernel.org/r/1608585459-17250-2-git-send-email-skomatineni@nvidia.com Signed-off-by: Mark Brown <broonie@kernel.org>
-rw-r--r--include/dt-bindings/clock/tegra210-car.h2
1 files changed, 1 insertions, 1 deletions
diff --git a/include/dt-bindings/clock/tegra210-car.h b/include/dt-bindings/clock/tegra210-car.h
index ab8b8a737a0a..9cfcc3baa52c 100644
--- a/include/dt-bindings/clock/tegra210-car.h
+++ b/include/dt-bindings/clock/tegra210-car.h
@@ -307,7 +307,7 @@
#define TEGRA210_CLK_AUDIO4 275
#define TEGRA210_CLK_SPDIF 276
/* 277 */
-/* 278 */
+#define TEGRA210_CLK_QSPI_PM 278
/* 279 */
/* 280 */
#define TEGRA210_CLK_SOR0_LVDS 281 /* deprecated */