diff options
| author | Jiri Pirko <jiri@mellanox.com> | 2019-10-31 11:42:06 +0200 |
|---|---|---|
| committer | David S. Miller <davem@davemloft.net> | 2019-10-31 10:54:46 -0700 |
| commit | 94e768373ae10d72528307256a869c846dc4ba00 (patch) | |
| tree | e1396ffd124736e5be9d19fef1ed80435445c27e | |
| parent | d74361dc58709fa200c2db86fa5cf086dc4acec8 (diff) | |
mlxsw: reg: Extend PMLP tx/rx lane value size to 4 bits
The tx/rx lane fields got extended to 4 bits, update the reg field
description accordingly.
Signed-off-by: Jiri Pirko <jiri@mellanox.com>
Reviewed-by: Shalom Toledo <shalomt@mellanox.com>
Signed-off-by: Ido Schimmel <idosch@mellanox.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
| -rw-r--r-- | drivers/net/ethernet/mellanox/mlxsw/reg.h | 5 |
1 files changed, 3 insertions, 2 deletions
diff --git a/drivers/net/ethernet/mellanox/mlxsw/reg.h b/drivers/net/ethernet/mellanox/mlxsw/reg.h index 7f7f1b95290f..7fd6fd9c5244 100644 --- a/drivers/net/ethernet/mellanox/mlxsw/reg.h +++ b/drivers/net/ethernet/mellanox/mlxsw/reg.h @@ -3969,6 +3969,7 @@ MLXSW_ITEM32(reg, pmlp, local_port, 0x00, 16, 8); * 1 - Lane 0 is used. * 2 - Lanes 0 and 1 are used. * 4 - Lanes 0, 1, 2 and 3 are used. + * 8 - Lanes 0-7 are used. * Access: RW */ MLXSW_ITEM32(reg, pmlp, width, 0x00, 0, 8); @@ -3983,14 +3984,14 @@ MLXSW_ITEM32_INDEXED(reg, pmlp, module, 0x04, 0, 8, 0x04, 0x00, false); * Tx Lane. When rxtx field is cleared, this field is used for Rx as well. * Access: RW */ -MLXSW_ITEM32_INDEXED(reg, pmlp, tx_lane, 0x04, 16, 2, 0x04, 0x00, false); +MLXSW_ITEM32_INDEXED(reg, pmlp, tx_lane, 0x04, 16, 4, 0x04, 0x00, false); /* reg_pmlp_rx_lane * Rx Lane. When rxtx field is cleared, this field is ignored and Rx lane is * equal to Tx lane. * Access: RW */ -MLXSW_ITEM32_INDEXED(reg, pmlp, rx_lane, 0x04, 24, 2, 0x04, 0x00, false); +MLXSW_ITEM32_INDEXED(reg, pmlp, rx_lane, 0x04, 24, 4, 0x04, 0x00, false); static inline void mlxsw_reg_pmlp_pack(char *payload, u8 local_port) { |