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author | Marek Szyprowski <m.szyprowski@samsung.com> | 2016-11-17 12:42:53 +0100 |
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committer | Sylwester Nawrocki <s.nawrocki@samsung.com> | 2016-11-17 13:58:49 +0100 |
commit | 4c9e92df790a2453adbdcebc4d94ef0bc4631d58 (patch) | |
tree | 568a025126584a98f44a5cae73e605c4d162cbf3 | |
parent | 9a81188e4c8abbaab92d5b77850dd855f5487440 (diff) |
clk: exynos5433: Add documentation for the audio block parent clocks
Audio block requires access to two parent clocks: audio PLL and oscillator,
so add this information to device tree bindings documentation.
Signed-off-by: Marek Szyprowski <m.szyprowski@samsung.com>
Reviewed-by: Chanwoo Choi <cw00.choi@samsung.com>
Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com>
-rw-r--r-- | Documentation/devicetree/bindings/clock/exynos5433-clock.txt | 7 |
1 files changed, 7 insertions, 0 deletions
diff --git a/Documentation/devicetree/bindings/clock/exynos5433-clock.txt b/Documentation/devicetree/bindings/clock/exynos5433-clock.txt index ffff67a0e9cd..1dc80f8811fe 100644 --- a/Documentation/devicetree/bindings/clock/exynos5433-clock.txt +++ b/Documentation/devicetree/bindings/clock/exynos5433-clock.txt @@ -104,6 +104,10 @@ Required Properties: - sclk_decon_tv_vclk_disp - aclk_disp_333 + Input clocks for audio clock controller: + - oscclk + - fout_aud_pll + Input clocks for bus0 clock controller: - aclk_bus0_400 @@ -297,6 +301,9 @@ Example 2: Examples of clock controller nodes are listed below. compatible = "samsung,exynos5433-cmu-aud"; reg = <0x114c0000 0x0b04>; #clock-cells = <1>; + + clock-names = "oscclk", "fout_aud_pll"; + clocks = <&xxti>, <&cmu_top CLK_FOUT_AUD_PLL>; }; cmu_bus0: clock-controller@13600000 { |