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authorTomasz Figa <t.figa@samsung.com>2013-04-04 13:32:43 +0900
committerKukjin Kim <kgene.kim@samsung.com>2013-04-04 15:51:08 +0900
commit4c3cc72cc7760f2aa3411e1e0f1a6cfca2659653 (patch)
tree471472a01c2738a0e0ae96901193301261465cb5
parent74f7f8ba5092a76da1e9d07f245575cef86f15ab (diff)
clk: exynos4: Add missing mout_mipihsi clock
This patch adds missing output of mux MIPIHSI which is needed for div_mipihsi clock. Signed-off-by: Tomasz Figa <t.figa@samsung.com> Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com> Reviewed-by: Thomas Abraham <thomas.abraham@linaro.org> Acked-by: Mike Turquette <mturquette@linaro.org> Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
-rw-r--r--drivers/clk/samsung/clk-exynos4.c1
1 files changed, 1 insertions, 0 deletions
diff --git a/drivers/clk/samsung/clk-exynos4.c b/drivers/clk/samsung/clk-exynos4.c
index 8edd64cb18a8..42c098df2e22 100644
--- a/drivers/clk/samsung/clk-exynos4.c
+++ b/drivers/clk/samsung/clk-exynos4.c
@@ -381,6 +381,7 @@ struct samsung_mux_clock exynos4x12_mux_clks[] __initdata = {
MUX(none, "mout_mmc2", group1_p4x12, SRC_FSYS, 8, 4),
MUX(none, "mout_mmc3", group1_p4x12, SRC_FSYS, 12, 4),
MUX(none, "mout_mmc4", group1_p4x12, SRC_FSYS, 16, 4),
+ MUX(none, "mout_mipihsi", aclk_p4412, SRC_FSYS, 24, 1),
MUX(none, "mout_uart0", group1_p4x12, SRC_PERIL0, 0, 4),
MUX(none, "mout_uart1", group1_p4x12, SRC_PERIL0, 4, 4),
MUX(none, "mout_uart2", group1_p4x12, SRC_PERIL0, 8, 4),