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| author | Mason Yang <masonccyang@mxic.com.tw> | 2019-08-19 15:19:09 +0800 |
|---|---|---|
| committer | Miquel Raynal <miquel.raynal@bootlin.com> | 2019-08-26 09:25:41 +0200 |
| commit | 220280708a2349bc8dd61ab029483d65440a5aa0 (patch) | |
| tree | 2232c64093be57139acfe83206f4d42f57976c59 | |
| parent | 738b0ca55f4f6ae1035262c2a2a605d2e9085031 (diff) | |
dt-bindings: mtd: Document Macronix raw NAND controller bindings
Document the bindings used by the Macronix raw NAND controller.
Signed-off-by: Mason Yang <masonccyang@mxic.com.tw>
Reviewed-by: Rob Herring <robh@kernel.org>
Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
| -rw-r--r-- | Documentation/devicetree/bindings/mtd/mxic-nand.txt | 36 |
1 files changed, 36 insertions, 0 deletions
diff --git a/Documentation/devicetree/bindings/mtd/mxic-nand.txt b/Documentation/devicetree/bindings/mtd/mxic-nand.txt new file mode 100644 index 000000000000..46c55295a3e6 --- /dev/null +++ b/Documentation/devicetree/bindings/mtd/mxic-nand.txt @@ -0,0 +1,36 @@ +Macronix Raw NAND Controller Device Tree Bindings +------------------------------------------------- + +Required properties: +- compatible: should be "mxic,multi-itfc-v009-nand-controller" +- reg: should contain 1 entry for the registers +- #address-cells: should be set to 1 +- #size-cells: should be set to 0 +- interrupts: interrupt line connected to this raw NAND controller +- clock-names: should contain "ps", "send" and "send_dly" +- clocks: should contain 3 phandles for the "ps", "send" and + "send_dly" clocks + +Children nodes: +- children nodes represent the available NAND chips. + +See Documentation/devicetree/bindings/mtd/nand-controller.yaml +for more details on generic bindings. + +Example: + + nand: nand-controller@43c30000 { + compatible = "mxic,multi-itfc-v009-nand-controller"; + reg = <0x43c30000 0x10000>; + #address-cells = <1>; + #size-cells = <0>; + interrupts = <GIC_SPI 0x1d IRQ_TYPE_EDGE_RISING>; + clocks = <&clkwizard 0>, <&clkwizard 1>, <&clkc 15>; + clock-names = "send", "send_dly", "ps"; + + nand@0 { + reg = <0>; + nand-ecc-mode = "soft"; + nand-ecc-algo = "bch"; + }; + }; |